d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Support the SPI mode and bus clock frequency parameters set by the devices

Browse Source 
requesting SPI transfers.

Reported by:	SAITOU Toshihide <toshi@ruby.ocn.ne.jp>
This commit is contained in:
Ian Lepore 2018-12-31 16:01:22 +00:00
parent 50757b1452
commit 584e31851a
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=342652
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
sys/arm/ti/ti_spi.c
View File

@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
{
int err;
struct ti_spi_softc *sc;
uint32_t reg, cs;
uint32_t clockhz, cs, mode, reg;
sc = device_get_softc(dev);
@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
/* Get the proper chip select for this child. */
spibus_get_cs(child, &cs);
spibus_get_clock(child, &clockhz);
spibus_get_mode(child, &mode);
cs &= ~SPIBUS_CS_HIGH;
@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
return (EINVAL);
}
if (mode > 3)
{
device_printf(dev, "Invalid mode %d requested by %s\n", mode,
device_get_nameunit(child));
return (EINVAL);
}
TI_SPI_LOCK(sc);
/* If the controller is in use wait until it is available. */
@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
/* Disable FIFO for now. */
sc->sc_fifolvl = 1;
/* Use a safe clock - 500kHz. */
ti_spi_set_clock(sc, sc->sc_cs, 500000);
/* Set the bus frequency. */
ti_spi_set_clock(sc, sc->sc_cs, clockhz);
/* Disable the FIFO. */
TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
#if 0