Support the SPI mode and bus clock frequency parameters set by the devices
requesting SPI transfers. Reported by: SAITOU Toshihide <toshi@ruby.ocn.ne.jp>
This commit is contained in:
parent
50757b1452
commit
584e31851a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342652
@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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{
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int err;
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int err;
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struct ti_spi_softc *sc;
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struct ti_spi_softc *sc;
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uint32_t reg, cs;
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uint32_t clockhz, cs, mode, reg;
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sc = device_get_softc(dev);
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sc = device_get_softc(dev);
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@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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/* Get the proper chip select for this child. */
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/* Get the proper chip select for this child. */
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spibus_get_cs(child, &cs);
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spibus_get_cs(child, &cs);
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spibus_get_clock(child, &clockhz);
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spibus_get_mode(child, &mode);
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cs &= ~SPIBUS_CS_HIGH;
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cs &= ~SPIBUS_CS_HIGH;
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@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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return (EINVAL);
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return (EINVAL);
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}
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}
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if (mode > 3)
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{
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device_printf(dev, "Invalid mode %d requested by %s\n", mode,
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device_get_nameunit(child));
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return (EINVAL);
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}
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TI_SPI_LOCK(sc);
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TI_SPI_LOCK(sc);
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/* If the controller is in use wait until it is available. */
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/* If the controller is in use wait until it is available. */
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@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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/* Disable FIFO for now. */
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/* Disable FIFO for now. */
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sc->sc_fifolvl = 1;
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sc->sc_fifolvl = 1;
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/* Use a safe clock - 500kHz. */
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/* Set the bus frequency. */
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ti_spi_set_clock(sc, sc->sc_cs, 500000);
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ti_spi_set_clock(sc, sc->sc_cs, clockhz);
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/* Disable the FIFO. */
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/* Disable the FIFO. */
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TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
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TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
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@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
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MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
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MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
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MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
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reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
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reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
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reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
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TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
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TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
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#if 0
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#if 0
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