Import device-tree files from Linux 5.14
This commit is contained in:
Emmanuel Vadot
commit
5956d97f4b
@ -167,6 +167,7 @@ properties:
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- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
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items:
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- enum:
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- bananapi,bpi-m5
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- hardkernel,odroid-c4
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- hardkernel,odroid-hc4
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- khadas,vim3l
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46
sys/contrib/device-tree/Bindings/arm/arm,scu.yaml
Normal file
46
sys/contrib/device-tree/Bindings/arm/arm,scu.yaml
Normal file
@ -0,0 +1,46 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,scu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Snoop Control Unit (SCU)
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
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with a Snoop Control Unit. The register range is usually 256 (0x100)
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bytes.
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References:
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- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
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Revision r2p0
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- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
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Revision r0p1
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- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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Manial Revision r2p0
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properties:
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compatible:
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enum:
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- arm,cortex-a9-scu
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- arm,cortex-a5-scu
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- arm,arm11mp-scu
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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scu@a0410000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xa0410000 0x100>;
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};
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@ -18,6 +18,7 @@ properties:
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- description: BCM2711 based Boards
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items:
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- enum:
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- raspberrypi,400
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- raspberrypi,4-model-b
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- const: brcm,bcm2711
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@ -257,6 +257,13 @@ properties:
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where voltage is in V, frequency is in MHz.
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performance-domains:
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maxItems: 1
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description:
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List of phandles and performance domain specifiers, as defined by
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bindings of the performance domain provider. See also
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dvfs/performance-domain.yaml.
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power-domains:
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description:
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List of phandles and PM domain specifiers, as defined by bindings of the
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@ -0,0 +1,58 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: OP-TEE Device Tree Bindings
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maintainers:
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- Jens Wiklander <jens.wiklander@linaro.org>
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description: |
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OP-TEE is a piece of software using hardware features to provide a Trusted
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Execution Environment. The security can be provided with ARM TrustZone, but
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also by virtualization or a separate chip.
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We're using "linaro" as the first part of the compatible property for
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the reference implementation maintained by Linaro.
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properties:
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$nodename:
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const: optee
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compatible:
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const: linaro,optee-tz
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method:
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enum: [smc, hvc]
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description: |
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The method of calling the OP-TEE Trusted OS depending on smc or hvc
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instruction usage.
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SMC #0, register assignments
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or
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HVC #0, register assignments
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register assignments are specified in drivers/tee/optee/optee_smc.h
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required:
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- compatible
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- method
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additionalProperties: false
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examples:
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- |
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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- |
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "hvc";
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};
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};
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@ -86,13 +86,11 @@ This binding uses the common clock binding[1].
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-clock"
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"fsl,imx8qxp-clock"
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"fsl,imx8qm-clk"
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"fsl,imx8qxp-clk"
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followed by "fsl,scu-clk"
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- #clock-cells: Should be either
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2: Contains the Resource and Clock ID value.
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or
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1: Contains the Clock ID value. (DEPRECATED)
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- #clock-cells: Should be 2.
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Contains the Resource and Clock ID value.
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- clocks: List of clock specifiers, must contain an entry for
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each required entry in clock-names
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- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
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@ -197,6 +197,7 @@ properties:
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- boundary,imx6q-nitrogen6x
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- compulab,cm-fx6 # CompuLab CM-FX6
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- dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
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- ds,imx6q-sbc # Da Sheng COM-9XX Modules
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- embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
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- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
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- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
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@ -400,6 +401,17 @@ properties:
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- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
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- const: fsl,imx6dl
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- description: i.MX6DL based congatec QMX6 Boards
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items:
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- enum:
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- ge,imx6dl-b105v2 # General Electric B105v2
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- ge,imx6dl-b105pv2 # General Electric B105Pv2
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- ge,imx6dl-b125v2 # General Electric B125v2
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- ge,imx6dl-b125pv2 # General Electric B125Pv2
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- ge,imx6dl-b155v2 # General Electric B155v2
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- const: congatec,qmx6
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- const: fsl,imx6dl
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- description: i.MX6DL based DFI FS700-M60-6DL Board
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items:
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- const: dfi,fs700-m60-6dl
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@ -685,6 +697,7 @@ properties:
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- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
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- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
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- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
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- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
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- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
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- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
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- const: fsl,imx8mm
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@ -11,6 +11,8 @@ maintainers:
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- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
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properties:
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$nodename:
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const: '/'
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compatible:
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items:
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- enum:
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@ -17,6 +17,7 @@ properties:
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- items:
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- enum:
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- linksys,nslu2
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- welltech,epbx100
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- const: intel,ixp42x
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- items:
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- enum:
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129
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.yaml
Normal file
129
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.yaml
Normal file
@ -0,0 +1,129 @@
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI-SCI controller device node bindings
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maintainers:
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- Nishanth Menon <nm@ti.com>
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description: |
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Texas Instrument's processors including those belonging to Keystone generation
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of processors have separate hardware entity which is now responsible for the
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management of the System on Chip (SoC) system. These include various system
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level functions as well.
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An example of such an SoC is K2G, which contains the system control hardware
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block called Power Management Micro Controller (PMMC). This hardware block is
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initialized early into boot process and provides services to Operating Systems
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on multiple processors including ones running Linux.
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See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
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The TI-SCI node describes the Texas Instrument's System Controller entity node.
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This parent node may optionally have additional children nodes which describe
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specific functionality such as clocks, power domain, reset or additional
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functionality as may be required for the SoC. This hierarchy also describes the
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relationship between the TI-SCI parent node to the child node.
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properties:
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$nodename:
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pattern: "^system-controller@[0-9a-f]+$"
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compatible:
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oneOf:
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- description: System controller on TI 66AK2G SoC and other K3 SoCs
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items:
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- const: ti,k2g-sci
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- description: System controller on TI AM654 SoC
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items:
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- const: ti,am654-sci
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reg-names:
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description: |
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Specifies the debug messages memory mapped region that is optionally
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made available from TI-SCI controller.
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const: debug_messages
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reg:
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minItems: 1
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mbox-names:
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description: |
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Specifies the mailboxes used to communicate with TI-SCI Controller
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made available from TI-SCI controller.
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items:
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- const: rx
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- const: tx
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mboxes:
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minItems: 2
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ti,system-reboot-controller:
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description: Determines If system reboot can be triggered by SoC reboot
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type: boolean
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ti,host-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Value corresponding to the host ID assigned by Firmware
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for identification of host processing entities such as virtual machines.
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power-controller:
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type: object
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$ref: /schemas/soc/ti/sci-pm-domain.yaml#
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clock-controller:
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type: object
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$ref: /schemas/clock/ti,sci-clk.yaml#
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reset-controller:
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type: object
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$ref: /schemas/reset/ti,sci-reset.yaml#
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required:
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- compatible
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- mbox-names
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- mboxes
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additionalProperties: false
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examples:
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- |
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pmmc: system-controller@2921800 {
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compatible = "ti,k2g-sci";
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ti,system-reboot-controller;
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mbox-names = "rx", "tx";
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mboxes= <&msgmgr 5 2>,
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<&msgmgr 0 0>;
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reg-names = "debug_messages";
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reg = <0x02921800 0x800>;
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};
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- |
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dmsc: system-controller@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x44083000 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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@ -122,6 +122,10 @@ properties:
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- enum:
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- mediatek,mt8195-evb
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- const: mediatek,mt8195
|
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- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
|
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items:
|
||||
- const: google,burnet
|
||||
- const: mediatek,mt8183
|
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- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
|
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items:
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- enum:
|
||||
@ -133,9 +137,19 @@ properties:
|
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items:
|
||||
- const: google,damu
|
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- const: mediatek,mt8183
|
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- description: Google Juniper (Acer Chromebook Spin 311)
|
||||
- description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
|
||||
items:
|
||||
- const: google,juniper-sku16
|
||||
- enum:
|
||||
- google,fennel-sku0
|
||||
- google,fennel-sku1
|
||||
- google,fennel-sku6
|
||||
- const: google,fennel
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
|
||||
items:
|
||||
- enum:
|
||||
- google,juniper-sku16
|
||||
- google,juniper-sku17
|
||||
- const: google,juniper
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
|
||||
@ -144,6 +158,10 @@ properties:
|
||||
- const: google,kakadu-rev2
|
||||
- const: google,kakadu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kappa (HP Chromebook 11a)
|
||||
items:
|
||||
- const: google,kappa
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
|
||||
items:
|
||||
- enum:
|
||||
@ -153,6 +171,13 @@ properties:
|
||||
- google,kodama-sku32
|
||||
- const: google,kodama
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Willow (Acer Chromebook 311 C722/C722T)
|
||||
items:
|
||||
- enum:
|
||||
- google,willow-sku0
|
||||
- google,willow-sku1
|
||||
- const: google,willow
|
||||
- const: mediatek,mt8183
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-pumpkin
|
||||
|
||||
@ -25,6 +25,7 @@ PROPERTIES
|
||||
"qcom,saw2"
|
||||
A more specific value could be one of:
|
||||
"qcom,apq8064-saw2-v1.1-cpu"
|
||||
"qcom,msm8226-saw2-v2.1-cpu"
|
||||
"qcom,msm8974-saw2-v2.1-cpu"
|
||||
"qcom,apq8084-saw2-v2.1-cpu"
|
||||
|
||||
|
||||
@ -36,17 +36,20 @@ description: |
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
sa8155p
|
||||
sc7180
|
||||
sc7280
|
||||
sdm630
|
||||
sdm660
|
||||
sdm845
|
||||
sdx55
|
||||
sm8150
|
||||
sm8250
|
||||
sm8350
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
adp
|
||||
cdp
|
||||
cp01-c1
|
||||
dragonboard
|
||||
@ -178,6 +181,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-idp
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
|
||||
- items:
|
||||
@ -198,6 +202,16 @@ properties:
|
||||
- qcom,ipq6018-cp01-c1
|
||||
- const: qcom,ipq6018
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8155p-adp
|
||||
- const: qcom,sa8155p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8150-mtp
|
||||
- const: qcom,sm8150
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qrb5165-rb5
|
||||
|
||||
@ -302,6 +302,24 @@ properties:
|
||||
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
|
||||
- const: renesas,r9a06g032
|
||||
|
||||
- description: RZ/G2UL (R9A07G043)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g043u11 # RZ/G2UL Type-1
|
||||
- renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
- const: renesas,r9a07g043
|
||||
|
||||
- description: RZ/G2{L,LC} (R9A07G044)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,smarc-evk # SMARC EVK
|
||||
- enum:
|
||||
- renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC
|
||||
- renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
|
||||
- renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L
|
||||
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
|
||||
- const: renesas,r9a07g044
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -600,6 +600,11 @@ properties:
|
||||
- const: zkmagic,a95x-z2
|
||||
- const: rockchip,rk3318
|
||||
|
||||
- description: Rockchip RK3568 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
55
sys/contrib/device-tree/Bindings/arm/rockchip/pmu.yaml
Normal file
55
sys/contrib/device-tree/Bindings/arm/rockchip/pmu.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip Power Management Unit (PMU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The PMU is used to turn on and off different power domains of the SoCs.
|
||||
This includes the power to the CPU cores.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,px30-pmu
|
||||
- rockchip,rk3066-pmu
|
||||
- rockchip,rk3288-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- rockchip,px30-pmu
|
||||
- rockchip,rk3066-pmu
|
||||
- rockchip,rk3288-pmu
|
||||
- rockchip,rk3399-pmu
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
pmu@20004000 {
|
||||
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
|
||||
reg = <0x20004000 0x100>;
|
||||
};
|
||||
@ -224,6 +224,12 @@ properties:
|
||||
- const: empire-electronix,m712
|
||||
- const: allwinner,sun5i-a13
|
||||
|
||||
- description: Forlinx OKA40i-C Development board
|
||||
items:
|
||||
- const: forlinx,oka40i-c
|
||||
- const: forlinx,feta40i-c
|
||||
- const: allwinner,sun8i-r40
|
||||
|
||||
- description: FriendlyARM NanoPi A64
|
||||
items:
|
||||
- const: friendlyarm,nanopi-a64
|
||||
@ -269,6 +275,11 @@ properties:
|
||||
- const: friendlyarm,nanopi-r1
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi R1S H5
|
||||
items:
|
||||
- const: friendlyarm,nanopi-r1s-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: FriendlyARM ZeroPi
|
||||
items:
|
||||
- const: friendlyarm,zeropi
|
||||
|
||||
@ -301,6 +301,33 @@ patternProperties:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
core-domain:
|
||||
type: object
|
||||
description: |
|
||||
The vast majority of hardware blocks of Tegra SoC belong to a
|
||||
Core power domain, which has a dedicated voltage rail that powers
|
||||
the blocks.
|
||||
|
||||
properties:
|
||||
operating-points-v2:
|
||||
description:
|
||||
Should contain level, voltages and opp-supported-hw property.
|
||||
The supported-hw is a bitfield indicating SoC speedo or process
|
||||
ID mask.
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- operating-points-v2
|
||||
- "#power-domain-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
core-supply:
|
||||
description:
|
||||
Phandle to voltage regulator connected to the SoC Core power rail.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -325,6 +352,7 @@ examples:
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
core-supply = <®ulator>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
@ -338,17 +366,24 @@ examples:
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
pd_core: core-domain {
|
||||
operating-points-v2 = <&core_opp_table>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
power-domains = <&pd_core>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -20,13 +20,13 @@ during retention, system won't boot without this):
|
||||
compatible = "ste,dbx500-backupram"
|
||||
|
||||
scu:
|
||||
see binding for arm/scu.txt
|
||||
see binding for arm/arm,scu.yaml
|
||||
|
||||
interrupt-controller:
|
||||
see binding for interrupt-controller/arm,gic.txt
|
||||
|
||||
timer:
|
||||
see binding for timer/arm,twd.txt
|
||||
see binding for timer/arm,twd-timer.yaml
|
||||
|
||||
clocks:
|
||||
see binding for clocks/ux500.txt
|
||||
|
||||
@ -20,7 +20,6 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: AHCI registers
|
||||
- description: SATA configuration and IPFS registers
|
||||
|
||||
@ -53,6 +53,17 @@ required:
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,sata-r8a7779
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -51,7 +51,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: High Frequency Oscillator (usually at 24MHz)
|
||||
- description: Low Frequency Oscillator (usually at 32kHz)
|
||||
@ -60,7 +59,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: hosc
|
||||
- const: losc
|
||||
|
||||
394
sys/contrib/device-tree/Bindings/clock/brcm,iproc-clocks.yaml
Normal file
394
sys/contrib/device-tree/Bindings/clock/brcm,iproc-clocks.yaml
Normal file
@ -0,0 +1,394 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom iProc Family Clocks
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
description: |
|
||||
The iProc clock controller manages clocks that are common to the iProc family.
|
||||
An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
|
||||
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
|
||||
comprises of several leaf clocks
|
||||
|
||||
ASIU clocks are a special case. These clocks are derived directly from the
|
||||
reference clock of the onboard crystal.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm63138-armpll
|
||||
- brcm,cygnus-armpll
|
||||
- brcm,cygnus-genpll
|
||||
- brcm,cygnus-lcpll0
|
||||
- brcm,cygnus-mipipll
|
||||
- brcm,cygnus-asiu-clk
|
||||
- brcm,cygnus-audiopll
|
||||
- brcm,hr2-armpll
|
||||
- brcm,nsp-armpll
|
||||
- brcm,nsp-genpll
|
||||
- brcm,nsp-lcpll0
|
||||
- brcm,ns2-genpll-scr
|
||||
- brcm,ns2-genpll-sw
|
||||
- brcm,ns2-lcpll-ddr
|
||||
- brcm,ns2-lcpll-ports
|
||||
- brcm,sr-genpll0
|
||||
- brcm,sr-genpll1
|
||||
- brcm,sr-genpll2
|
||||
- brcm,sr-genpll3
|
||||
- brcm,sr-genpll4
|
||||
- brcm,sr-genpll5
|
||||
- brcm,sr-genpll6
|
||||
- brcm,sr-lcpll0
|
||||
- brcm,sr-lcpll1
|
||||
- brcm,sr-lcpll-pcie
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: base register
|
||||
- description: power register
|
||||
- description: ASIU or split status register
|
||||
|
||||
clocks:
|
||||
description: The input parent clock phandle for the PLL / ASIU clock. For
|
||||
most iProc PLLs, this is an onboard crystal with a fixed rate.
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 45
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,cygnus-armpll
|
||||
- brcm,cygnus-genpll
|
||||
- brcm,cygnus-lcpll0
|
||||
- brcm,cygnus-mipipll
|
||||
- brcm,cygnus-asiu-clk
|
||||
- brcm,cygnus-audiopll
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
description: |
|
||||
The following table defines the set of PLL/clock index and ID for Cygnus.
|
||||
These clock IDs are defined in:
|
||||
"include/dt-bindings/clock/bcm-cygnus.h"
|
||||
|
||||
Clock Source (Parent) Index ID
|
||||
----- --------------- ----- --
|
||||
crystal N/A N/A N/A
|
||||
|
||||
armpll crystal N/A N/A
|
||||
|
||||
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
|
||||
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
|
||||
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
|
||||
|
||||
genpll crystal 0 BCM_CYGNUS_GENPLL
|
||||
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
|
||||
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
|
||||
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
|
||||
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
|
||||
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
|
||||
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
|
||||
|
||||
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
|
||||
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
|
||||
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
|
||||
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
|
||||
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
|
||||
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
|
||||
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
|
||||
|
||||
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
|
||||
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
|
||||
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
|
||||
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
|
||||
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
|
||||
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
|
||||
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
|
||||
|
||||
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
|
||||
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
|
||||
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
|
||||
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,hr2-armpll
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
description: |
|
||||
The following table defines the set of PLL/clock for Hurricane 2:
|
||||
|
||||
Clock Source Index ID
|
||||
----- ------ ----- --
|
||||
crystal N/A N/A N/A
|
||||
|
||||
armpll crystal N/A N/A
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,nsp-armpll
|
||||
- brcm,nsp-genpll
|
||||
- brcm,nsp-lcpll0
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
description: |
|
||||
The following table defines the set of PLL/clock index and ID for Northstar and
|
||||
Northstar Plus. These clock IDs are defined in:
|
||||
"include/dt-bindings/clock/bcm-nsp.h"
|
||||
|
||||
Clock Source Index ID
|
||||
----- ------ ----- --
|
||||
crystal N/A N/A N/A
|
||||
|
||||
armpll crystal N/A N/A
|
||||
|
||||
genpll crystal 0 BCM_NSP_GENPLL
|
||||
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
|
||||
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
|
||||
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
|
||||
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
|
||||
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
|
||||
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
|
||||
|
||||
lcpll0 crystal 0 BCM_NSP_LCPLL0
|
||||
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
|
||||
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
|
||||
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,ns2-genpll-scr
|
||||
- brcm,ns2-genpll-sw
|
||||
- brcm,ns2-lcpll-ddr
|
||||
- brcm,ns2-lcpll-ports
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
description: |
|
||||
The following table defines the set of PLL/clock index and ID for Northstar 2.
|
||||
These clock IDs are defined in:
|
||||
"include/dt-bindings/clock/bcm-ns2.h"
|
||||
|
||||
Clock Source Index ID
|
||||
----- ------ ----- --
|
||||
crystal N/A N/A N/A
|
||||
|
||||
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
|
||||
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
|
||||
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
|
||||
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
|
||||
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
|
||||
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
|
||||
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
|
||||
|
||||
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
|
||||
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
|
||||
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
|
||||
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
|
||||
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
|
||||
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
|
||||
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
|
||||
|
||||
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
|
||||
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
|
||||
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
|
||||
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
|
||||
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
|
||||
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
|
||||
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
|
||||
|
||||
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
|
||||
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
|
||||
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
|
||||
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
|
||||
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
|
||||
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
|
||||
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,sr-genpll0
|
||||
- brcm,sr-genpll1
|
||||
- brcm,sr-genpll2
|
||||
- brcm,sr-genpll3
|
||||
- brcm,sr-genpll4
|
||||
- brcm,sr-genpll5
|
||||
- brcm,sr-genpll6
|
||||
- brcm,sr-lcpll0
|
||||
- brcm,sr-lcpll1
|
||||
- brcm,sr-lcpll-pcie
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
description: |
|
||||
The following table defines the set of PLL/clock index and ID for Stingray.
|
||||
These clock IDs are defined in:
|
||||
"include/dt-bindings/clock/bcm-sr.h"
|
||||
|
||||
Clock Source Index ID
|
||||
----- ------ ----- --
|
||||
crystal N/A N/A N/A
|
||||
crmu_ref25m crystal N/A N/A
|
||||
|
||||
genpll0 crystal 0 BCM_SR_GENPLL0
|
||||
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
|
||||
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
|
||||
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
|
||||
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
|
||||
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
|
||||
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
|
||||
|
||||
genpll1 crystal 0 BCM_SR_GENPLL1
|
||||
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
|
||||
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
|
||||
|
||||
genpll2 crystal 0 BCM_SR_GENPLL2
|
||||
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
|
||||
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
|
||||
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
|
||||
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
|
||||
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
|
||||
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
|
||||
|
||||
genpll3 crystal 0 BCM_SR_GENPLL3
|
||||
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
|
||||
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
|
||||
|
||||
genpll4 crystal 0 BCM_SR_GENPLL4
|
||||
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
|
||||
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
|
||||
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
|
||||
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
|
||||
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
|
||||
|
||||
genpll5 crystal 0 BCM_SR_GENPLL5
|
||||
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
|
||||
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
|
||||
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
|
||||
|
||||
genpll6 crystal 0 BCM_SR_GENPLL6
|
||||
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
|
||||
|
||||
lcpll0 crystal 0 BCM_SR_LCPLL0
|
||||
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
|
||||
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
|
||||
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
|
||||
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
|
||||
|
||||
lcpll1 crystal 0 BCM_SR_LCPLL1
|
||||
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
|
||||
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
|
||||
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
|
||||
|
||||
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
|
||||
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,cygnus-genpll
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: genpll
|
||||
- const: axi21
|
||||
- const: 250mhz
|
||||
- const: ihost_sys
|
||||
- const: enet_sw
|
||||
- const: audio_125
|
||||
- const: can
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,nsp-lcpll0
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: lcpll0
|
||||
- const: pcie_phy
|
||||
- const: sdio
|
||||
- const: ddr_phy
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,nsp-genpll
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: genpll
|
||||
- const: phy
|
||||
- const: ethernetclk
|
||||
- const: usbclk
|
||||
- const: iprocfast
|
||||
- const: sata1
|
||||
- const: sata2
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
osc1: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
genpll@301d000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,cygnus-genpll";
|
||||
reg = <0x301d000 0x2c>, <0x301c020 0x4>;
|
||||
clocks = <&os1c>;
|
||||
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
|
||||
"enet_sw", "audio_125", "can";
|
||||
};
|
||||
- |
|
||||
osc2: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
asiu_clks@301d048 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,cygnus-asiu-clk";
|
||||
reg = <0x301d048 0xc>, <0x180aa024 0x4>;
|
||||
clocks = <&osc2>;
|
||||
clock-output-names = "keypad", "adc/touch", "pwm";
|
||||
};
|
||||
45
sys/contrib/device-tree/Bindings/clock/gpio-mux-clock.yaml
Normal file
45
sys/contrib/device-tree/Bindings/clock/gpio-mux-clock.yaml
Normal file
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple GPIO clock multiplexer
|
||||
|
||||
maintainers:
|
||||
- Sergej Sawazki <ce3a@gmx.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: gpio-mux-clock
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: First parent clock
|
||||
- description: Second parent clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
select-gpios:
|
||||
description: GPIO reference for selecting the parent clock.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- select-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
clock {
|
||||
compatible = "gpio-mux-clock";
|
||||
clocks = <&parentclk1>, <&parentclk2>;
|
||||
#clock-cells = <0>;
|
||||
select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hisilicon SOC Clock for HI3559AV100
|
||||
|
||||
maintainers:
|
||||
- Dongjiu Geng <gengdongjiu@huawei.com>
|
||||
|
||||
description: |
|
||||
Hisilicon SOC clock control module which supports the clocks, resets and
|
||||
power domains on HI3559AV100.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/hi3559av100-clock.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- hisilicon,hi3559av100-clock
|
||||
- hisilicon,hi3559av100-shub-clock
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 2
|
||||
description: |
|
||||
First cell is reset request register offset.
|
||||
Second cell is bit offset in reset request register.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@12010000 {
|
||||
compatible = "hisilicon,hi3559av100-clock";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <2>;
|
||||
reg = <0x0 0x12010000 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -84,6 +84,7 @@ patternProperties:
|
||||
idt,slew-percent:
|
||||
description: The Slew rate control for CMOS single-ended.
|
||||
enum: [ 80, 85, 90, 100 ]
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -139,13 +140,13 @@ examples:
|
||||
clock-names = "xin";
|
||||
|
||||
OUT1 {
|
||||
idt,drive-mode = <VC5_CMOSD>;
|
||||
idt,voltage-microvolts = <1800000>;
|
||||
idt,mode = <VC5_CMOSD>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <80>;
|
||||
};
|
||||
|
||||
OUT4 {
|
||||
idt,drive-mode = <VC5_LVDS>;
|
||||
idt,mode = <VC5_LVDS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -22,6 +22,8 @@ select:
|
||||
enum:
|
||||
- ingenic,jz4740-cgu
|
||||
- ingenic,jz4725b-cgu
|
||||
- ingenic,jz4760-cgu
|
||||
- ingenic,jz4760b-cgu
|
||||
- ingenic,jz4770-cgu
|
||||
- ingenic,jz4780-cgu
|
||||
- ingenic,x1000-cgu
|
||||
@ -49,6 +51,8 @@ properties:
|
||||
- enum:
|
||||
- ingenic,jz4740-cgu
|
||||
- ingenic,jz4725b-cgu
|
||||
- ingenic,jz4760-cgu
|
||||
- ingenic,jz4760b-cgu
|
||||
- ingenic,jz4770-cgu
|
||||
- ingenic,jz4780-cgu
|
||||
- ingenic,x1000-cgu
|
||||
@ -93,6 +97,8 @@ required:
|
||||
patternProperties:
|
||||
"^usb-phy@[a-f0-9]+$":
|
||||
allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
|
||||
"^mac-phy-ctrl@[a-f0-9]+$":
|
||||
allOf: [ $ref: "../net/ingenic,mac.yaml#" ]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
115
sys/contrib/device-tree/Bindings/clock/nvidia,tegra124-car.yaml
Normal file
115
sys/contrib/device-tree/Bindings/clock/nvidia,tegra124-car.yaml
Normal file
@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Clock and Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |
|
||||
The Clock and Reset (CAR) is the HW module responsible for muxing and gating
|
||||
Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
|
||||
|
||||
CLKGEN provides the registers to program the PLLs. It controls most of
|
||||
the clock source programming and most of the clock dividers.
|
||||
|
||||
CLKGEN input signals include the external clock for the reference frequency
|
||||
(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
|
||||
|
||||
Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
|
||||
|
||||
RSTGEN provides the registers needed to control resetting of each block in
|
||||
the Tegra system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra124-car
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
nvidia,external-memory-controller:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the external memory controller node
|
||||
|
||||
patternProperties:
|
||||
"^emc-timings-[0-9]+$":
|
||||
type: object
|
||||
properties:
|
||||
nvidia,ram-code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
|
||||
this timing set is used for
|
||||
|
||||
patternProperties:
|
||||
"^timing-[0-9]+$":
|
||||
type: object
|
||||
properties:
|
||||
clock-frequency:
|
||||
description:
|
||||
external memory clock rate in Hz
|
||||
minimum: 1000000
|
||||
maximum: 1000000000
|
||||
|
||||
nvidia,parent-clock-frequency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
rate of parent clock in Hz
|
||||
minimum: 1000000
|
||||
maximum: 1000000000
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: parent clock of EMC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: emc-parent
|
||||
|
||||
required:
|
||||
- clock-frequency
|
||||
- nvidia,parent-clock-frequency
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
|
||||
car: clock-controller@60006000 {
|
||||
compatible = "nvidia,tegra124-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
compatible = "nvidia,tegra20-ehci";
|
||||
reg = <0xc5004000 0x4000>;
|
||||
clocks = <&car TEGRA124_CLK_USB2>;
|
||||
resets = <&car TEGRA124_CLK_USB2>;
|
||||
};
|
||||
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Clock and Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |
|
||||
The Clock and Reset (CAR) is the HW module responsible for muxing and gating
|
||||
Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
|
||||
|
||||
CLKGEN provides the registers to program the PLLs. It controls most of
|
||||
the clock source programming and most of the clock dividers.
|
||||
|
||||
CLKGEN input signals include the external clock for the reference frequency
|
||||
(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
|
||||
|
||||
Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
|
||||
|
||||
RSTGEN provides the registers needed to control resetting of each block in
|
||||
the Tegra system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-car
|
||||
- nvidia,tegra30-car
|
||||
- nvidia,tegra114-car
|
||||
- nvidia,tegra210-car
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
car: clock-controller@60006000 {
|
||||
compatible = "nvidia,tegra20-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
compatible = "nvidia,tegra20-ehci";
|
||||
reg = <0xc5004000 0x4000>;
|
||||
clocks = <&car TEGRA20_CLK_USB2>;
|
||||
resets = <&car TEGRA20_CLK_USB2>;
|
||||
};
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
|
||||
|
||||
maintainers:
|
||||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SM8250.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sm8250-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -20,6 +20,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8180x-dispcc
|
||||
- qcom,sm8150-dispcc
|
||||
- qcom,sm8250-dispcc
|
||||
|
||||
|
||||
@ -46,7 +46,6 @@ properties:
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
@ -27,7 +27,6 @@ properties:
|
||||
- description: Sleep clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -35,7 +34,6 @@ properties:
|
||||
- const: sleep_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
72
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml
Normal file
72
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6125.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6125.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm6125
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@1400000 {
|
||||
compatible = "qcom,gcc-sm6125";
|
||||
reg = <0x01400000 0x1f0000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
|
||||
};
|
||||
...
|
||||
@ -36,7 +36,6 @@ properties:
|
||||
- description: USB3 phy wrapper pipe clock source (Optional clock)
|
||||
- description: USB3 phy sec pipe clock source (Optional clock)
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -54,7 +53,6 @@ properties:
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -26,9 +26,10 @@ description: |
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-msm8994.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
@ -40,6 +41,8 @@ properties:
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
|
||||
@ -12,6 +12,7 @@ Required properties :
|
||||
|
||||
"qcom,rpmcc-msm8660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8226", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8936", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
|
||||
140
sys/contrib/device-tree/Bindings/clock/renesas,emev2-smu.yaml
Normal file
140
sys/contrib/device-tree/Bindings/clock/renesas,emev2-smu.yaml
Normal file
@ -0,0 +1,140 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas EMMA Mobile EV2 System Management Unit
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
- Magnus Damm <magnus.damm@gmail.com>
|
||||
|
||||
description: |
|
||||
The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
|
||||
This is not a clock provider, but clocks under SMU depend on it.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,emev2-smu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 2
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
patternProperties:
|
||||
".*sclkdiv@.*":
|
||||
type: object
|
||||
|
||||
description: |
|
||||
Function block with an input mux and a divider, which corresponds to
|
||||
"Serial clock generator" in fig. "Clock System Overview" of the manual,
|
||||
and "xxx frequency division setting register" (XXXCLKDIV) registers.
|
||||
This makes internal (neither input nor output) clock that is provided
|
||||
to input of xxxGCLK block.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,emev2-smu-clkdiv
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Byte offset from SMU base and Bit position in the register.
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
".*sclk@.*":
|
||||
type: object
|
||||
|
||||
description: |
|
||||
Clock gating node shown as "Clock stop processing block" in the
|
||||
fig. "Clock System Overview" of the manual.
|
||||
Registers are "xxx clock gate control register" (XXXGCLKCTRL).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,emev2-smu-gclk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Byte offset from SMU base and Bit position in the register.
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
// Example of clock-tree description:
|
||||
//
|
||||
// This describes a clock path in the clock tree
|
||||
// c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
|
||||
clocks@e0110000 {
|
||||
compatible = "renesas,emev2-smu";
|
||||
reg = <0xe0110000 0x10000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
c32ki: c32ki {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
pll3_fo: pll3_fo {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&c32ki>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <7000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
|
||||
compatible = "renesas,emev2-smu-clkdiv";
|
||||
reg = <0x610 0>;
|
||||
clocks = <&pll3_fo>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
usia_u0_sclk: usia_u0_sclk@4a0,1 {
|
||||
compatible = "renesas,emev2-smu-gclk";
|
||||
reg = <0x4a0 1>;
|
||||
clocks = <&usia_u0_sclkdiv>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/N1D (R9A06G032) System Controller
|
||||
|
||||
maintainers:
|
||||
- Gareth Williams <gareth.williams.jx@renesas.com>
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a06g032-sysctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: External 40 MHz crystal
|
||||
- description: Optional external 32.768 kHz crystal
|
||||
- description: Optional external JTAG input
|
||||
- description: Optional external RGMII_REFCLK
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mclk
|
||||
- const: rtc
|
||||
- const: jtag
|
||||
- const: rgmii_ref_ext
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sysctrl: system-controller@4000c000 {
|
||||
compatible = "renesas,r9a06g032-sysctrl";
|
||||
reg = <0x4000c000 0x1000>;
|
||||
clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
|
||||
<&ext_rgmii_ref>;
|
||||
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
|
||||
- The Module Standby Mode block provides two functions:
|
||||
1. Module Standby, providing a Clock Domain to control the clock supply
|
||||
to individual SoC devices,
|
||||
2. Reset Control, to perform a software reset of individual SoC devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
Clock source to CPG can be either from external clock input (EXCLK) or
|
||||
crystal oscillator (XIN/XOUT).
|
||||
const: extal
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a07g044-cpg.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
description:
|
||||
SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
|
||||
can be power-managed through Module Standby should refer to the CPG device
|
||||
node in their "power-domains" property, as documented by the generic PM
|
||||
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
const: 0
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpg: clock-controller@11010000 {
|
||||
compatible = "renesas,r9a07g044-cpg";
|
||||
reg = <0x11010000 0x10000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -24,9 +24,8 @@ it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
The driver currently only supports XTAL input mode, and does not support any
|
||||
fancy input configurations. They can still be programmed into the chip and
|
||||
the driver will leave them "as is".
|
||||
The driver currently does not support any fancy input configurations. They can
|
||||
still be programmed into the chip and the driver will leave them "as is".
|
||||
|
||||
==I2C device node==
|
||||
|
||||
@ -45,9 +44,9 @@ Required properties:
|
||||
corresponding to inputs. Use a fixed clock for the "xtal" input.
|
||||
At least one must be present.
|
||||
- clock-names: One of: "xtal", "in0", "in1", "in2"
|
||||
- vdd-supply: Regulator node for VDD
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: Regulator node for VDD
|
||||
- vdda-supply: Regulator node for VDDA
|
||||
- vdds-supply: Regulator node for VDDS
|
||||
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
|
||||
@ -60,7 +59,14 @@ Optional properties:
|
||||
be initialized, and always performs the soft-reset routine. Since this will
|
||||
temporarily stop all output clocks, don't do this if the chip is generating
|
||||
the CPU clock for example.
|
||||
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
|
||||
in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
|
||||
- interrupts: Interrupt for INTRb pin.
|
||||
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
|
||||
rather than 1.8V thresholds.
|
||||
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
|
||||
specified output. The driver selects the output VDD_SEL setting based on this
|
||||
voltage.
|
||||
- #address-cells: shall be set to 1.
|
||||
- #size-cells: shall be set to 0.
|
||||
|
||||
@ -77,8 +83,6 @@ Required child node properties:
|
||||
- reg: number of clock output.
|
||||
|
||||
Optional child node properties:
|
||||
- vdd-supply: Regulator node for VDD for this output. The driver selects default
|
||||
values for common-mode and amplitude based on the voltage.
|
||||
- silabs,format: Output format, one of:
|
||||
1 = differential (defaults to LVDS levels)
|
||||
2 = low-power (defaults to HCSL levels)
|
||||
|
||||
@ -40,7 +40,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: ext-26m
|
||||
- const: ext-32k
|
||||
|
||||
@ -54,7 +54,9 @@ properties:
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: st,stm32mp1-rcc
|
||||
- enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
- st,stm32mp1-rcc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
@ -71,7 +73,7 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
@ -10,7 +10,10 @@ Required properties:
|
||||
|
||||
- compatible : shall be:
|
||||
"st,clkgen-pll0"
|
||||
"st,clkgen-pll0-a0"
|
||||
"st,clkgen-pll0-c0"
|
||||
"st,clkgen-pll1"
|
||||
"st,clkgen-pll1-c0"
|
||||
"st,stih407-clkgen-plla9"
|
||||
"st,stih418-clkgen-plla9"
|
||||
|
||||
|
||||
@ -64,6 +64,16 @@ Required properties:
|
||||
audio use case)
|
||||
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
|
||||
and activate synchronous mode)
|
||||
"st,flexgen-stih407-a0"
|
||||
"st,flexgen-stih410-a0"
|
||||
"st,flexgen-stih407-c0"
|
||||
"st,flexgen-stih410-c0"
|
||||
"st,flexgen-stih418-c0"
|
||||
"st,flexgen-stih407-d0"
|
||||
"st,flexgen-stih410-d0"
|
||||
"st,flexgen-stih407-d2"
|
||||
"st,flexgen-stih418-d2"
|
||||
"st,flexgen-stih407-d3"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs).
|
||||
|
||||
@ -12,6 +12,9 @@ This binding uses the common clock binding[1].
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,quadfs"
|
||||
"st,quadfs-d0"
|
||||
"st,quadfs-d2"
|
||||
"st,quadfs-d3"
|
||||
"st,quadfs-pll"
|
||||
|
||||
|
||||
|
||||
@ -12,7 +12,9 @@ maintainers:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,am654-ehrpwm-tbclk
|
||||
- enum:
|
||||
- ti,am654-ehrpwm-tbclk
|
||||
- ti,am64-epwm-tbclk
|
||||
- const: syscon
|
||||
|
||||
"#clock-cells":
|
||||
|
||||
209
sys/contrib/device-tree/Bindings/clock/ti,lmk04832.yaml
Normal file
209
sys/contrib/device-tree/Bindings/clock/ti,lmk04832.yaml
Normal file
@ -0,0 +1,209 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for the Texas Instruments LMK04832
|
||||
|
||||
maintainers:
|
||||
- Liam Beguin <liambeguin@gmail.com>
|
||||
|
||||
description: |
|
||||
Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
|
||||
support. The LMK04832 is pin compatible with the LMK0482x family.
|
||||
|
||||
Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,lmk04832
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 5000000
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PLL2 reference clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscin
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
ti,spi-4wire-rdbk:
|
||||
description: |
|
||||
Select SPI 4wire readback pin configuration.
|
||||
Available readback pins are,
|
||||
CLKin_SEL0 0
|
||||
CLKin_SEL1 1
|
||||
RESET 2
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
default: 1
|
||||
|
||||
ti,vco-hz:
|
||||
description: Optional to set VCO frequency of the PLL in Hertz.
|
||||
|
||||
ti,sysref-ddly:
|
||||
description: SYSREF digital delay value.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 8
|
||||
maximum: 8191
|
||||
default: 8
|
||||
|
||||
ti,sysref-mux:
|
||||
description: |
|
||||
SYSREF Mux configuration.
|
||||
Available options are,
|
||||
Normal SYNC 0
|
||||
Re-clocked 1
|
||||
SYSREF Pulser 2
|
||||
SYSREF Continuous 3
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 3
|
||||
|
||||
ti,sync-mode:
|
||||
description: SYNC pin configuration.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
default: 1
|
||||
|
||||
ti,sysref-pulse-count:
|
||||
description:
|
||||
Number of SYSREF pulses to send when SYSREF is not in continuous mode.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 4, 8]
|
||||
default: 4
|
||||
|
||||
patternProperties:
|
||||
"@[0-9a-d]+$":
|
||||
type: object
|
||||
description:
|
||||
Child nodes used to configure output clocks.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description:
|
||||
clock output identifier.
|
||||
minimum: 0
|
||||
maximum: 13
|
||||
|
||||
ti,clkout-fmt:
|
||||
description:
|
||||
Clock output format.
|
||||
Available options are,
|
||||
Powerdown 0x00
|
||||
LVDS 0x01
|
||||
HSDS 6 mA 0x02
|
||||
HSDS 8 mA 0x03
|
||||
LVPECL 1600 mV 0x04
|
||||
LVPECL 2000 mV 0x05
|
||||
LCPECL 0x06
|
||||
CML 16 mA 0x07
|
||||
CML 24 mA 0x08
|
||||
CML 32 mA 0x09
|
||||
CMOS (Off/Inverted) 0x0a
|
||||
CMOS (Normal/Off) 0x0b
|
||||
CMOS (Inverted/Inverted) 0x0c
|
||||
CMOS (Inverted/Normal) 0x0d
|
||||
CMOS (Normal/Inverted) 0x0e
|
||||
CMOS (Normal/Normal) 0x0f
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
ti,clkout-sysref:
|
||||
description:
|
||||
Select SYSREF clock path for output clock.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clocks {
|
||||
lmk04832_oscin: oscin {
|
||||
compatible = "fixed-clock";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <122880000>;
|
||||
clock-output-names = "lmk04832-oscin";
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
lmk04832: clock-controller@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0>;
|
||||
|
||||
compatible = "ti,lmk04832";
|
||||
spi-max-frequency = <781250>;
|
||||
|
||||
reset-gpios = <&gpio_lmk 0 0 0>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clocks = <&lmk04832_oscin>;
|
||||
clock-names = "oscin";
|
||||
|
||||
ti,spi-4wire-rdbk = <0>;
|
||||
ti,vco-hz = <2457600000>;
|
||||
|
||||
assigned-clocks =
|
||||
<&lmk04832 0>, <&lmk04832 1>,
|
||||
<&lmk04832 2>, <&lmk04832 3>,
|
||||
<&lmk04832 4>,
|
||||
<&lmk04832 6>, <&lmk04832 7>,
|
||||
<&lmk04832 10>, <&lmk04832 11>;
|
||||
assigned-clock-rates =
|
||||
<122880000>, <384000>,
|
||||
<122880000>, <384000>,
|
||||
<122880000>,
|
||||
<153600000>, <384000>,
|
||||
<614400000>, <384000>;
|
||||
|
||||
clkout0@0 {
|
||||
reg = <0>;
|
||||
ti,clkout-fmt = <0x01>; // LVDS
|
||||
};
|
||||
|
||||
clkout1@1 {
|
||||
reg = <1>;
|
||||
ti,clkout-fmt = <0x01>; // LVDS
|
||||
ti,clkout-sysref;
|
||||
};
|
||||
};
|
||||
};
|
||||
49
sys/contrib/device-tree/Bindings/clock/ti,sci-clk.yaml
Normal file
49
sys/contrib/device-tree/Bindings/clock/ti,sci-clk.yaml
Normal file
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI-SCI clock controller node bindings
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
||||
description: |
|
||||
Some TI SoCs contain a system controller (like the Power Management Micro
|
||||
Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
|
||||
the state of the various hardware modules present on the SoC. Communication
|
||||
between the host processor running an OS and the system controller happens
|
||||
through a protocol called TI System Control Interface (TI-SCI protocol).
|
||||
|
||||
This clock controller node uses the TI SCI protocol to perform various clock
|
||||
management of various hardware modules (devices) present on the SoC. This
|
||||
node must be a child node of the associated TI-SCI system controller node.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^clock-controller$"
|
||||
|
||||
compatible:
|
||||
const: ti,k2g-sci-clk
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
description:
|
||||
The two cells represent values that the TI-SCI controller defines.
|
||||
|
||||
The first cell should contain the device ID.
|
||||
|
||||
The second cell should contain the clock ID.
|
||||
|
||||
Please see http://processors.wiki.ti.com/index.php/TISCI for
|
||||
protocol documentation for the values to be used for different devices.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
@ -42,6 +42,11 @@ Required properties:
|
||||
"idlest" - contains the idle status register base address
|
||||
"mult-div1" - contains the multiplier / divider register base address
|
||||
"autoidle" - contains the autoidle register base address (optional)
|
||||
"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
|
||||
the frequency spreading register base address (optional)
|
||||
"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
|
||||
the modulation frequency register base address
|
||||
(optional)
|
||||
ti,am3-* dpll types do not have autoidle register
|
||||
ti,omap2-* dpll type does not support idlest / autoidle registers
|
||||
|
||||
@ -51,6 +56,14 @@ Optional properties:
|
||||
- ti,low-power-stop : DPLL supports low power stop mode, gating output
|
||||
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
|
||||
- ti,lock : DPLL locks in programmed rate
|
||||
- ti,min-div : the minimum divisor to start from to round the DPLL
|
||||
target rate
|
||||
- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
|
||||
spreading in permille (10th of a percent)
|
||||
- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
|
||||
spectrum modulation frequency
|
||||
- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
|
||||
to enable the downspread feature
|
||||
|
||||
Examples:
|
||||
dpll_core_ck: dpll_core_ck@44e00490 {
|
||||
@ -83,3 +96,10 @@ Examples:
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0500>, <0x0540>;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
|
||||
};
|
||||
|
||||
@ -202,11 +202,11 @@ Example 2 (MT8173 SoC):
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
clocks = <&infracfg CLK_INFRA_CA72SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
@ -214,11 +214,11 @@ Example 2 (MT8173 SoC):
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&infracfg CLK_INFRA_CA57SEL>,
|
||||
clocks = <&infracfg CLK_INFRA_CA72SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cpu_opp_table_b>;
|
||||
|
||||
@ -30,7 +30,6 @@ properties:
|
||||
- description: Module clock
|
||||
- description: MBus clock
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -38,7 +37,6 @@ properties:
|
||||
- const: mod
|
||||
- const: ram
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
53
sys/contrib/device-tree/Bindings/crypto/arm,cryptocell.yaml
Normal file
53
sys/contrib/device-tree/Bindings/crypto/arm,cryptocell.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm TrustZone CryptoCell cryptographic engine
|
||||
|
||||
maintainers:
|
||||
- Gilad Ben-Yossef <gilad@benyossef.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,cryptocell-713-ree
|
||||
- arm,cryptocell-703-ree
|
||||
- arm,cryptocell-712-ree
|
||||
- arm,cryptocell-710-ree
|
||||
- arm,cryptocell-630p-ree
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
arm_cc712: crypto@80000000 {
|
||||
compatible = "arm,cryptocell-712-ree";
|
||||
reg = <0x80000000 0x10000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/cortina,sl3516-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SL3516 cryptographic offloader driver
|
||||
|
||||
maintainers:
|
||||
- Corentin Labbe <clabbe@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cortina,sl3516-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
#include <dt-bindings/reset/cortina,gemini-reset.h>
|
||||
|
||||
crypto@62000000 {
|
||||
compatible = "cortina,sl3516-crypto";
|
||||
reg = <0x62000000 0x10000>;
|
||||
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_SECURITY>;
|
||||
clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
|
||||
};
|
||||
@ -27,7 +27,6 @@ properties:
|
||||
- description: MXS DCP DCP interrupt
|
||||
- description: MXS DCP secure interrupt
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2018 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Intel IXP4xx cryptographic engine
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
|
||||
(Network Processing Engine). Since it is not a device on its own
|
||||
it is defined as a subnode of the NPE, if crypto support is
|
||||
available on the platform.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,ixp4xx-crypto
|
||||
|
||||
intel,npe-handle:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
maxItems: 1
|
||||
description: phandle to the NPE this crypto engine is using, the cell
|
||||
describing the NPE instance to be used.
|
||||
|
||||
queue-rx:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
description: phandle to the RX queue on the NPE, the cell describing
|
||||
the queue instance to be used.
|
||||
|
||||
queue-txready:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
description: phandle to the TX READY queue on the NPE, the cell describing
|
||||
the queue instance to be used.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- intel,npe-handle
|
||||
- queue-rx
|
||||
- queue-txready
|
||||
|
||||
additionalProperties: false
|
||||
@ -0,0 +1,126 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra30 Activity Monitor
|
||||
|
||||
maintainers:
|
||||
- Dmitry Osipenko <digetx@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |
|
||||
The activity monitor block collects statistics about the behaviour of other
|
||||
components in the system. This information can be used to derive the rate at
|
||||
which the external memory needs to be clocked in order to serve all requests
|
||||
from the monitored clients.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra30-actmon
|
||||
- nvidia,tegra114-actmon
|
||||
- nvidia,tegra124-actmon
|
||||
- nvidia,tegra210-actmon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: actmon
|
||||
- const: emc
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: actmon
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
interconnect-names:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
description:
|
||||
Should include name of the interconnect path for each interconnect
|
||||
entry. Consult TRM documentation for information about available
|
||||
memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
|
||||
|
||||
operating-points-v2:
|
||||
description:
|
||||
Should contain freqs and voltages and opp-supported-hw property, which
|
||||
is a bitfield indicating SoC speedo ID mask.
|
||||
|
||||
"#cooling-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- interrupts
|
||||
- interconnects
|
||||
- interconnect-names
|
||||
- operating-points-v2
|
||||
- "#cooling-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/memory/tegra30-mc.h>
|
||||
|
||||
mc: memory-controller@7000f000 {
|
||||
compatible = "nvidia,tegra30-mc";
|
||||
reg = <0x7000f000 0x400>;
|
||||
clocks = <&clk 32>;
|
||||
clock-names = "mc";
|
||||
|
||||
interrupts = <0 77 4>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
emc: external-memory-controller@7000f400 {
|
||||
compatible = "nvidia,tegra30-emc";
|
||||
reg = <0x7000f400 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
clocks = <&clk 57>;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
};
|
||||
|
||||
actmon@6000c800 {
|
||||
compatible = "nvidia,tegra30-actmon";
|
||||
reg = <0x6000c800 0x400>;
|
||||
interrupts = <0 45 4>;
|
||||
clocks = <&clk 119>, <&clk 57>;
|
||||
clock-names = "actmon", "emc";
|
||||
resets = <&rst 119>;
|
||||
reset-names = "actmon";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
|
||||
interconnect-names = "cpu-read";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
@ -26,14 +26,12 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: Display Backend registers
|
||||
- description: SAT registers
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: be
|
||||
- const: sat
|
||||
@ -43,7 +41,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: The backend interface clock
|
||||
- description: The backend module clock
|
||||
@ -52,7 +49,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: ahb
|
||||
- const: mod
|
||||
@ -61,14 +57,12 @@ properties:
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: The Backend reset line
|
||||
- description: The SAT reset line
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: be
|
||||
- const: sat
|
||||
|
||||
@ -24,7 +24,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Module Clock
|
||||
|
||||
@ -46,7 +46,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Register Clock
|
||||
@ -57,7 +56,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: iahb
|
||||
- const: isfr
|
||||
@ -68,14 +66,12 @@ properties:
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: HDMI Controller Reset
|
||||
- description: HDCP Reset
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: ctrl
|
||||
- const: hdcp
|
||||
|
||||
@ -27,7 +27,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Module Clock
|
||||
@ -36,7 +35,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: bus
|
||||
- const: mod
|
||||
|
||||
@ -48,7 +48,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 6
|
||||
items:
|
||||
- description: The TCON TOP interface clock
|
||||
- description: The TCON TOP TV0 clock
|
||||
@ -59,7 +58,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: bus
|
||||
- const: tcon-tv0
|
||||
|
||||
@ -11,7 +11,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-vec
|
||||
enum:
|
||||
- brcm,bcm2711-vec
|
||||
- brcm,bcm2835-vec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
240
sys/contrib/device-tree/Bindings/display/bridge/adi,adv7511.yaml
Normal file
240
sys/contrib/device-tree/Bindings/display/bridge/adi,adv7511.yaml
Normal file
@ -0,0 +1,240 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/adi,adv7511.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices ADV7511/11W/13 HDMI Encoders
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
The ADV7511, ADV7511W and ADV7513 are HDMI audio and video
|
||||
transmitters compatible with HDMI 1.4 and DVI 1.0. They support color
|
||||
space conversion, S/PDIF, CEC and HDCP. The transmitter input is
|
||||
parallel RGB or YUV data.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,adv7511
|
||||
- adi,adv7511w
|
||||
- adi,adv7513
|
||||
|
||||
reg:
|
||||
description: |
|
||||
I2C slave addresses.
|
||||
|
||||
The ADV7511/11W/13 internal registers are split into four pages
|
||||
exposed through different I2C addresses, creating four register
|
||||
maps. Each map has it own I2C address and acts as a standard slave
|
||||
device on the I2C bus. The main address is mandatory, others are
|
||||
optional and revert to defaults if not specified.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
description:
|
||||
Names of maps with programmable addresses. It can contain any map
|
||||
needing a non-default address.
|
||||
minItems: 1
|
||||
items:
|
||||
- const: main
|
||||
- const: edid
|
||||
- const: cec
|
||||
- const: packet
|
||||
|
||||
clocks:
|
||||
description: Reference to the CEC clock.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: cec
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
pd-gpios:
|
||||
description: GPIO connected to the power down signal.
|
||||
maxItems: 1
|
||||
|
||||
avdd-supply:
|
||||
description: A 1.8V supply that powers up the AVDD pin.
|
||||
|
||||
dvdd-supply:
|
||||
description: A 1.8V supply that powers up the DVDD pin.
|
||||
|
||||
pvdd-supply:
|
||||
description: A 1.8V supply that powers up the PVDD pin.
|
||||
|
||||
dvdd-3v-supply:
|
||||
description: A 3.3V supply that powers up the DVDD_3V pin.
|
||||
|
||||
bgvdd-supply:
|
||||
description: A 1.8V supply that powers up the BGVDD pin.
|
||||
|
||||
adi,input-depth:
|
||||
description: Number of bits per color component at the input.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 8, 10, 12 ]
|
||||
|
||||
adi,input-colorspace:
|
||||
description: Input color space.
|
||||
enum: [ rgb, yuv422, yuv444 ]
|
||||
|
||||
adi,input-clock:
|
||||
description: |
|
||||
Input clock type.
|
||||
"1x": one clock cycle per pixel
|
||||
"2x": two clock cycles per pixel
|
||||
"dd": one clock cycle per pixel, data driven on both edges
|
||||
enum: [ 1x, 2x, dd ]
|
||||
|
||||
adi,clock-delay:
|
||||
description:
|
||||
Video data clock delay relative to the pixel clock, in ps
|
||||
(-1200ps .. 1600 ps).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
adi,embedded-sync:
|
||||
description:
|
||||
If defined, the input uses synchronization signals embedded in the
|
||||
data stream (similar to BT.656).
|
||||
type: boolean
|
||||
|
||||
adi,input-style:
|
||||
description:
|
||||
Input components arrangement variant as listed in the input
|
||||
format tables in the datasheet.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3 ]
|
||||
|
||||
adi,input-justification:
|
||||
description: Input bit justification.
|
||||
enum: [ left, evenly, right ]
|
||||
|
||||
ports:
|
||||
description:
|
||||
The ADV7511(W)/13 has two video ports and one audio port. This node
|
||||
models their connections as documented in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
type: object
|
||||
properties:
|
||||
port@0:
|
||||
description: Video port for the RGB or YUV input.
|
||||
type: object
|
||||
|
||||
port@1:
|
||||
description: Video port for the HDMI output.
|
||||
type: object
|
||||
|
||||
port@2:
|
||||
description: Audio port for the HDMI output.
|
||||
type: object
|
||||
|
||||
# adi,input-colorspace and adi,input-clock are required except in
|
||||
# "rgb 1x" and "yuv444 1x" modes, in which case they must not be
|
||||
# specified.
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
adi,input-colorspace:
|
||||
contains:
|
||||
enum: [ rgb, yuv444 ]
|
||||
adi,input-clock:
|
||||
contains:
|
||||
const: 1x
|
||||
|
||||
then:
|
||||
required:
|
||||
- adi,input-style
|
||||
- adi,input-justification
|
||||
|
||||
else:
|
||||
properties:
|
||||
adi,input-style: false
|
||||
adi,input-justification: false
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ports
|
||||
- adi,input-depth
|
||||
- adi,input-colorspace
|
||||
- adi,input-clock
|
||||
- avdd-supply
|
||||
- dvdd-supply
|
||||
- pvdd-supply
|
||||
- dvdd-3v-supply
|
||||
- bgvdd-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0 0xe6500000>;
|
||||
|
||||
adv7511w: hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
/*
|
||||
* The EDID page will be accessible on address 0x66 on the I2C
|
||||
* bus. All other maps continue to use their default addresses.
|
||||
*/
|
||||
reg = <0x39>, <0x66>;
|
||||
reg-names = "main", "edid";
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&cec_clock>;
|
||||
clock-names = "cec";
|
||||
avdd-supply = <&v1v8>;
|
||||
dvdd-supply = <&v1v8>;
|
||||
pvdd-supply = <&v1v8>;
|
||||
dvdd-3v-supply = <&v3v3>;
|
||||
bgvdd-supply = <&v1v8>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "yuv422";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
adi,input-style = <3>;
|
||||
adi,input-justification = "right";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511w_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
codec_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s0_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
184
sys/contrib/device-tree/Bindings/display/bridge/adi,adv7533.yaml
Normal file
184
sys/contrib/device-tree/Bindings/display/bridge/adi,adv7533.yaml
Normal file
@ -0,0 +1,184 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices ADV7533/35 HDMI Encoders
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
The ADV7533 and ADV7535 are HDMI audio and video transmitters
|
||||
compatible with HDMI 1.4 and DVI 1.0. They support color space
|
||||
conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,adv7533
|
||||
- adi,adv7535
|
||||
|
||||
reg:
|
||||
description: |
|
||||
I2C slave addresses.
|
||||
|
||||
The ADV7533/35 internal registers are split into four pages
|
||||
exposed through different I2C addresses, creating four register
|
||||
maps. Each map has it own I2C address and acts as a standard slave
|
||||
device on the I2C bus. The main address is mandatory, others are
|
||||
optional and revert to defaults if not specified.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
description:
|
||||
Names of maps with programmable addresses. It can contain any map
|
||||
needing a non-default address.
|
||||
minItems: 1
|
||||
items:
|
||||
- const: main
|
||||
- const: edid
|
||||
- const: cec
|
||||
- const: packet
|
||||
|
||||
clocks:
|
||||
description: Reference to the CEC clock.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: cec
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
pd-gpios:
|
||||
description: GPIO connected to the power down signal.
|
||||
maxItems: 1
|
||||
|
||||
avdd-supply:
|
||||
description: A 1.8V supply that powers up the AVDD pin.
|
||||
|
||||
dvdd-supply:
|
||||
description: A 1.8V supply that powers up the DVDD pin.
|
||||
|
||||
pvdd-supply:
|
||||
description: A 1.8V supply that powers up the PVDD pin.
|
||||
|
||||
a2vdd-supply:
|
||||
description: A 1.8V supply that powers up the A2VDD pin.
|
||||
|
||||
v3p3-supply:
|
||||
description: A 3.3V supply that powers up the V3P3 pin.
|
||||
|
||||
v1p2-supply:
|
||||
description:
|
||||
A supply that powers up the V1P2 pin. It can be either 1.2V
|
||||
or 1.8V for ADV7533 but only 1.8V for ADV7535.
|
||||
|
||||
adi,disable-timing-generator:
|
||||
description:
|
||||
Disables the internal timing generator. The chip will rely on the
|
||||
sync signals in the DSI data lanes, rather than generating its own
|
||||
timings for HDMI output.
|
||||
type: boolean
|
||||
|
||||
adi,dsi-lanes:
|
||||
description: Number of DSI data lanes connected to the DSI host.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
|
||||
ports:
|
||||
description:
|
||||
The ADV7533/35 has two video ports and one audio port. This node
|
||||
models their connections as documented in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
type: object
|
||||
properties:
|
||||
port@0:
|
||||
description:
|
||||
Video port for the DSI input. The remote endpoint phandle
|
||||
should be a reference to a valid mipi_dsi_host_device.
|
||||
type: object
|
||||
|
||||
port@1:
|
||||
description: Video port for the HDMI output.
|
||||
type: object
|
||||
|
||||
port@2:
|
||||
description: Audio port for the HDMI output.
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ports
|
||||
- adi,dsi-lanes
|
||||
- avdd-supply
|
||||
- dvdd-supply
|
||||
- pvdd-supply
|
||||
- a2vdd-supply
|
||||
- v3p3-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0 0xe6500000>;
|
||||
|
||||
adv7533: hdmi@39 {
|
||||
compatible = "adi,adv7533";
|
||||
/*
|
||||
* The EDID page will be accessible on address 0x66 on the I2C
|
||||
* bus. All other maps continue to use their default addresses.
|
||||
*/
|
||||
reg = <0x39>, <0x66>;
|
||||
reg-names = "main", "edid";
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&cec_clock>;
|
||||
clock-names = "cec";
|
||||
adi,dsi-lanes = <4>;
|
||||
avdd-supply = <&v1v8>;
|
||||
dvdd-supply = <&v1v8>;
|
||||
pvdd-supply = <&v1v8>;
|
||||
a2vdd-supply = <&v1v8>;
|
||||
v3p3-supply = <&v3v3>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7533_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7533_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
codec_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s0_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -18,7 +18,6 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description:
|
||||
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
|
||||
@ -26,13 +25,15 @@ properties:
|
||||
included in the associated PHY.
|
||||
- description:
|
||||
Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
|
||||
- description:
|
||||
Register block of mhdptx sapb registers.
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: mhdptx
|
||||
- const: j721e-intg
|
||||
- const: mhdptx-sapb
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
@ -99,14 +100,18 @@ allOf:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
|
||||
|
||||
maintainers:
|
||||
- Nicolas Boichat <drinkcat@chromium.org>
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
|
||||
description: |
|
||||
ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
|
||||
DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
|
||||
which is connected to and operated by the ChromeOS Embedded Controller
|
||||
(See google,cros-ec.yaml). It is accessed using I2C tunneling through
|
||||
the EC and therefore its node should be a child of an EC I2C tunnel node
|
||||
(See google,cros-ec-i2c-tunnel.yaml).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-ec-anx7688
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: I2C address of the device.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for HDMI input.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: USB Type-c connector.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c_tunnel_b: i2c-tunnel1 {
|
||||
compatible = "google,cros-ec-i2c-tunnel";
|
||||
google,remote-bus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
anx7688: anx7688@2c {
|
||||
compatible = "google,cros-ec-anx7688";
|
||||
reg = <0x2c>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
anx7688_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
anx7688_out: endpoint {
|
||||
remote-endpoint = <&typec_connector>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
124
sys/contrib/device-tree/Bindings/display/bridge/ite,it66121.yaml
Normal file
124
sys/contrib/device-tree/Bindings/display/bridge/ite,it66121.yaml
Normal file
@ -0,0 +1,124 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ITE it66121 HDMI bridge Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Phong LE <ple@baylibre.com>
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
description: |
|
||||
The IT66121 is a high-performance and low-power single channel HDMI
|
||||
transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible
|
||||
to DVI 1.0 specifications.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ite,it66121
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to active low reset
|
||||
|
||||
vrf12-supply:
|
||||
description: Regulator for 1.2V analog core power.
|
||||
|
||||
vcn33-supply:
|
||||
description: Regulator for 3.3V digital core power.
|
||||
|
||||
vcn18-supply:
|
||||
description: Regulator for 1.8V IO core power.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: DPI input port.
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
bus-width:
|
||||
description:
|
||||
Endpoint bus width.
|
||||
enum:
|
||||
- 12 # 12 data lines connected and dual-edge mode
|
||||
- 24 # 24 data lines connected and single-edge mode
|
||||
default: 24
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: HDMI Connector port.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- vrf12-supply
|
||||
- vcn33-supply
|
||||
- vcn18-supply
|
||||
- interrupts
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
it66121hdmitx: hdmitx@4c {
|
||||
compatible = "ite,it66121";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ite_pins_default>;
|
||||
vcn33-supply = <&mt6358_vcn33_wifi_reg>;
|
||||
vcn18-supply = <&mt6358_vcn18_reg>;
|
||||
vrf12-supply = <&mt6358_vrf12_reg>;
|
||||
reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <0x4c>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
it66121_in: endpoint {
|
||||
bus-width = <12>;
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi_conn_out: endpoint {
|
||||
remote-endpoint = <&hdmi_conn_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -29,7 +29,8 @@ properties:
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Primary MIPI port for MIPI input
|
||||
|
||||
|
||||
@ -0,0 +1,159 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
Texas Instruments SN65DSI83 1x Single-link MIPI DSI
|
||||
to 1x Single-link LVDS
|
||||
https://www.ti.com/lit/gpn/sn65dsi83
|
||||
Texas Instruments SN65DSI84 1x Single-link MIPI DSI
|
||||
to 1x Dual-link or 2x Single-link LVDS
|
||||
https://www.ti.com/lit/gpn/sn65dsi84
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,sn65dsi83
|
||||
- ti,sn65dsi84
|
||||
|
||||
reg:
|
||||
enum:
|
||||
- 0x2c
|
||||
- 0x2d
|
||||
|
||||
enable-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO specifier for bridge_en pin (active high).
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for MIPI DSI Channel-A input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for MIPI DSI Channel-B input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-A output (panel or bridge).
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-B output (panel or bridge).
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- enable-gpios
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,sn65dsi83
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@1: false
|
||||
port@3: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,sn65dsi84
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@1: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@2d {
|
||||
compatible = "ti,sn65dsi83";
|
||||
reg = <0x2d>;
|
||||
|
||||
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
68
sys/contrib/device-tree/Bindings/display/faraday,tve200.yaml
Normal file
68
sys/contrib/device-tree/Bindings/display/faraday,tve200.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/faraday,tve200.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Faraday TV Encoder TVE200
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: faraday,tve200
|
||||
- items:
|
||||
- const: cortina,gemini-tvc
|
||||
- const: faraday,tve200
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: PCLK
|
||||
- const: TVE
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/cortina,gemini-reset.h>
|
||||
display-controller@6a000000 {
|
||||
compatible = "faraday,tve200";
|
||||
reg = <0x6a000000 0x1000>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_TVC>;
|
||||
clocks = <&syscon GEMINI_CLK_GATE_TVC>,
|
||||
<&syscon GEMINI_CLK_TVC>;
|
||||
clock-names = "PCLK", "TVE";
|
||||
|
||||
port {
|
||||
display_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI CEC Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7623-cec
|
||||
- mediatek,mt8167-cec
|
||||
- mediatek,mt8173-cec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
cec: cec@10013000 {
|
||||
compatible = "mediatek,mt8173-cec";
|
||||
reg = <0x10013000 0xbc>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI DDC Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7623-hdmi-ddc
|
||||
- mediatek,mt8167-hdmi-ddc
|
||||
- mediatek,mt8173-hdmi-ddc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ddc-i2c
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
hdmi_ddc0: i2c@11012000 {
|
||||
compatible = "mediatek,mt8173-hdmi-ddc";
|
||||
reg = <0x11012000 0x1c>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_I2C5>;
|
||||
clock-names = "ddc-i2c";
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,133 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI Encoder Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
|
||||
its parallel input.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt2701-hdmi
|
||||
- mediatek,mt7623-hdmi
|
||||
- mediatek,mt8167-hdmi
|
||||
- mediatek,mt8173-hdmi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Pixel Clock
|
||||
- description: HDMI PLL
|
||||
- description: Bit Clock
|
||||
- description: S/PDIF Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pixel
|
||||
- const: pll
|
||||
- const: bclk
|
||||
- const: spdif
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: hdmi
|
||||
|
||||
mediatek,syscon-hdmi:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
maxItems: 1
|
||||
description: |
|
||||
phandle link and register offset to the system configuration registers.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
Input port node. This port should be connected to a DPI output port.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
Output port node. This port should be connected to the input port of a connector
|
||||
node that contains a ddc-i2c-bus property, or to the input port of an attached
|
||||
bridge chip, such as a SlimPort transmitter.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- mediatek,syscon-hdmi
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
hdmi0: hdmi@14025000 {
|
||||
compatible = "mediatek,mt8173-hdmi";
|
||||
reg = <0x14025000 0x400>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLLCK>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pin>;
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
146
sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml
Normal file
146
sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml
Normal file
@ -0,0 +1,146 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MSM Display Port Controller
|
||||
|
||||
maintainers:
|
||||
- Kuogee Hsieh <khsieh@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for DisplayPort host controller for MSM targets
|
||||
that are compatible with VESA DisplayPort interface specification.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-dp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB clock to enable register access
|
||||
- description: Display Port AUX clock
|
||||
- description: Display Port Link clock
|
||||
- description: Link interface clock between DP and PHY
|
||||
- description: Display Port Pixel clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core_iface
|
||||
- const: core_aux
|
||||
- const: ctrl_link
|
||||
- const: ctrl_link_iface
|
||||
- const: stream_pixel
|
||||
|
||||
assigned-clocks:
|
||||
items:
|
||||
- description: link clock source
|
||||
- description: pixel clock source
|
||||
|
||||
assigned-clock-parents:
|
||||
items:
|
||||
- description: phy 0 parent
|
||||
- description: phy 1 parent
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: dp
|
||||
|
||||
operating-points-v2:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Input endpoint of the controller
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Output endpoint of the controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- "#sound-dai-cells"
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/power/qcom-aoss-qmp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
compatible = "qcom,sc7180-dp";
|
||||
reg = <0xae90000 0x1400>;
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
|
||||
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
|
||||
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&typec>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
228
sys/contrib/device-tree/Bindings/display/msm/dpu-sc7180.yaml
Normal file
228
sys/contrib/device-tree/Bindings/display/msm/dpu-sc7180.yaml
Normal file
@ -0,0 +1,228 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SC7180 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path specifying the port ids for data bus
|
||||
|
||||
interconnect-names:
|
||||
const: mdp0-mem
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display rotator clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: rot
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF0 (DP)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7180-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "ahb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
212
sys/contrib/device-tree/Bindings/display/msm/dpu-sdm845.yaml
Normal file
212
sys/contrib/device-tree/Bindings/display/msm/dpu-sdm845.yaml
Normal file
@ -0,0 +1,212 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SDM845 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF2 (DSI2)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x880 0x8>,
|
||||
<&apps_smmu 0xc80 0x8>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,185 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI controller
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: dsi_ctrl
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display byte clock
|
||||
- description: Display byte interface clock
|
||||
- description: Display pixel clock
|
||||
- description: Display escape clock
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
qcom,dual-dsi-mode:
|
||||
type: boolean
|
||||
description: |
|
||||
Indicates if the DSI controller is driving a panel which needs
|
||||
2 DSI links.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
ports:
|
||||
$ref: "/schemas/graph.yaml#/properties/ports"
|
||||
description: |
|
||||
Contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 10nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-10nm
|
||||
- const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vdds-supply:
|
||||
description: |
|
||||
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
|
||||
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 14nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-14nm
|
||||
- const: qcom,dsi-phy-14nm-660
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 20nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-20nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-20nm";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 28nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-28nm-hpm
|
||||
- const: qcom,dsi-phy-28nm-lp
|
||||
- const: qcom,dsi-phy-28nm-8960
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-lp";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Description of Qualcomm Display DSI PHY common dt properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
This defines the DSI PHY dt properties which are common for all
|
||||
dsi phy versions.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
@ -51,37 +51,37 @@ properties:
|
||||
- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
|
||||
[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
|
||||
- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
|
||||
specifications. Data are transferred as follows on 4 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
|
||||
DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
|
||||
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
|
||||
DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
|
||||
DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
|
||||
|
||||
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
|
||||
Data are transferred as follows on 4 LVDS lanes.
|
||||
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
|
||||
Slot 0 1 2 3 4 5 6
|
||||
________________ _________________
|
||||
Clock \_______________________/
|
||||
______ ______ ______ ______ ______ ______ ______
|
||||
DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
|
||||
DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
|
||||
DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
|
||||
DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
|
||||
|
||||
Control signals are mapped as follows.
|
||||
|
||||
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/samsung,lms397kf04.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung LMS397KF04 display panel
|
||||
|
||||
description: The datasheet claims this is based around a display controller
|
||||
named DB7430 with a separate backlight controller.
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,lms397kf04
|
||||
|
||||
reg: true
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
vci-supply:
|
||||
description: regulator that supplies the VCI analog voltage
|
||||
usually around 3.0 V
|
||||
|
||||
vccio-supply:
|
||||
description: regulator that supplies the VCCIO voltage usually
|
||||
around 1.8 V
|
||||
|
||||
backlight: true
|
||||
|
||||
spi-max-frequency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: inherited as a SPI client node, the datasheet specifies
|
||||
maximum 300 ns minimum cycle which gives around 3 MHz max frequency
|
||||
maximum: 3000000
|
||||
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "samsung,lms397kf04";
|
||||
spi-max-frequency = <3000000>;
|
||||
reg = <0>;
|
||||
vci-supply = <&lcd_3v0_reg>;
|
||||
vccio-supply = <&lcd_1v8_reg>;
|
||||
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&ktd259>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -55,7 +55,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
The connections to the DU output video ports are modeled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
@ -92,7 +92,6 @@ required:
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- resets
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
|
||||
@ -29,7 +29,6 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
@ -41,7 +40,6 @@ properties:
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
|
||||
@ -29,7 +29,6 @@ properties:
|
||||
- description: DSI bus clock
|
||||
- description: Pixel clock
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -37,7 +36,6 @@ properties:
|
||||
- const: ref
|
||||
- const: px_clk
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
@ -22,7 +22,6 @@ properties:
|
||||
- description: events interrupt line.
|
||||
- description: errors interrupt line.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
@ -65,7 +65,6 @@ properties:
|
||||
The APB clock and at least one video clock are mandatory, the audio clock
|
||||
is optional.
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: dp_apb_clk is the APB clock
|
||||
- description: dp_aud_clk is the Audio clock
|
||||
@ -78,13 +77,11 @@ properties:
|
||||
clock-names:
|
||||
oneOf:
|
||||
- minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: dp_apb_clk
|
||||
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
|
||||
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
|
||||
- minItems: 3
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: dp_apb_clk
|
||||
- const: dp_aud_clk
|
||||
@ -116,7 +113,6 @@ properties:
|
||||
maxItems: 2
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: dp-phy0
|
||||
- const: dp-phy1
|
||||
|
||||
61
sys/contrib/device-tree/Bindings/dma/altr,msgdma.yaml
Normal file
61
sys/contrib/device-tree/Bindings/dma/altr,msgdma.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Altera mSGDMA IP core
|
||||
|
||||
maintainers:
|
||||
- Olivier Dautricourt <olivier.dautricourt@orolia.com>
|
||||
|
||||
description: |
|
||||
Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
|
||||
intellectual property (IP)
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: altr,socfpga-msgdma
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Control and Status Register Slave Port
|
||||
- description: Descriptor Slave Port
|
||||
- description: Response Slave Port
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: csr
|
||||
- const: desc
|
||||
- const: resp
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
description:
|
||||
The cell identifies the channel id (must be 0)
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
msgdma_controller: dma-controller@ff200b00 {
|
||||
compatible = "altr,socfpga-msgdma";
|
||||
reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
|
||||
reg-names = "csr", "desc", "resp";
|
||||
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
136
sys/contrib/device-tree/Bindings/dma/arm-pl08x.yaml
Normal file
136
sys/contrib/device-tree/Bindings/dma/arm-pl08x.yaml
Normal file
@ -0,0 +1,136 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
# We need a select here so we don't match all nodes with 'arm,primecell'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- arm,pl080
|
||||
- arm,pl081
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- arm,pl080
|
||||
- arm,pl081
|
||||
- const: arm,primecell
|
||||
- items:
|
||||
- const: faraday,ftdma020
|
||||
- const: arm,pl080
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: Address range of the PL08x registers
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
description: The PL08x interrupt number
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
description: The clock running the IP core clock
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
lli-bus-interface-ahb1:
|
||||
type: boolean
|
||||
description: if AHB master 1 is eligible for fetching LLIs
|
||||
|
||||
lli-bus-interface-ahb2:
|
||||
type: boolean
|
||||
description: if AHB master 2 is eligible for fetching LLIs
|
||||
|
||||
mem-bus-interface-ahb1:
|
||||
type: boolean
|
||||
description: if AHB master 1 is eligible for fetching memory contents
|
||||
|
||||
mem-bus-interface-ahb2:
|
||||
type: boolean
|
||||
description: if AHB master 2 is eligible for fetching memory contents
|
||||
|
||||
memcpy-burst-size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum:
|
||||
- 1
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
- 64
|
||||
- 128
|
||||
- 256
|
||||
description: the size of the bursts for memcpy
|
||||
|
||||
memcpy-bus-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
- 64
|
||||
description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
|
||||
|
||||
required:
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#dma-cells"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dmac0: dma-controller@10130000 {
|
||||
compatible = "arm,pl080", "arm,primecell";
|
||||
reg = <0x10130000 0x1000>;
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <15>;
|
||||
clocks = <&hclkdma0>;
|
||||
clock-names = "apb_pclk";
|
||||
lli-bus-interface-ahb1;
|
||||
lli-bus-interface-ahb2;
|
||||
mem-bus-interface-ahb2;
|
||||
memcpy-burst-size = <256>;
|
||||
memcpy-bus-width = <32>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/cortina,gemini-reset.h>
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
dma-controller@67000000 {
|
||||
compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
|
||||
/* Faraday Technology FTDMAC020 variant */
|
||||
arm,primecell-periphid = <0x0003b080>;
|
||||
reg = <0x67000000 0x1000>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_DMAC>;
|
||||
clocks = <&syscon GEMINI_CLK_AHB>;
|
||||
clock-names = "apb_pclk";
|
||||
/* Bus interface AHB1 (AHB0) is totally tilted */
|
||||
lli-bus-interface-ahb2;
|
||||
mem-bus-interface-ahb2;
|
||||
memcpy-burst-size = <256>;
|
||||
memcpy-bus-width = <32>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
enum:
|
||||
- qcom,sdm845-gpi-dma
|
||||
- qcom,sm8150-gpi-dma
|
||||
- qcom,sm8250-gpi-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -52,7 +52,6 @@ properties:
|
||||
|
||||
interrupt-names:
|
||||
minItems: 9
|
||||
maxItems: 17
|
||||
items:
|
||||
- const: error
|
||||
- pattern: "^ch([0-9]|1[0-5])$"
|
||||
|
||||
@ -33,7 +33,7 @@ The following are mandatory properties for 66AK2G SoCs only:
|
||||
- power-domains:Should contain a phandle to a PM domain provider node
|
||||
and an args specifier containing the device id
|
||||
value. This property is as per the binding,
|
||||
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
|
||||
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
|
||||
|
||||
Optional properties:
|
||||
-------------------
|
||||
@ -70,7 +70,7 @@ The following are mandatory properties for 66AK2G SoCs only:
|
||||
- power-domains:Should contain a phandle to a PM domain provider node
|
||||
and an args specifier containing the device id
|
||||
value. This property is as per the binding,
|
||||
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
|
||||
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
|
||||
|
||||
Optional properties:
|
||||
-------------------
|
||||
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Generic performance domains
|
||||
|
||||
maintainers:
|
||||
- Sudeep Holla <sudeep.holla@arm.com>
|
||||
|
||||
description: |+
|
||||
This binding is intended for performance management of groups of devices or
|
||||
CPUs that run in the same performance domain. Performance domains must not
|
||||
be confused with power domains. A performance domain is defined by a set
|
||||
of devices that always have to run at the same performance level. For a given
|
||||
performance domain, there is a single point of control that affects all the
|
||||
devices in the domain, making it impossible to set the performance level of
|
||||
an individual device in the domain independently from other devices in
|
||||
that domain. For example, a set of CPUs that share a voltage domain, and
|
||||
have a common frequency control, is said to be in the same performance
|
||||
domain.
|
||||
|
||||
This device tree binding can be used to bind performance domain consumer
|
||||
devices with their performance domains provided by performance domain
|
||||
providers. A performance domain provider can be represented by any node in
|
||||
the device tree and can provide one or more performance domains. A consumer
|
||||
node can refer to the provider by a phandle and a set of phandle arguments
|
||||
(so called performance domain specifiers) of length specified by the
|
||||
\#performance-domain-cells property in the performance domain provider node.
|
||||
|
||||
select: true
|
||||
|
||||
properties:
|
||||
"#performance-domain-cells":
|
||||
description:
|
||||
Number of cells in a performance domain specifier. Typically 0 for nodes
|
||||
representing a single performance domain and 1 for nodes providing
|
||||
multiple performance domains (e.g. performance controllers), but can be
|
||||
any value as specified by device tree binding documentation of particular
|
||||
provider.
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
performance-domains:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle and performance domain specifier as defined by bindings of the
|
||||
performance controller/provider specified by phandle.
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
performance: performance-controller@12340000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x12340000 0x1000>;
|
||||
#performance-domain-cells = <1>;
|
||||
};
|
||||
|
||||
// The node above defines a performance controller that is a performance
|
||||
// domain provider and expects one cell as its phandle argument.
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
performance-domains = <&performance 1>;
|
||||
};
|
||||
};
|
||||
@ -30,14 +30,12 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: uncorrectable error interrupt
|
||||
- description: correctable error interrupt
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: ue
|
||||
- const: ce
|
||||
|
||||
@ -32,7 +32,6 @@ properties:
|
||||
oneOf:
|
||||
- allOf:
|
||||
- minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$"
|
||||
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
|
||||
|
||||
@ -4,14 +4,16 @@
|
||||
$id: "http://devicetree.org/schemas/eeprom/at25.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: SPI EEPROMs compatible with Atmel's AT25
|
||||
title: SPI EEPROMs or FRAMs compatible with Atmel's AT25
|
||||
|
||||
maintainers:
|
||||
- Christian Eggers <ceggers@arri.de>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^eeprom@[0-9a-f]{1,2}$"
|
||||
anyOf:
|
||||
- pattern: "^eeprom@[0-9a-f]{1,2}$"
|
||||
- pattern: "^fram@[0-9a-f]{1,2}$"
|
||||
|
||||
# There are multiple known vendors who manufacture EEPROM chips compatible
|
||||
# with Atmel's AT25. The compatible string requires two items where the
|
||||
@ -31,6 +33,7 @@ properties:
|
||||
- microchip,25lc040
|
||||
- st,m95m02
|
||||
- st,m95256
|
||||
- cypress,fm25
|
||||
|
||||
- const: atmel,at25
|
||||
|
||||
@ -47,7 +50,7 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072]
|
||||
description:
|
||||
Size of the eeprom page.
|
||||
Size of the eeprom page. FRAMs don't have pages.
|
||||
|
||||
size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
@ -100,9 +103,19 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
- pagesize
|
||||
- size
|
||||
- address-width
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
const: cypress,fm25
|
||||
then:
|
||||
required:
|
||||
- pagesize
|
||||
- size
|
||||
- address-width
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -125,4 +138,10 @@ examples:
|
||||
size = <32768>;
|
||||
address-width = <16>;
|
||||
};
|
||||
|
||||
fram@1 {
|
||||
compatible = "cypress,fm25", "atmel,at25";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -91,7 +91,6 @@ properties:
|
||||
interrupts:
|
||||
# Either 1 or 2 interrupts can be present
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: tx or combined interrupt
|
||||
- description: rx interrupt
|
||||
@ -105,7 +104,6 @@ properties:
|
||||
interrupt-names:
|
||||
# minItems must be specified here because the default would be 2
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: tx irq
|
||||
- const: rx irq
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user