diff --git a/sys/amd64/pci/pci_bus.c b/sys/amd64/pci/pci_bus.c
index 3611b1b17fba..54bc13853860 100644
--- a/sys/amd64/pci/pci_bus.c
+++ b/sys/amd64/pci/pci_bus.c
@@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
+#include <sys/sysctl.h>
 
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
@@ -42,6 +43,7 @@ __FBSDID("$FreeBSD$");
 #include <isa/isavar.h>
 #include <machine/legacyvar.h>
 #include <machine/pci_cfgreg.h>
+#include <machine/resource.h>
 
 #include "pcib_if.h"
 
@@ -81,8 +83,8 @@ legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
 
 static const char *
 legacy_pcib_is_host_bridge(int bus, int slot, int func,
-			  u_int32_t id, u_int8_t class, u_int8_t subclass,
-			  u_int8_t *busnum)
+			  uint32_t id, uint8_t class, uint8_t subclass,
+			  uint8_t *busnum)
 {
 	const char *s = NULL;
 
@@ -262,6 +264,37 @@ legacy_pcib_write_ivar(device_t dev, device_t child, int which,
 	return ENOENT;
 }
 
+SYSCTL_DECL(_hw_pci);
+
+static int legacy_host_mem_start = 0x80000000;
+/* No TUNABLE_ULONG :-( */
+TUNABLE_INT("hw.pci.host_mem_start", &legacy_host_mem_start);
+SYSCTL_INT(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
+    &legacy_host_mem_start, 0x80000000,
+    "Limit the host bridge memory to being above this address.  Must be\n\
+set at boot via a tunable.");
+
+static struct resource *
+legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+    /*
+     * If no memory preference is given, use upper 32MB slot most
+     * bioses use for their memory window.  Typically other bridges
+     * before us get in the way to assert their preferences on memory.
+     * Hardcoding like this sucks, so a more MD/MI way needs to be
+     * found to do it.  This is typically only used on older laptops
+     * that don't have pci busses behind pci bridge, so assuming > 32MB
+     * is liekly OK.
+     *
+     * However, this can cause problems for other chipsets, so we make
+     * this tunable by hw.pci.host_mem_start.
+     */
+    if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
+	start = legacy_host_mem_start;
+    return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
+	count, flags));
+}
 
 static device_method_t legacy_pcib_methods[] = {
 	/* Device interface */
@@ -276,7 +309,7 @@ static device_method_t legacy_pcib_methods[] = {
 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
 	DEVMETHOD(bus_read_ivar,	legacy_pcib_read_ivar),
 	DEVMETHOD(bus_write_ivar,	legacy_pcib_write_ivar),
-	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
+	DEVMETHOD(bus_alloc_resource,	legacy_pcib_alloc_resource),
 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),