Do not expose to scheduler caches of single CPU.
Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels or topology (root, package/L3 and core/L2). But with SMT disabled core/L2 matches thread, so additional topology level only causes more traversal work. With this change SMT case is reported same as before, while non-SMT is reported with only 2 much more simple levels. MFC after: 2 weeks
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@ -829,6 +829,12 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
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node = topo_next_nonchild_node(root, node);
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}
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/*
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* We are not interested in nodes including only one CPU each.
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*/
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if (nchildren == root->cpu_count)
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return;
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cg_root->cg_child = smp_topo_alloc(nchildren);
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cg_root->cg_children = nchildren;
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