Set PCIe device's Max_Payload_Size to match PCIe root's.
Usually on boot the MPS is already configured by BIOS. But we've found that on hot-plug it is not true at least for our Supermicro X11 boards. As result, mismatch between root's configuration of 256 bytes and device's default of 128 bytes cause problems for some devices, while others seem to work fine. MFC after: 1 month Sponsored by: iXsystems, Inc.
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@ -4267,6 +4267,45 @@ pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
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}
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#endif
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/*
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* For PCIe device set Max_Payload_Size to match PCIe root's.
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*/
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static void
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pcie_setup_mps(device_t dev)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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device_t root;
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uint16_t rmps, mmps, mps;
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if (dinfo->cfg.pcie.pcie_location == 0)
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return;
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root = pci_find_pcie_root_port(dev);
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if (root == NULL)
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return;
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/* Check whether the MPS is already configured. */
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rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) &
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PCIEM_CTL_MAX_PAYLOAD;
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mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) &
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PCIEM_CTL_MAX_PAYLOAD;
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if (mps == rmps)
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return;
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/* Check whether the device is capable of the root's MPS. */
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mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) &
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PCIEM_CAP_MAX_PAYLOAD) << 5;
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if (rmps > mmps) {
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/*
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* The device is unable to handle root's MPS. Limit root.
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* XXX: We should traverse through all the tree, applying
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* it to all the devices.
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*/
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pcie_adjust_config(root, PCIER_DEVICE_CTL,
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PCIEM_CTL_MAX_PAYLOAD, mmps, 2);
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} else {
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pcie_adjust_config(dev, PCIER_DEVICE_CTL,
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PCIEM_CTL_MAX_PAYLOAD, rmps, 2);
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}
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}
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static void
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pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
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{
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@ -4354,6 +4393,7 @@ pci_add_child(device_t bus, struct pci_devinfo *dinfo)
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pci_cfg_restore(dev, dinfo);
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pci_print_verbose(dinfo);
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pci_add_resources(bus, dev, 0, 0);
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pcie_setup_mps(dev);
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pci_child_added(dinfo->cfg.dev);
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if (pci_clear_aer_on_attach)
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