* According to the reference code, AR_WA_D3_L1_DISBABLE is bit 14.
* Add some other WAR bits (very usefully described too) in preparation for porting over some suspend/resume fixes from ath9k/Atheros. Obtained from: Qualcomm Atheros
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=236009
@ -253,11 +253,15 @@
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#define AR_MAC_LED_ASSOC_PEND 0x2 /* STA is trying to associate */
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#define AR_MAC_LED_ASSOC_S 10
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#define AR_WA_BIT6 0x00000040
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#define AR_WA_BIT7 0x00000080
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#define AR_WA_D3_L1_DISABLE 0x00004000 /* */
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#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */
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#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */
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#define AR_WA_ANALOG_SHIFT 0x00100000
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#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */
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#define AR_WA_D3_L1_DISABLE 0x00800000 /* bit 23 */
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#define AR_WA_BIT22 0x00400000
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#define AR_WA_BIT23 0x00800000
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#define AR_WA_DEFAULT 0x0000073f
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#define AR9280_WA_DEFAULT 0x0040073b /* disable bit 2, see commit */
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