Add a driver for the BCM2835 Mini-UART as seen on the RPi3
Reviewed by: andrew Approved by: andrew Differential Revision: https://reviews.freebsd.org/D15684
This commit is contained in:
Diane Bruce
parent
e34425be26
commit
5bede50958
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=334997
@ -165,6 +165,7 @@ device dwmmc
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# Serial (COM) ports
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device uart # Generic UART driver
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device uart_msm # Qualcomm MSM UART driver
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device uart_mu # RPI3 aux port
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device uart_mvebu # Armada 3700 UART driver
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device uart_ns8250 # ns8250-type UART driver
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device uart_snps
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@ -209,6 +209,7 @@ dev/pci/pci_host_generic_fdt.c optional pci fdt
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dev/psci/psci.c standard
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dev/psci/psci_arm64.S standard
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dev/uart/uart_cpu_arm64.c optional uart
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dev/uart/uart_dev_mu.c optional uart uart_mu
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dev/uart/uart_dev_pl011.c optional uart pl011
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dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220
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dev/usb/controller/ehci_mv.c optional ehci_mv fdt
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521
sys/dev/uart/uart_dev_mu.c
Normal file
521
sys/dev/uart/uart_dev_mu.c
Normal file
@ -0,0 +1,521 @@
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/*-
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* Copyright (c) 2018 Diane Bruce
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Based on uart_dev_pl011.c
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* Copyright (c) 2012 Semihalf.
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* All rights reserved.
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*/
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/*
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* The mini Uart has the following features:
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* - 7 or 8 bit operation.
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* - 1 start and 1 stop bit.
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* - No parities.
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* - Break generation.
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* - 8 symbols deep FIFOs for receive and transmit.
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* - SW controlled RTS, SW readable CTS.
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* - Auto flow control with programmable FIFO level.
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* - 16550 like registers.
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* - Baudrate derived from system clock.
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* This is a mini UART and it does NOT have the following capabilities:
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* - Break detection
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* - Framing errors detection.
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* - Parity bit
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* - Receive Time-out interrupt
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* - DCD, DSR, DTR or RI signals.
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* The implemented UART is not a 16650 compatible UART However as far
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* as possible the first 8 control and status registers are laid out
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* like a 16550 UART. All 16550 register bits which are not supported can
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* be written but will be ignored and read back as 0. All control bits
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* for simple UART receive/transmit operations are available.
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*/
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#include "opt_acpi.h"
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/machdep.h>
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#include <machine/pcpu.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#ifdef FDT
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#include <dev/uart/uart_cpu_fdt.h>
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#include <dev/ofw/ofw_bus.h>
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#endif
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#include <dev/uart/uart_bus.h>
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#include "uart_if.h"
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/* BCM2835 Micro UART registers and masks*/
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#define AUX_MU_IO_REG 0x00 /* I/O register */
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/*
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* According to errata bits 1 and 2 are swapped,
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* Also bits 2 and 3 are required to enable interrupts.
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*/
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#define AUX_MU_IER_REG 0x01
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#define IER_RXENABLE (1)
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#define IER_TXENABLE (1<<1)
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#define IER_REQUIRED (3<<2)
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#define IER_MASK_ALL (IER_TXENABLE|IER_RXENABLE)
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#define AUX_MU_IIR_REG 0x02
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#define IIR_READY (1)
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#define IIR_TXREADY (1<<1)
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#define IIR_RXREADY (1<<2)
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#define IIR_CLEAR (3<<1)
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#define AUX_MU_LCR_REG 0x03
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#define LCR_WLEN7 (0)
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#define LCR_WLEN8 (3)
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#define AUX_MU_MCR_REG 0x04
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#define AUX_MCR_RTS (1<<1)
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#define AUX_MU_LSR_REG 0x05
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#define LSR_RXREADY (1)
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#define LSR_OVRRUN (1<<1)
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#define LSR_TXEMPTY (1<<5)
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#define LSR_TXIDLE (1<<6)
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#define AUX_MU_MSR_REG 0x06
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#define MSR_CTS (1<<5)
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#define AUX_MU_SCRATCH_REG 0x07
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#define AUX_MU_CNTL_REG 0x08
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#define CNTL_RXENAB (1)
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#define CNTL_TXENAB (1<<1)
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#define AUX_MU_STAT_REG 0x09
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#define STAT_TX_SA (1<<1)
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#define STAT_RX_SA (1)
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#define AUX_MU_BAUD_REG 0x0a
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/*
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* FIXME: actual register size is SoC-dependent, we need to handle it
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*/
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#define __uart_getreg(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
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#define __uart_setreg(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
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/*
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* Low-level UART interface.
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*/
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static int uart_mu_probe(struct uart_bas *bas);
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static void uart_mu_init(struct uart_bas *bas, int, int, int, int);
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static void uart_mu_term(struct uart_bas *bas);
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static void uart_mu_putc(struct uart_bas *bas, int);
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static int uart_mu_rxready(struct uart_bas *bas);
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static int uart_mu_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_mu_ops = {
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.probe = uart_mu_probe,
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.init = uart_mu_init,
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.term = uart_mu_term,
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.putc = uart_mu_putc,
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.rxready = uart_mu_rxready,
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.getc = uart_mu_getc,
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};
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static int
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uart_mu_probe(struct uart_bas *bas)
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{
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return (0);
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}
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/*
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* According to the docs, the cpu clock is locked to 250Mhz when
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* the micro-uart is used
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*/
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#define CPU_CLOCK 250000000
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static void
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uart_mu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t line;
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uint32_t baud;
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/*
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* Zero all settings to make sure
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* UART is disabled and not configured
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*/
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line = 0x0;
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__uart_setreg(bas, AUX_MU_CNTL_REG, line);
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/* As I know UART is disabled I can setup the line */
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switch (databits) {
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case 7:
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line |= LCR_WLEN7;
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break;
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case 6:
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case 8:
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default:
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line |= LCR_WLEN8;
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break;
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}
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__uart_setreg(bas, AUX_MU_LCR_REG, line);
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/* See 2.2.1 BCM2835-ARM-Peripherals baudrate */
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if (baudrate != 0) {
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baud = CPU_CLOCK / (8 * baudrate);
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/* XXX
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* baud = cpu_clock() / (8 * baudrate);
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*/
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__uart_setreg(bas, AUX_MU_BAUD_REG, ((uint32_t)(baud & 0xFFFF)));
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}
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/* re-enable UART */
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__uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
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}
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static void
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uart_mu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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/* Mask all interrupts */
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__uart_setreg(bas, AUX_MU_IER_REG, 0);
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uart_mu_param(bas, baudrate, databits, stopbits, parity);
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}
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static void
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uart_mu_term(struct uart_bas *bas)
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{
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}
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static void
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uart_mu_putc(struct uart_bas *bas, int c)
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{
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/* Wait when TX FIFO full. Push character otherwise. */
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while ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXEMPTY) == 0)
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;
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__uart_setreg(bas, AUX_MU_IO_REG, c & 0xff);
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}
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static int
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uart_mu_rxready(struct uart_bas *bas)
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{
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return ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_RXREADY) != 0);
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}
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static int
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uart_mu_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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while(!uart_mu_rxready(bas))
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;
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c = __uart_getreg(bas, AUX_MU_IO_REG) & 0xff;
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct uart_mu_softc {
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struct uart_softc bas;
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uint16_t aux_ier; /* Interrupt mask */
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};
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static int uart_mu_bus_attach(struct uart_softc *);
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static int uart_mu_bus_detach(struct uart_softc *);
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static int uart_mu_bus_flush(struct uart_softc *, int);
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static int uart_mu_bus_getsig(struct uart_softc *);
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static int uart_mu_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int uart_mu_bus_ipend(struct uart_softc *);
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static int uart_mu_bus_param(struct uart_softc *, int, int, int, int);
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static int uart_mu_bus_probe(struct uart_softc *);
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static int uart_mu_bus_receive(struct uart_softc *);
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static int uart_mu_bus_setsig(struct uart_softc *, int);
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static int uart_mu_bus_transmit(struct uart_softc *);
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static void uart_mu_bus_grab(struct uart_softc *);
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static void uart_mu_bus_ungrab(struct uart_softc *);
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static kobj_method_t uart_mu_methods[] = {
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KOBJMETHOD(uart_attach, uart_mu_bus_attach),
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KOBJMETHOD(uart_detach, uart_mu_bus_detach),
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KOBJMETHOD(uart_flush, uart_mu_bus_flush),
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KOBJMETHOD(uart_getsig, uart_mu_bus_getsig),
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KOBJMETHOD(uart_ioctl, uart_mu_bus_ioctl),
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KOBJMETHOD(uart_ipend, uart_mu_bus_ipend),
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KOBJMETHOD(uart_param, uart_mu_bus_param),
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KOBJMETHOD(uart_probe, uart_mu_bus_probe),
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KOBJMETHOD(uart_receive, uart_mu_bus_receive),
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KOBJMETHOD(uart_setsig, uart_mu_bus_setsig),
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KOBJMETHOD(uart_transmit, uart_mu_bus_transmit),
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KOBJMETHOD(uart_grab, uart_mu_bus_grab),
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KOBJMETHOD(uart_ungrab, uart_mu_bus_ungrab),
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{ 0, 0 }
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};
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static struct uart_class uart_mu_class = {
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"aux-uart",
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uart_mu_methods,
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sizeof(struct uart_mu_softc),
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.uc_ops = &uart_mu_ops,
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.uc_range = 0x48,
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.uc_rclk = 0,
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.uc_rshift = 2
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};
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#ifdef FDT
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static struct ofw_compat_data fdt_compat_data[] = {
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{"brcm,bcm2835-aux-uart" , (uintptr_t)&uart_mu_class},
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{NULL, (uintptr_t)NULL},
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};
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UART_FDT_CLASS_AND_DEVICE(fdt_compat_data);
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#endif
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static int
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uart_mu_bus_attach(struct uart_softc *sc)
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{
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struct uart_mu_softc *psc;
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struct uart_bas *bas;
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psc = (struct uart_mu_softc *)sc;
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bas = &sc->sc_bas;
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/* Clear interrupts */
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__uart_setreg(bas, AUX_MU_IIR_REG, IIR_CLEAR);
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/* Enable interrupts */
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psc->aux_ier = (IER_RXENABLE|IER_TXENABLE|IER_REQUIRED);
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__uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
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sc->sc_txbusy = 0;
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return (0);
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}
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static int
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uart_mu_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_mu_bus_flush(struct uart_softc *sc, int what)
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{
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return (0);
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}
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static int
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uart_mu_bus_getsig(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_mu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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break;
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case UART_IOCTL_BAUD:
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*(int*)data = 115200;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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uart_mu_bus_ipend(struct uart_softc *sc)
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{
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struct uart_mu_softc *psc;
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struct uart_bas *bas;
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uint32_t ints;
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int ipend;
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psc = (struct uart_mu_softc *)sc;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ints = __uart_getreg(bas, AUX_MU_IIR_REG);
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ipend = 0;
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/*
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* According to docs only one of IIR_RXREADY
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* or IIR_TXREADY are valid eg. Only one or the other.
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*/
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if (ints & IIR_RXREADY) {
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ipend |= SER_INT_RXREADY;
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} else if (ints & IIR_TXREADY) {
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if (__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXIDLE) {
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if (sc->sc_txbusy)
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ipend |= SER_INT_TXIDLE;
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/* Disable TX interrupt */
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__uart_setreg(bas, AUX_MU_IER_REG,
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psc->aux_ier & ~IER_TXENABLE);
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}
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}
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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uart_mu_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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uart_lock(sc->sc_hwmtx);
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uart_mu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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uart_mu_bus_probe(struct uart_softc *sc)
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{
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/* MU always has 8 byte deep fifo */
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sc->sc_rxfifosz = 8;
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sc->sc_txfifosz = 8;
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device_set_desc(sc->sc_dev, "BCM2835 Mini-UART");
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return (0);
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}
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static int
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uart_mu_bus_receive(struct uart_softc *sc)
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{
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struct uart_mu_softc *psc;
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struct uart_bas *bas;
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uint32_t lsr, xc;
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int rx;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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psc = (struct uart_mu_softc *)sc;
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lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
|
||||
while (lsr & LSR_RXREADY) {
|
||||
xc = __uart_getreg(bas, AUX_MU_IO_REG);
|
||||
rx = xc & 0xff;
|
||||
if (uart_rx_full(sc)) {
|
||||
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
||||
break;
|
||||
}
|
||||
uart_rx_put(sc, rx);
|
||||
lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
|
||||
}
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
uart_mu_bus_setsig(struct uart_softc *sc, int sig)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
uart_mu_bus_transmit(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_mu_softc *psc;
|
||||
struct uart_bas *bas;
|
||||
int i;
|
||||
|
||||
psc = (struct uart_mu_softc *)sc;
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
|
||||
for (i = 0; i < sc->sc_txdatasz; i++) {
|
||||
__uart_setreg(bas, AUX_MU_IO_REG, sc->sc_txbuf[i] & 0xff);
|
||||
uart_barrier(bas);
|
||||
}
|
||||
|
||||
/* Mark busy and enable TX interrupt */
|
||||
sc->sc_txbusy = 1;
|
||||
__uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
|
||||
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
uart_mu_bus_grab(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_mu_softc *psc;
|
||||
struct uart_bas *bas;
|
||||
|
||||
psc = (struct uart_mu_softc *)sc;
|
||||
bas = &sc->sc_bas;
|
||||
|
||||
/* Disable interrupts on switch to polling */
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
__uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier &~IER_MASK_ALL);
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
}
|
||||
|
||||
static void
|
||||
uart_mu_bus_ungrab(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_mu_softc *psc;
|
||||
struct uart_bas *bas;
|
||||
|
||||
psc = (struct uart_mu_softc *)sc;
|
||||
bas = &sc->sc_bas;
|
||||
|
||||
/* Switch to using interrupts while not grabbed */
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
__uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
|
||||
__uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
}
|
||||
@ -23,14 +23,15 @@ uart_cpu_machine= ${_uart_cpu}
|
||||
|
||||
.if ${MACHINE} == "arm64"
|
||||
uart_dev_mvebu=uart_dev_mvebu.c
|
||||
uart_dev_mu=uart_dev_mu.c
|
||||
.endif
|
||||
|
||||
KMOD= uart
|
||||
SRCS= uart_bus_acpi.c ${uart_bus_ebus} uart_bus_isa.c uart_bus_pccard.c \
|
||||
uart_bus_pci.c uart_bus_puc.c uart_bus_scc.c \
|
||||
uart_core.c ${uart_cpu_machine} uart_dbg.c \
|
||||
${uart_dev_mvebu} uart_dev_ns8250.c uart_dev_quicc.c \
|
||||
uart_dev_sab82532.c uart_dev_z8530.c \
|
||||
${uart_dev_mvebu} uart_dev_ns8250.c ${uart_dev_mu} \
|
||||
uart_dev_quicc.c uart_dev_sab82532.c uart_dev_z8530.c \
|
||||
uart_if.c uart_if.h uart_subr.c uart_tty.c
|
||||
|
||||
SRCS+= acpi_if.h bus_if.h card_if.h device_if.h isa_if.h ${ofw_bus_if} \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user