Remove old cy driver files. They have been repo-copied to sys/dev/cy and
sys/dev/ic and adjusted to work there.
This commit is contained in:
bde
parent
919d8b8ca6
commit
5bfd2a373b
3005
sys/i386/isa/cy.c
3005
sys/i386/isa/cy.c
File diff suppressed because it is too large
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@ -1,75 +0,0 @@
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/*-
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* Copyright (c) 1995 Bruce Evans.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for Cyclades Cyclom-Y serial boards.
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*/
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/*
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* Cyclades register offsets. These are physical offsets for ISA boards
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* and physical offsets divided by 2 for PCI boards.
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*/
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#define CY8_SVCACKR 0x100 /* (r) */
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#define CY8_SVCACKT 0x200 /* (r) */
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#define CY8_SVCACKM 0x300 /* (r) */
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#define CY16_RESET 0x1400 /* (r) */
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#define CY_CLEAR_INTR 0x1800 /* intr ack address (w) */
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#define CY_MAX_CD1400s 8 /* for Cyclom-32Y */
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#define CY_CLOCK(version) ((version) >= 0x48 ? 60000000 : 25000000)
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#define CY_RTS_DTR_SWAPPED(version) ((version) >= 0x48)
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/*
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* The `cd' macros are for access to cd1400 registers. The `cy' macros
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* are for access to Cyclades registers. Both sets of macros scale the
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* register number to get an offset, but the scales are different for
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* mostly historical reasons.
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*/
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#ifdef CyDebug
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#define cd_inb(iobase, reg, cy_align) \
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(++cd_inbs, *((iobase) + (2 * (reg) << (cy_align))))
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#define cy_inb(iobase, reg, cy_align) \
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(++cy_inbs, *((iobase) + ((reg) << (cy_align))))
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#define cd_outb(iobase, reg, cy_align, val) \
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(++cd_outbs, (void)(*((iobase) + (2 * (reg) << (cy_align))) = (val)))
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#define cy_outb(iobase, reg, cy_align, val) \
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(++cy_outbs, (void)(*((iobase) + ((reg) << (cy_align))) = (val)))
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#else
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#define cd_inb(iobase, reg, cy_align) \
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(*((iobase) + (2 * (reg) << (cy_align))))
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#define cy_inb(iobase, reg, cy_align) \
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(*((iobase) + ((reg) << (cy_align))))
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#define cd_outb(iobase, reg, cy_align, val) \
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((void)(*((iobase) + (2 * (reg) << (cy_align))) = (val)))
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#define cy_outb(iobase, reg, cy_align, val) \
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((void)(*((iobase) + ((reg) << (cy_align))) = (val)))
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#endif
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@ -1,203 +0,0 @@
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/*-
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* cyclades cyclom-y serial driver
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* Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993
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*
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* Copyright (c) 1993 Andrew Herbert.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name Andrew Herbert may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for Cirrus Logic CD1400 serial/parallel chips.
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*/
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#define CD1400_NO_OF_CHANNELS 4 /* 4 serial channels per chip */
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#define CD1400_RX_FIFO_SIZE 12
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#define CD1400_TX_FIFO_SIZE 12
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/*
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* Global registers.
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*/
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#define CD1400_GFRCR 0x40 /* global firmware revision code */
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#define CD1400_CAR 0x68 /* channel access */
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#define CD1400_CAR_CHAN (3<<0) /* channel select */
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#define CD1400_GCR 0x4B /* global configuration */
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#define CD1400_GCR_PARALLEL (1<<7) /* channel 0 is parallel */
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#define CD1400_SVRR 0x67 /* service request */
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#define CD1400_SVRR_MDMCH (1<<2)
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#define CD1400_SVRR_TXRDY (1<<1)
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#define CD1400_SVRR_RXRDY (1<<0)
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#define CD1400_RICR 0x44 /* receive interrupting channel */
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#define CD1400_TICR 0x45 /* transmit interrupting channel */
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#define CD1400_MICR 0x46 /* modem interrupting channel */
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#define CD1400_RIR 0x6B /* receive interrupt status */
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#define CD1400_RIR_RDIREQ (1<<7) /* rx service required */
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#define CD1400_RIR_RBUSY (1<<6) /* rx service in progress */
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#define CD1400_RIR_CHAN (3<<0) /* channel select */
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#define CD1400_TIR 0x6A /* transmit interrupt status */
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#define CD1400_TIR_RDIREQ (1<<7) /* tx service required */
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#define CD1400_TIR_RBUSY (1<<6) /* tx service in progress */
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#define CD1400_TIR_CHAN (3<<0) /* channel select */
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#define CD1400_MIR 0x69 /* modem interrupt status */
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#define CD1400_MIR_RDIREQ (1<<7) /* modem service required */
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#define CD1400_MIR_RBUSY (1<<6) /* modem service in progress */
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#define CD1400_MIR_CHAN (3<<0) /* channel select */
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#define CD1400_PPR 0x7E /* prescaler period */
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#define CD1400_PPR_PRESCALER 512
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/*
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* Virtual registers.
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*/
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#define CD1400_RIVR 0x43 /* receive interrupt vector */
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#define CD1400_RIVR_EXCEPTION (1<<2) /* receive exception bit */
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#define CD1400_TIVR 0x42 /* transmit interrupt vector */
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#define CD1400_MIVR 0x41 /* modem interrupt vector */
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#define CD1400_TDR 0x63 /* transmit data */
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#define CD1400_RDSR 0x62 /* receive data/status */
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#define CD1400_RDSR_TIMEOUT (1<<7) /* rx timeout */
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#define CD1400_RDSR_SPECIAL_SHIFT 4 /* rx special char shift */
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#define CD1400_RDSR_SPECIAL (7<<4) /* rx special char */
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#define CD1400_RDSR_BREAK (1<<3) /* rx break */
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#define CD1400_RDSR_PE (1<<2) /* rx parity error */
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#define CD1400_RDSR_FE (1<<1) /* rx framing error */
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#define CD1400_RDSR_OE (1<<0) /* rx overrun error */
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#define CD1400_MISR 0x4C /* modem interrupt status */
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#define CD1400_MISR_DSRd (1<<7) /* DSR delta */
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#define CD1400_MISR_CTSd (1<<6) /* CTS delta */
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#define CD1400_MISR_RId (1<<5) /* RI delta */
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#define CD1400_MISR_CDd (1<<4) /* CD delta */
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#define CD1400_EOSRR 0x60 /* end of service request */
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/*
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* Channel registers.
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*/
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#define CD1400_LIVR 0x18 /* local interrupt vector */
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#define CD1400_CCR 0x05 /* channel control */
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#define CD1400_CCR_CMDRESET (1<<7) /* enables following: */
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#define CD1400_CCR_FTF (1<<1) /* flush tx fifo */
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#define CD1400_CCR_FULLRESET (1<<0) /* full reset */
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#define CD1400_CCR_CHANRESET 0 /* current channel */
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#define CD1400_CCR_CMDCORCHG (1<<6) /* enables following: */
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#define CD1400_CCR_COR3 (1<<3) /* COR3 changed */
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#define CD1400_CCR_COR2 (1<<2) /* COR2 changed */
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#define CD1400_CCR_COR1 (1<<1) /* COR1 changed */
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#define CD1400_CCR_CMDSENDSC (1<<5) /* enables following: */
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#define CD1400_CCR_SC (7<<0) /* special char 1-4 */
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#define CD1400_CCR_CMDCHANCTL (1<<4) /* enables following: */
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#define CD1400_CCR_XMTEN (1<<3) /* tx enable */
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#define CD1400_CCR_XMTDIS (1<<2) /* tx disable */
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#define CD1400_CCR_RCVEN (1<<1) /* rx enable */
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#define CD1400_CCR_RCVDIS (1<<0) /* rx disable */
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#define CD1400_SRER 0x06 /* service request enable */
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#define CD1400_SRER_MDMCH (1<<7) /* modem change */
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#define CD1400_SRER_RXDATA (1<<4) /* rx data */
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#define CD1400_SRER_TXRDY (1<<2) /* tx fifo empty */
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#define CD1400_SRER_TXMPTY (1<<1) /* tx shift reg empty */
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#define CD1400_SRER_NNDT (1<<0) /* no new data */
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#define CD1400_COR1 0x08 /* channel option 1 */
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#define CD1400_COR1_PARODD (1<<7)
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#define CD1400_COR1_PARNORMAL (2<<5)
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#define CD1400_COR1_PARFORCE (1<<5) /* odd/even = force 1/0 */
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#define CD1400_COR1_PARNONE (0<<5)
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#define CD1400_COR1_NOINPCK (1<<4)
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#define CD1400_COR1_STOP2 (2<<2)
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#define CD1400_COR1_STOP15 (1<<2) /* 1.5 stop bits */
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#define CD1400_COR1_STOP1 (0<<2)
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#define CD1400_COR1_CS8 (3<<0)
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#define CD1400_COR1_CS7 (2<<0)
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#define CD1400_COR1_CS6 (1<<0)
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#define CD1400_COR1_CS5 (0<<0)
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#define CD1400_COR2 0x09 /* channel option 2 */
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#define CD1400_COR2_IXANY (1<<7) /* implied XON mode */
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#define CD1400_COR2_IXOFF (1<<6) /* in-band tx flow control */
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#define CD1400_COR2_ETC (1<<5) /* embedded tx command */
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#define CD1400_ETC_CMD 0x00 /* start an ETC */
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#define CD1400_ETC_SENDBREAK 0x81
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#define CD1400_ETC_INSERTDELAY 0x82
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#define CD1400_ETC_STOPBREAK 0x83
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#define CD1400_COR2_LLM (1<<4) /* local loopback mode */
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#define CD1400_COR2_RLM (1<<3) /* remote loopback mode */
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#define CD1400_COR2_RTSAO (1<<2) /* RTS auto output */
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#define CD1400_COR2_CCTS_OFLOW (1<<1) /* CTS auto enable */
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#define CD1400_COR2_CDSR_OFLOW (1<<0) /* DSR auto enable */
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#define CD1400_COR3 0x0A /* channel option 3 */
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#define CD1400_COR3_SCDRNG (1<<7) /* special char detect range */
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#define CD1400_COR3_SCD34 (1<<6) /* special char detect 3-4 */
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#define CD1400_COR3_FTC (1<<5) /* flow control transparency */
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#define CD1400_COR3_SCD12 (1<<4) /* special char detect 1-2 */
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#define CD1400_COR3_RXTH (15<<0) /* rx fifo threshold */
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#define CD1400_COR4 0x1E /* channel option 4 */
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#define CD1400_COR4_IGNCR (1<<7)
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#define CD1400_COR4_ICRNL (1<<6)
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#define CD1400_COR4_INLCR (1<<5)
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#define CD1400_COR4_IGNBRK (1<<4)
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#define CD1400_COR4_NOBRKINT (1<<3)
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#define CD1400_COR4_PFO_ESC (4<<0) /* parity/framing/overrun... */
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#define CD1400_COR4_PFO_NUL (3<<0)
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#define CD1400_COR4_PFO_DISCARD (2<<0)
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#define CD1400_COR4_PFO_GOOD (1<<0)
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#define CD1400_COR4_PFO_EXCEPTION (0<<0)
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#define CD1400_COR5 0x1F /* channel option 5 */
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#define CD1400_COR5_ISTRIP (1<<7)
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#define CD1400_COR5_LNEXT (1<<6)
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#define CD1400_COR5_CMOE (1<<5) /* char matching on error */
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#define CD1400_COR5_EBD (1<<2) /* end of break detected */
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#define CD1400_COR5_ONLCR (1<<1)
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#define CD1400_COR5_OCRNL (1<<0)
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#define CD1400_CCSR 0x0B /* channel control status */
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#define CD1400_RDCR 0x0E /* received data count */
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#define CD1400_SCHR1 0x1A /* special character 1 */
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#define CD1400_SCHR2 0x1B /* special character 2 */
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#define CD1400_SCHR3 0x1C /* special character 3 */
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#define CD1400_SCHR4 0x1D /* special character 4 */
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#define CD1400_SCRL 0x22 /* special character range, low */
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#define CD1400_SCRH 0x23 /* special character range, high */
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#define CD1400_LNC 0x24 /* lnext character */
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#define CD1400_MCOR1 0x15 /* modem change option 1 */
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#define CD1400_MCOR1_DSRzd (1<<7) /* DSR one-to-zero delta */
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#define CD1400_MCOR1_CTSzd (1<<6)
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#define CD1400_MCOR1_RIzd (1<<5)
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#define CD1400_MCOR1_CDzd (1<<4)
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#define CD1400_MCOR1_DTRth (15<<0) /* dtrflow threshold */
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#define CD1400_MCOR2 0x16 /* modem change option 2 */
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#define CD1400_MCOR2_DSRod (1<<7) /* DSR zero-to-one delta */
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#define CD1400_MCOR2_CTSod (1<<6)
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#define CD1400_MCOR2_RIod (1<<5)
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#define CD1400_MCOR2_CDod (1<<4)
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#define CD1400_RTPR 0x21 /* receive timeout period */
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#define CD1400_MSVR1 0x6C /* modem signal value 1 */
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#define CD1400_MSVR1_RTS (1<<0) /* RTS line (r/w) */
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#define CD1400_MSVR2 0x6D /* modem signal value 2 */
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#define CD1400_MSVR2_DSR (1<<7) /* !DSR line (r) */
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#define CD1400_MSVR2_CTS (1<<6) /* !CTS line (r) */
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#define CD1400_MSVR2_RI (1<<5) /* !RI line (r) */
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#define CD1400_MSVR2_CD (1<<4) /* !CD line (r) */
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#define CD1400_MSVR2_DTR (1<<1) /* DTR line (r/w) */
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#define CD1400_PSVR 0x6F /* printer signal value */
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#define CD1400_RBPR 0x78 /* receive baud rate period */
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#define CD1400_RCOR 0x7C /* receive clock option */
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#define CD1400_TBPR 0x72 /* transmit baud rate period */
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#define CD1400_TCOR 0x76 /* transmit clock option */
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198
sys/pci/cy_pci.c
198
sys/pci/cy_pci.c
@ -1,198 +0,0 @@
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/*
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* Copyright (c) 1996, David Greenman
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* All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
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/*
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* Cyclades Y PCI serial interface driver
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cy_pci_fastintr.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#define CY_PCI_BASE_ADDR0 0x10
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#define CY_PCI_BASE_ADDR1 0x14
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#define CY_PCI_BASE_ADDR2 0x18
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#define CY_PLX_9050_ICS 0x4c
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#define CY_PLX_9060_ICS 0x68
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#define CY_PLX_9050_ICS_IENABLE 0x040
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#define CY_PLX_9050_ICS_LOCAL_IENABLE 0x001
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#define CY_PLX_9050_ICS_LOCAL_IPOLARITY 0x002
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#define CY_PLX_9060_ICS_IENABLE 0x100
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#define CY_PLX_9060_ICS_LOCAL_IENABLE 0x800
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/* Cyclom-Y Custom Register for PLX ID. */
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#define PLX_VER 0x3400
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#define PLX_9050 0x0b
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#define PLX_9060 0x0c
|
||||
#define PLX_9080 0x0d
|
||||
|
||||
extern devclass_t cy_devclass;
|
||||
|
||||
void *cyattach_common(u_char volatile *iobase, int cy_align);
|
||||
driver_intr_t cyintr;
|
||||
|
||||
static int cy_pci_attach(device_t dev);
|
||||
static int cy_pci_probe(device_t dev);
|
||||
|
||||
static device_method_t cy_pci_methods[] = {
|
||||
/* Device interface. */
|
||||
DEVMETHOD(device_probe, cy_pci_probe),
|
||||
DEVMETHOD(device_attach, cy_pci_attach),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t cy_pci_driver = {
|
||||
"cy",
|
||||
cy_pci_methods,
|
||||
0,
|
||||
};
|
||||
|
||||
DRIVER_MODULE(cy, pci, cy_pci_driver, cy_devclass, 0, 0);
|
||||
MODULE_DEPEND(cy, pci, 1, 1, 1);
|
||||
|
||||
static int
|
||||
cy_pci_probe(dev)
|
||||
device_t dev;
|
||||
{
|
||||
u_int32_t device_id;
|
||||
|
||||
device_id = pci_get_devid(dev);
|
||||
device_id &= ~0x00060000;
|
||||
if (device_id != 0x0100120e && device_id != 0x0101120e)
|
||||
return (ENXIO);
|
||||
device_set_desc(dev, "Cyclades Cyclom-Y Serial Adapter");
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
cy_pci_attach(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct resource *ioport_res, *irq_res, *mem_res;
|
||||
void *irq_cookie, *vaddr, *vsc;
|
||||
u_int32_t ioport;
|
||||
int irq_setup, ioport_rid, irq_rid, mem_rid;
|
||||
u_char plx_ver;
|
||||
|
||||
ioport_res = NULL;
|
||||
irq_res = NULL;
|
||||
mem_res = NULL;
|
||||
|
||||
ioport_rid = CY_PCI_BASE_ADDR1;
|
||||
ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
|
||||
0ul, ~0ul, 0ul, RF_ACTIVE);
|
||||
if (ioport_res == NULL) {
|
||||
device_printf(dev, "ioport resource allocation failed\n");
|
||||
goto fail;
|
||||
}
|
||||
ioport = rman_get_start(ioport_res);
|
||||
|
||||
mem_rid = CY_PCI_BASE_ADDR2;
|
||||
mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &mem_rid,
|
||||
0ul, ~0ul, 0ul, RF_ACTIVE);
|
||||
if (mem_res == NULL) {
|
||||
device_printf(dev, "memory resource allocation failed\n");
|
||||
goto fail;
|
||||
}
|
||||
vaddr = rman_get_virtual(mem_res);
|
||||
|
||||
vsc = cyattach_common(vaddr, 1);
|
||||
if (vsc == NULL) {
|
||||
device_printf(dev, "no ports found!\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
irq_rid = 0;
|
||||
irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, 0ul, ~0ul, 0ul,
|
||||
RF_SHAREABLE | RF_ACTIVE);
|
||||
if (irq_res == NULL) {
|
||||
device_printf(dev, "interrupt resource allocation failed\n");
|
||||
goto fail;
|
||||
}
|
||||
#ifdef CY_PCI_FASTINTR
|
||||
irq_setup = bus_setup_intr(dev, irq_res, INTR_TYPE_TTY | INTR_FAST,
|
||||
cyintr, vsc, &irq_cookie);
|
||||
#else
|
||||
irq_setup = ENXIO;
|
||||
#endif
|
||||
if (irq_setup != 0)
|
||||
irq_setup = bus_setup_intr(dev, irq_res, INTR_TYPE_TTY,
|
||||
cyintr, vsc, &irq_cookie);
|
||||
if (irq_setup != 0) {
|
||||
device_printf(dev, "interrupt setup failed\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the "local" interrupt input to generate a
|
||||
* PCI interrupt.
|
||||
*/
|
||||
plx_ver = *((u_char *)vaddr + PLX_VER) & 0x0f;
|
||||
switch (plx_ver) {
|
||||
case PLX_9050:
|
||||
outw(ioport + CY_PLX_9050_ICS,
|
||||
CY_PLX_9050_ICS_IENABLE | CY_PLX_9050_ICS_LOCAL_IENABLE |
|
||||
CY_PLX_9050_ICS_LOCAL_IPOLARITY);
|
||||
break;
|
||||
case PLX_9060:
|
||||
case PLX_9080:
|
||||
default: /* Old board, use PLX_9060 values. */
|
||||
outw(ioport + CY_PLX_9060_ICS,
|
||||
inw(ioport + CY_PLX_9060_ICS) | CY_PLX_9060_ICS_IENABLE |
|
||||
CY_PLX_9060_ICS_LOCAL_IENABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
return (0);
|
||||
|
||||
fail:
|
||||
if (ioport_res != NULL)
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid,
|
||||
ioport_res);
|
||||
if (irq_res != NULL)
|
||||
bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
|
||||
if (mem_res != NULL)
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, mem_rid, mem_res);
|
||||
return (ENXIO);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user