amd64: Eliminate write only cpu_fxsr.
Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D38289 MFC after: 1 week
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@ -279,7 +279,7 @@ initializecpu(void)
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cr4 = rcr4();
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cr4 = rcr4();
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if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
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if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
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cr4 |= CR4_FXSR | CR4_XMM;
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cr4 |= CR4_FXSR | CR4_XMM;
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cpu_fxsr = hw_instruction_sse = 1;
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hw_instruction_sse = 1;
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}
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}
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if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
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if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
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cr4 |= CR4_FSGSBASE;
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cr4 |= CR4_FSGSBASE;
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@ -175,6 +175,7 @@ SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
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&lazy_fpu_switch, 0,
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&lazy_fpu_switch, 0,
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"Lazily load FPU context after context switch");
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"Lazily load FPU context after context switch");
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u_int cpu_fxsr; /* SSE enabled */
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int use_xsave;
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int use_xsave;
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uint64_t xsave_mask;
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uint64_t xsave_mask;
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static uma_zone_t fpu_save_area_zone;
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static uma_zone_t fpu_save_area_zone;
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@ -36,6 +36,7 @@
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#include <x86/x86_var.h>
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#include <x86/x86_var.h>
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extern u_int cpu_fxsr;
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extern u_int cyrix_did;
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extern u_int cyrix_did;
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#if defined(I586_CPU) && !defined(NO_F00F_HACK)
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#if defined(I586_CPU) && !defined(NO_F00F_HACK)
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extern int has_f00f_bug;
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extern int has_f00f_bug;
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@ -53,7 +53,6 @@ extern u_int cpu_stdext_feature;
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extern u_int cpu_stdext_feature2;
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extern u_int cpu_stdext_feature2;
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extern u_int cpu_stdext_feature3;
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extern u_int cpu_stdext_feature3;
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extern uint64_t cpu_ia32_arch_caps;
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extern uint64_t cpu_ia32_arch_caps;
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extern u_int cpu_fxsr;
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extern u_int cpu_high;
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extern u_int cpu_high;
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extern u_int cpu_id;
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extern u_int cpu_id;
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extern u_int cpu_max_ext_state_size;
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extern u_int cpu_max_ext_state_size;
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@ -106,7 +106,6 @@ u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
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u_int cpu_procinfo2; /* Multicore info */
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u_int cpu_procinfo2; /* Multicore info */
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char cpu_vendor[20]; /* CPU Origin code */
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char cpu_vendor[20]; /* CPU Origin code */
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u_int cpu_vendor_id; /* CPU vendor ID */
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u_int cpu_vendor_id; /* CPU vendor ID */
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u_int cpu_fxsr; /* SSE enabled */
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u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
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u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
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u_int cpu_clflush_line_size = 32;
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u_int cpu_clflush_line_size = 32;
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u_int cpu_stdext_feature; /* %ebx */
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u_int cpu_stdext_feature; /* %ebx */
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