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Document the fact that some Core2 family CPUs lack fixed-function counters.

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This commit is contained in:
Joseph Koshy 2009-06-09 06:36:29 +00:00
parent b47ea38e01
commit 5c9306fd41
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=193810
1 changed files with 4 additions and 3 deletions
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7
lib/libpmc/pmc.core2.3
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@ -1,4 +1,4 @@
.\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
.\" Copyright (c) 2008,2009 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
@ -23,7 +23,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd November 12, 2008
.Dd June 8, 2009
.Os
.Dt PMC.CORE2 3
.Sh NAME
@ -42,7 +42,7 @@ family CPUs
CPUs contain PMCs conforming to version 2 of the
.Tn Intel
performance measurement architecture.
These CPUs contains two classes of PMCs:
These CPUs may contain upto two classes of PMCs:
.Bl -tag -width "Li PMC_CLASS_IAP"
.It Li PMC_CLASS_IAF
Fixed-function counters that count only one hardware event per counter.
@ -66,6 +66,7 @@ Intel Core2 PMCs are documented in
.Ss CORE2 FIXED FUNCTION PMCS
These PMCs and their supported events are documented in
.Xr pmc.iaf 3 .
Not all CPUs in this family implement fixed-function counters.
.Ss CORE2 PROGRAMMABLE PMCS
The programmable PMCs support the following capabilities:
.Bl -column "PMC_CAP_INTERRUPT" "Support"