ioat(4): Add support for interrupt coalescing
In I/OAT, this is done through the INTRDELAY register. On supported platforms, this register can coalesce interrupts in a set period to avoid excessive interrupt load for small descriptor workflows. The period is configurable anywhere from 1 microsecond to 16.38 milliseconds, in microsecond granularity. Sponsored by: EMC / Isilon Storage Division
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=292228
@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 9, 2015
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.Dd December 14, 2015
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.Dt IOAT 4
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.Os
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.Sh NAME
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@ -63,6 +63,10 @@ In
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.Fn ioat_get_dmaengine "uint32_t channel_index"
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.Ft void
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.Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine"
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.Ft int
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.Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay"
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.Ft uint16_t
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.Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine"
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.Ft void
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.Fn ioat_acquire "bus_dmaengine_t dmaengine"
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.Ft void
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@ -129,6 +133,20 @@ flag.
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For example, a user might submit multiple operations to the same channel and
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only enable an interrupt and callback for the last operation.
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.Pp
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The hardware can delay and coalesce interrupts on a given channel for a
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configurable period of time, in microseconds.
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This may be desired to reduce the processing and interrupt overhead per
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descriptor, especially for workflows consisting of many small operations.
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Software can control this on a per-channel basis with the
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.Fn ioat_set_interrupt_coalesce
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API.
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The
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.Fn ioat_get_max_coalesce_period
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API can be used to determine the maximum coalescing period supported by the
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hardware, in microseconds.
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Current platforms support up to a 16.383 millisecond coalescing period.
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Optimal configuration will vary by workflow and desired operation latency.
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.Pp
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All operations are safe to use in a non-blocking context with the
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.Ar DMA_NO_WAIT
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flag.
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@ -404,6 +404,11 @@ ioat3_attach(device_t device)
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xfercap = ioat_read_xfercap(ioat);
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ioat->max_xfer_size = 1 << xfercap;
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ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
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IOAT_INTRDELAY_SUPPORTED) != 0;
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if (ioat->intrdelay_supported)
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ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
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/* TODO: need to check DCA here if we ever do XOR/PQ */
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mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
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@ -730,6 +735,32 @@ ioat_put_dmaengine(bus_dmaengine_t dmaengine)
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ioat_put(ioat, IOAT_DMAENGINE_REF);
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}
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int
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ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
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{
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struct ioat_softc *ioat;
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ioat = to_ioat_softc(dmaengine);
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if (!ioat->intrdelay_supported)
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return (ENODEV);
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if (delay > ioat->intrdelay_max)
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return (ERANGE);
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ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
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ioat->cached_intrdelay =
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ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
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return (0);
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}
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uint16_t
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ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
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{
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struct ioat_softc *ioat;
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ioat = to_ioat_softc(dmaengine);
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return (ioat->intrdelay_max);
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}
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void
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ioat_acquire(bus_dmaengine_t dmaengine)
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{
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@ -1641,6 +1672,11 @@ ioat_setup_sysctl(device_t device)
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&ioat->version, 0, "HW version (0xMM form)");
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SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
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&ioat->max_xfer_size, 0, "HW maximum transfer size");
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SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
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&ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
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SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
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&ioat->intrdelay_max, 0,
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"Maximum configurable INTRDELAY on this channel (microseconds)");
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tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL,
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"IOAT channel internal state");
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@ -1671,6 +1707,10 @@ ioat_setup_sysctl(device_t device)
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CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A",
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"String of the channel status");
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SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
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&ioat->cached_intrdelay, 0,
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"Current INTRDELAY on this channel (cached, microseconds)");
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tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL,
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"Big hammers (mostly for testing)");
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hammer = SYSCTL_CHILDREN(tmp);
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@ -60,6 +60,28 @@ bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index);
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/* Release the DMA channel */
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void ioat_put_dmaengine(bus_dmaengine_t dmaengine);
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/*
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* Set interrupt coalescing on a DMA channel.
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*
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* The argument is in microseconds. A zero value disables coalescing. Any
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* other value delays interrupt generation for N microseconds to provide
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* opportunity to coalesce multiple operations into a single interrupt.
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*
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* Returns an error status, or zero on success.
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*
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* - ERANGE if the given value exceeds the delay supported by the hardware.
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* (All current hardware supports a maximum of 0x3fff microseconds delay.)
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* - ENODEV if the hardware does not support interrupt coalescing.
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*/
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int ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay);
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/*
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* Return the maximum supported coalescing period, for use in
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* ioat_set_interrupt_coalesce(). If the hardware does not support coalescing,
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* returns zero.
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*/
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uint16_t ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine);
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/*
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* Acquire must be called before issuing an operation to perform. Release is
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* called after. Multiple operations can be issued within the context of one
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@ -50,6 +50,10 @@ __FBSDID("$FreeBSD$");
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#define IOAT_VER_3_3 0x33
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#define IOAT_INTRDELAY_OFFSET 0x0C
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#define IOAT_INTRDELAY_SUPPORTED (1 << 15)
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/* Reserved. (1 << 14) */
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/* [13:0] is the coalesce period, in microseconds. */
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#define IOAT_INTRDELAY_US_MASK ((1 << 14) - 1)
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#define IOAT_CS_STATUS_OFFSET 0x0E
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@ -373,6 +373,8 @@ struct ioat_softc {
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struct resource *pci_resource;
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uint32_t max_xfer_size;
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uint32_t capabilities;
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uint16_t intrdelay_max;
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uint16_t cached_intrdelay;
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struct resource *res;
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int rid;
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@ -393,6 +395,7 @@ struct ioat_softc {
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boolean_t is_completion_pending;
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boolean_t is_reset_pending;
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boolean_t is_channel_running;
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boolean_t intrdelay_supported;
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uint32_t head;
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uint32_t tail;
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