[POWERPC] Floating-Point Exception trap support
Add support for Floating-Point Exception traps on 32 and 64 bit platforms. Also make sure to clean FPSCR on EXEC and thread exit Author of initial version: Renato Riolino <renato.riolino@eldorad.org.br> Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D23623
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=367416
@ -163,6 +163,25 @@ mttb(u_quad_t time)
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mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
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}
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static __inline register_t
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mffs(void)
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{
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register_t value;
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__asm __volatile ("mffs 0; stfd 0,0(%0)"
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:: "b"(&value));
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return (value);
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}
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static __inline void
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mtfsf(register_t value)
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{
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__asm __volatile ("lfd 0,0(%0); mtfsf 0xff,0"
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:: "b"(&value));
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}
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static __inline void
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eieio(void)
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{
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@ -75,6 +75,8 @@
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void enable_fpu(struct thread *);
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void save_fpu(struct thread *);
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void save_fpu_nodrop(struct thread *);
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void cleanup_fpscr(void);
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u_int get_fpu_exception(struct thread *);
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#endif /* _KERNEL */
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@ -88,7 +88,7 @@
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#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
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#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
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#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
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#define PSL_FE_DFLT PSL_FE_DIS /* default == none */
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#define PSL_FE_DFLT PSL_FE_PREC /* default == precise */
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#ifndef LOCORE
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extern register_t psl_kernset; /* Default MSR values for kernel */
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@ -240,9 +240,12 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
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}
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/*
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* Save the floating-point state, if necessary, then copy it.
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* Set Floating Point facility to "Ignore Exceptions Mode" so signal
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* handler can run.
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*/
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/* XXX */
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if (td->td_pcb->pcb_flags & PCB_FPU)
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tf->srr1 = tf->srr1 & ~(PSL_FE0 | PSL_FE1);
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/*
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* Set up the registers to return to sigcode.
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@ -333,6 +336,13 @@ sys_sigreturn(struct thread *td, struct sigreturn_args *uap)
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kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
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/*
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* Save FPU state if needed. User may have changed it on
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* signal handler
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*/
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if (uc.uc_mcontext.mc_srr1 & PSL_FP)
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save_fpu(td);
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CTR3(KTR_SIG, "sigreturn: return td=%p pc=%#x sp=%#x",
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td, uc.uc_mcontext.mc_srr0, uc.uc_mcontext.mc_gpr[1]);
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@ -556,6 +566,8 @@ cleanup_power_extras(struct thread *td)
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mtspr(SPR_FSCR, 0);
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if (pcb_flags & PCB_CDSCR)
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mtspr(SPR_DSCRP, 0);
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cleanup_fpscr();
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}
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/*
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@ -826,6 +838,14 @@ freebsd32_sigreturn(struct thread *td, struct freebsd32_sigreturn_args *uap)
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kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
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/*
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* Save FPU state if needed. User may have changed it on
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* signal handler
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*/
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if (uc.uc_mcontext.mc_srr1 & PSL_FP)
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save_fpu(td);
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CTR3(KTR_SIG, "sigreturn: return td=%p pc=%#x sp=%#x",
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td, uc.uc_mcontext.mc_srr0, uc.uc_mcontext.mc_gpr[1]);
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@ -48,7 +48,7 @@ __FBSDID("$FreeBSD$");
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static void
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save_fpu_int(struct thread *td)
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{
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int msr;
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register_t msr;
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struct pcb *pcb;
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pcb = td->td_pcb;
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@ -102,7 +102,7 @@ save_fpu_int(struct thread *td)
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void
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enable_fpu(struct thread *td)
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{
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int msr;
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register_t msr;
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struct pcb *pcb;
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struct trapframe *tf;
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@ -208,3 +208,58 @@ save_fpu_nodrop(struct thread *td)
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if (td == PCPU_GET(fputhread))
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save_fpu_int(td);
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}
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/*
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* Clear Floating-Point Status and Control Register
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*/
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void
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cleanup_fpscr()
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{
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register_t msr;
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msr = mfmsr();
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mtmsr(msr | PSL_FP | PSL_VSX);
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mtfsf(0);
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isync();
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mtmsr(msr);
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}
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/*
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* * Returns the current fp exception
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* */
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u_int
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get_fpu_exception(struct thread *td)
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{
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register_t msr;
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u_int ucode;
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register_t reg;
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critical_enter();
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msr = mfmsr();
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mtmsr(msr | PSL_FP);
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reg = mffs();
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isync();
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mtmsr(msr);
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critical_exit();
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if (reg & FPSCR_ZX)
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ucode = FPE_FLTDIV;
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else if (reg & FPSCR_OX)
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ucode = FPE_FLTOVF;
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else if (reg & FPSCR_UX)
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ucode = FPE_FLTUND;
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else if (reg & FPSCR_XX)
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ucode = FPE_FLTRES;
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else
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ucode = FPE_FLTINV;
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return ucode;
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}
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@ -405,16 +405,24 @@ trap(struct trapframe *frame)
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#endif
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sig = SIGTRAP;
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ucode = TRAP_BRKPT;
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} else {
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break;
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}
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if ((frame->srr1 & EXC_PGM_FPENABLED) &&
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(td->td_pcb->pcb_flags & PCB_FPU))
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sig = SIGFPE;
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else
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sig = ppc_instr_emulate(frame, td);
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if (sig == SIGILL) {
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if (frame->srr1 & EXC_PGM_PRIV)
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ucode = ILL_PRVOPC;
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else if (frame->srr1 & EXC_PGM_ILLEGAL)
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ucode = ILL_ILLOPC;
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} else if (sig == SIGFPE)
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ucode = FPE_FLTINV; /* Punt for now, invalid operation. */
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} else if (sig == SIGFPE) {
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ucode = get_fpu_exception(td);
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}
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break;
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case EXC_MCHK:
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@ -964,7 +972,7 @@ fix_unaligned(struct thread *td, struct trapframe *frame)
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static void
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normalize_inputs(void)
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{
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unsigned long msr;
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register_t msr;
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/* enable VSX */
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msr = mfmsr();
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