Add support for new LAW registers in QorIQ SoCs.
QorIQ SoCs (e5500 core, P5 family) have 2 BARs for local access windows, while MPC85XX, and P1/P2 families use only a single BAR register. This also adds the QORIQ_DPAA option, mutually exclusive to MPC85XX, to handle this difference. Obtained from: Semihalf Sponsored by: Alex Perez/Inertial Computing
This commit is contained in:
parent
a065797aa4
commit
5d89896cbf
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=291008
@ -74,7 +74,7 @@ dev/syscons/scvtb.c optional sc
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dev/tsec/if_tsec.c optional tsec
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dev/tsec/if_tsec_fdt.c optional tsec fdt
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dev/uart/uart_cpu_powerpc.c optional uart
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dev/usb/controller/ehci_fsl.c optional ehci mpc85xx
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dev/usb/controller/ehci_fsl.c optional ehci mpc85xx | ehci qoriq_dpaa
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dev/vt/hw/ofwfb/ofwfb.c optional vt aim
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kern/kern_clocksource.c standard
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kern/subr_dummy_vdso_tc.c standard
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@ -133,15 +133,15 @@ powerpc/mikrotik/platform_rb.c optional mikrotik
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powerpc/mpc85xx/atpic.c optional mpc85xx isa
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powerpc/mpc85xx/ds1553_bus_fdt.c optional ds1553 fdt
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powerpc/mpc85xx/ds1553_core.c optional ds1553
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powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc
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powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc | qoriq_dpaa sdhc
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powerpc/mpc85xx/i2c.c optional iicbus fdt
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powerpc/mpc85xx/isa.c optional mpc85xx isa
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powerpc/mpc85xx/lbc.c optional mpc85xx
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powerpc/mpc85xx/mpc85xx.c optional mpc85xx
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powerpc/mpc85xx/lbc.c optional mpc85xx | qoriq_dpaa
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powerpc/mpc85xx/mpc85xx.c optional mpc85xx | qoriq_dpaa
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powerpc/mpc85xx/mpc85xx_gpio.c optional mpc85xx gpio
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powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx
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powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx
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powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx
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powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx | qoriq_dpaa
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powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx | pci qoriq_dpaa
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powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx | pci qoriq_dpaa
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powerpc/ofw/ofw_machdep.c standard
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powerpc/ofw/ofw_pci.c optional pci
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powerpc/ofw/ofw_pcibus.c optional pci
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@ -21,6 +21,7 @@ GFB_NO_MODE_CHANGE opt_gfb.h
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MPC85XX opt_platform.h
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POWERMAC opt_platform.h
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PS3 opt_platform.h
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QORIQ_DPAA opt_platform.h
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MAMBO
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PSERIES
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PSIM
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@ -27,6 +27,7 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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@ -45,6 +46,7 @@ __FBSDID("$FreeBSD$");
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#include <powerpc/mpc85xx/mpc85xx.h>
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/*
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* MPC85xx system specific routines
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*/
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@ -70,70 +72,133 @@ int
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law_getmax(void)
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{
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uint32_t ver;
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int law_max;
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8555E || ver == SVR_MPC8555)
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return (8);
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if (ver == SVR_MPC8548E || ver == SVR_MPC8548 ||
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ver == SVR_MPC8533E || ver == SVR_MPC8533)
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return (10);
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switch (ver) {
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case SVR_MPC8555:
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case SVR_MPC8555E:
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law_max = 8;
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break;
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case SVR_MPC8533:
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case SVR_MPC8533E:
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case SVR_MPC8548:
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case SVR_MPC8548E:
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law_max = 10;
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break;
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case SVR_P5020:
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case SVR_P5020E:
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law_max = 32;
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break;
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default:
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law_max = 8;
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}
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return (12);
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return (law_max);
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}
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static inline void
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law_write(uint32_t n, uint64_t bar, uint32_t sr)
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{
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#if defined(QORIQ_DPAA)
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ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
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ccsr_write4(OCP85XX_LAWBARL(n), bar);
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#else
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ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
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#endif
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ccsr_write4(OCP85XX_LAWSR(n), sr);
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/*
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* The last write to LAWAR should be followed by a read
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* of LAWAR before any device try to use any of windows.
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* What more the read of LAWAR should be followed by isync
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* instruction.
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*/
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ccsr_read4(OCP85XX_LAWSR(n));
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isync();
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}
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static inline void
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law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
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{
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#if defined(QORIQ_DPAA)
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*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
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ccsr_read4(OCP85XX_LAWBARL(n));
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#else
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*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
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#endif
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*sr = ccsr_read4(OCP85XX_LAWSR(n));
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}
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static int
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law_find_free(void)
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{
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uint32_t i,sr;
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uint64_t bar;
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int law_max;
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law_max = law_getmax();
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/* Find free LAW */
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar, &sr);
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if ((sr & 0x80000000) == 0)
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break;
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}
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return (i);
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}
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#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
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#define _LAW_BAR(addr) (addr >> 12)
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int
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law_enable(int trgt, u_long addr, u_long size)
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law_enable(int trgt, uint64_t bar, uint32_t size)
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{
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uint32_t bar, sr;
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uint64_t bar_tmp;
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uint32_t sr, sr_tmp;
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int i, law_max;
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if (size == 0)
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return (0);
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law_max = law_getmax();
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bar = _LAW_BAR(addr);
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sr = _LAW_SR(trgt, size);
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/* Bail if already programmed. */
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for (i = 0; i < law_max; i++)
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if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
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bar == ccsr_read4(OCP85XX_LAWBAR(i)))
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar_tmp, &sr_tmp);
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if (sr == sr_tmp && bar == bar_tmp)
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return (0);
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}
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/* Find an unused access window. */
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for (i = 0; i < law_max; i++)
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if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
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break;
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i = law_find_free();
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if (i == law_max)
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return (ENOSPC);
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ccsr_write4(OCP85XX_LAWBAR(i), bar);
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ccsr_write4(OCP85XX_LAWSR(i), sr);
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law_write(i, bar, sr);
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return (0);
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}
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int
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law_disable(int trgt, u_long addr, u_long size)
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law_disable(int trgt, uint64_t bar, uint32_t size)
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{
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uint32_t bar, sr;
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uint64_t bar_tmp;
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uint32_t sr, sr_tmp;
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int i, law_max;
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law_max = law_getmax();
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bar = _LAW_BAR(addr);
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sr = _LAW_SR(trgt, size);
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/* Find and disable requested LAW. */
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for (i = 0; i < law_max; i++)
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if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
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bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
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ccsr_write4(OCP85XX_LAWBAR(i), 0);
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ccsr_write4(OCP85XX_LAWSR(i), 0);
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for (i = 0; i < law_max; i++) {
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law_read(i, &bar_tmp, &sr_tmp);
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if (sr == sr_tmp && bar == bar_tmp) {
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law_write(i, 0, 0);
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return (0);
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}
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}
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return (ENOENT);
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}
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@ -152,18 +217,22 @@ law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
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rv = 0;
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trgt = -1;
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switch (start) {
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case 0x0000:
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case 0x8000:
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trgt = 0;
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break;
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case 0x1000:
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case 0x9000:
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trgt = 1;
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break;
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case 0x2000:
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case 0xa000:
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if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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trgt = 3;
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else
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trgt = 2;
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break;
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case 0x3000:
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case 0xb000:
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if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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rv = EINVAL;
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@ -48,14 +48,35 @@ extern vm_offset_t ccsrbar_va;
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/*
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* Local access registers
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*/
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#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
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#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
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#if defined(QORIQ_DPAA)
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/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
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#define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n))
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#define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n))
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#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
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#else
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#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
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#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n))
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#endif
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#define OCP85XX_TGTIF_LBC 4
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#define OCP85XX_TGTIF_RAM_INTL 11
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#define OCP85XX_TGTIF_RIO 12
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#define OCP85XX_TGTIF_RAM1 15
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#define OCP85XX_TGTIF_RAM2 22
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/* Attribute register */
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#define OCP85XX_ENA_MASK 0x80000000
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#define OCP85XX_DIS_MASK 0x7fffffff
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#if defined(QORIQ_DPAA)
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#define OCP85XX_TGTIF_LBC 0x1f
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#define OCP85XX_TGTIF_RAM_INTL 0x14
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#define OCP85XX_TGTIF_RAM1 0x10
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#define OCP85XX_TGTIF_RAM2 0x11
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#define OCP85XX_TGTIF_BMAN 0x18
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#define OCP85XX_TGTIF_QMAN 0x3C
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#define OCP85XX_TRGT_SHIFT 20
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#else
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#define OCP85XX_TGTIF_LBC 0x04
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#define OCP85XX_TGTIF_RAM_INTL 0x0b
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#define OCP85XX_TGTIF_RIO 0x0c
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#define OCP85XX_TGTIF_RAM1 0x0f
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#define OCP85XX_TGTIF_RAM2 0x16
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#endif
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/*
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* L2 cache registers
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@ -81,8 +102,8 @@ extern vm_offset_t ccsrbar_va;
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*/
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uint32_t ccsr_read4(uintptr_t addr);
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void ccsr_write4(uintptr_t addr, uint32_t val);
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int law_enable(int trgt, u_long addr, u_long size);
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int law_disable(int trgt, u_long addr, u_long size);
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int law_enable(int trgt, uint64_t bar, uint32_t size);
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int law_disable(int trgt, uint64_t bar, uint32_t size);
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int law_getmax(void);
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int law_pci_target(struct resource *, int *, int *);
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