Implement resets for PCI buses and PCIe bridges.
For PCI device (i.e. child of a PCI bus), reset tries FLR if implemented and worked, and falls to power reset otherwise. For PCIe bus (child of a PCIe bridge or root port), reset disables PCIe link and then re-trains it, performing what is known as link-level reset. Reviewed by: imp (previous version), jhb (previous version) Sponsored by: Mellanox Technologies MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D19646
This commit is contained in:
parent
c53df6da4e
commit
5db2a4a812
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=345963
@ -356,25 +356,12 @@ ppt_is_mmio(struct vm *vm, vm_paddr_t gpa)
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static void
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ppt_pci_reset(device_t dev)
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{
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int ps;
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if (pcie_flr(dev,
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max(pcie_get_max_completion_timeout(dev) / 1000, 10),
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true))
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max(pcie_get_max_completion_timeout(dev) / 1000, 10), true))
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return;
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/*
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* If FLR fails, attempt a power-management reset by cycling
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* the device in/out of D3 state.
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* PCI spec says we can only go into D3 state from D0 state.
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* Transition from D[12] into D0 before going to D3 state.
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*/
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ps = pci_get_powerstate(dev);
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if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
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pci_set_powerstate(dev, PCI_POWERSTATE_D0);
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if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
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pci_set_powerstate(dev, PCI_POWERSTATE_D3);
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pci_set_powerstate(dev, ps);
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pci_power_reset(dev);
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}
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int
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@ -126,6 +126,10 @@ static int pci_remap_intr_method(device_t bus, device_t dev,
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u_int irq);
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static void pci_hint_device_unit(device_t acdev, device_t child,
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const char *name, int *unitp);
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static int pci_reset_post(device_t dev, device_t child);
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static int pci_reset_prepare(device_t dev, device_t child);
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static int pci_reset_child(device_t dev, device_t child,
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int flags);
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static int pci_get_id_method(device_t dev, device_t child,
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enum pci_id_type type, uintptr_t *rid);
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@ -150,6 +154,9 @@ static device_method_t pci_methods[] = {
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DEVMETHOD(bus_driver_added, pci_driver_added),
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DEVMETHOD(bus_setup_intr, pci_setup_intr),
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DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
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DEVMETHOD(bus_reset_prepare, pci_reset_prepare),
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DEVMETHOD(bus_reset_post, pci_reset_post),
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DEVMETHOD(bus_reset_child, pci_reset_child),
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DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
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DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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@ -6387,6 +6394,89 @@ pcie_flr(device_t dev, u_int max_delay, bool force)
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return (true);
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}
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int
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pci_power_reset(device_t dev)
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{
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int ps;
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ps = pci_get_powerstate(dev);
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if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
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pci_set_powerstate(dev, PCI_POWERSTATE_D0);
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pci_set_powerstate(dev, PCI_POWERSTATE_D3);
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pci_set_powerstate(dev, ps);
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return (0);
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}
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/*
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* Try link drop and retrain of the downstream port of upstream
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* switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must
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* cause Conventional Hot reset of the device in the slot.
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* Alternative, for PCIe, could be the secondary bus reset initiatied
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* on the upstream switch PCIR_BRIDGECTL_1, bit 6.
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*/
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int
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pcie_link_reset(device_t port, int pcie_location)
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{
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uint16_t v;
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v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2);
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v |= PCIEM_LINK_CTL_LINK_DIS;
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pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
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pause_sbt("pcier1", mstosbt(20), 0, 0);
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v &= ~PCIEM_LINK_CTL_LINK_DIS;
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v |= PCIEM_LINK_CTL_RETRAIN_LINK;
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pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
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pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */
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v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2);
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return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0);
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}
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static int
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pci_reset_post(device_t dev, device_t child)
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{
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if (dev == device_get_parent(child))
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pci_restore_state(child);
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return (0);
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}
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static int
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pci_reset_prepare(device_t dev, device_t child)
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{
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if (dev == device_get_parent(child))
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pci_save_state(child);
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return (0);
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}
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static int
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pci_reset_child(device_t dev, device_t child, int flags)
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{
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int error;
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if (dev == NULL || device_get_parent(child) != dev)
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return (0);
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if ((flags & DEVF_RESET_DETACH) != 0) {
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error = device_get_state(child) == DS_ATTACHED ?
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device_detach(child) : 0;
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} else {
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error = BUS_SUSPEND_CHILD(dev, child);
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}
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if (error == 0) {
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if (!pcie_flr(child, 1000, false)) {
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error = BUS_RESET_PREPARE(dev, child);
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if (error == 0)
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pci_power_reset(child);
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BUS_RESET_POST(dev, child);
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}
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if ((flags & DEVF_RESET_DETACH) != 0)
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device_probe_and_attach(child);
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else
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BUS_RESUME_CHILD(dev, child);
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}
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return (error);
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}
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const struct pci_device_table *
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pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt)
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{
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@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/pciio.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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@ -80,6 +81,7 @@ static void pcib_pcie_dll_timeout(void *arg);
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#endif
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static int pcib_request_feature_default(device_t pcib, device_t dev,
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enum pci_feature feature);
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static int pcib_reset_child(device_t dev, device_t child, int flags);
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static device_method_t pcib_methods[] = {
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/* Device interface */
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@ -106,6 +108,7 @@ static device_method_t pcib_methods[] = {
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_reset_child, pcib_reset_child),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
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@ -2909,3 +2912,31 @@ pcib_request_feature_default(device_t pcib, device_t dev,
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bus = device_get_parent(pcib);
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return (PCIB_REQUEST_FEATURE(device_get_parent(bus), dev, feature));
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}
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static int
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pcib_reset_child(device_t dev, device_t child, int flags)
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{
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struct pci_devinfo *pdinfo;
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int error;
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error = 0;
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if (dev == NULL || device_get_parent(child) != dev)
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goto out;
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error = ENXIO;
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if (device_get_devclass(child) != devclass_find("pci"))
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goto out;
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pdinfo = device_get_ivars(dev);
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if (pdinfo->cfg.pcie.pcie_location != 0 &&
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(pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT ||
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pdinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)) {
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error = bus_helper_reset_prepare(child, flags);
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if (error == 0) {
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error = pcie_link_reset(dev,
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pdinfo->cfg.pcie.pcie_location);
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/* XXXKIB call _post even if error != 0 ? */
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bus_helper_reset_post(child, flags);
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}
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}
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out:
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return (error);
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}
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@ -681,6 +681,7 @@ int pci_get_max_read_req(device_t dev);
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void pci_restore_state(device_t dev);
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void pci_save_state(device_t dev);
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int pci_set_max_read_req(device_t dev, int size);
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int pci_power_reset(device_t dev);
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uint32_t pcie_read_config(device_t dev, int reg, int width);
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void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
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uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
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@ -688,6 +689,7 @@ uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
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bool pcie_flr(device_t dev, u_int max_delay, bool force);
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int pcie_get_max_completion_timeout(device_t dev);
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bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
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int pcie_link_reset(device_t port, int pcie_location);
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void pci_print_faulted_dev(void);
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