Add support for the IMISS, DLMISS, and DSMISS traps required to run
FreeBSD on a G2 core. PR: powerpc/111296 Submitted by: Andrew Turner
This commit is contained in:
Nathan Whitehorn
parent
4a56bb2033
commit
5ebee02036
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=215107
@ -245,6 +245,9 @@ extern void *dsitrap, *dsisize;
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extern void *decrint, *decrsize;
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extern void *extint, *extsize;
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extern void *dblow, *dbsize;
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extern void *imisstrap, *imisssize;
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extern void *dlmisstrap, *dlmisssize;
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extern void *dsmisstrap, *dsmisssize;
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uintptr_t
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powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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@ -491,6 +494,12 @@ powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
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bcopy(generictrap, (void *)EXC_VEC, (size_t)&trapsize);
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bcopy(generictrap, (void *)EXC_VECAST_G4, (size_t)&trapsize);
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bcopy(generictrap, (void *)EXC_VECAST_G5, (size_t)&trapsize);
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#ifndef __powerpc64__
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/* G2-specific TLB miss helper handlers */
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bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
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bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
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bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize);
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#endif
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__syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
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/*
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@ -361,6 +361,207 @@ CNAME(alitrap):
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bla s_trap
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CNAME(alisize) = .-CNAME(alitrap)
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/*
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* G2 specific: instuction TLB miss.
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*/
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.globl CNAME(imisstrap),CNAME(imisssize)
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CNAME(imisstrap):
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mfspr %r2, SPR_HASH1 /* get first pointer */
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addi %r1, 0, 8 /* load 8 for counter */
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mfctr %r0 /* save counter */
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mfspr %r3, SPR_ICMP /* get first compare value */
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addi %r2, %r2, -8 /* pre dec the pointer */
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im0:
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mtctr %r1 /* load counter */
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im1:
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lwzu %r1, 8(%r2) /* get next pte */
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cmp 0, %r1, %r3 /* see if found pte */
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bdnzf 2, im1 /* dec count br if cmp ne and if
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* count not zero */
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bne instr_sec_hash /* if not found set up second hash
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* or exit */
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lwz %r1, +4(%r2) /* load tlb entry lower-word */
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andi. %r3, %r1, 8 /* check G bit */
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bne do_isi_prot /* if guarded, take an ISI */
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mtctr %r0 /* restore counter */
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mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
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mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtspr SPR_RPA, %r1 /* set the pte */
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ori %r1, %r1, 0x100 /* set reference bit */
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srwi %r1, %r1, 8 /* get byte 7 of pte */
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tlbli %r0 /* load the itlb */
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stb %r1, +6(%r2) /* update page table */
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rfi /* return to executing program */
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instr_sec_hash:
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andi. %r1, %r3, 0x0040 /* see if we have done second hash */
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bne do_isi /* if so, go to ISI interrupt */
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mfspr %r2, SPR_HASH2 /* get the second pointer */
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ori %r3, %r3, 0x0040 /* change the compare value */
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addi %r1, %r0, 8 /* load 8 for counter */
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addi %r2, %r2, -8 /* pre dec for update on load */
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b im0 /* try second hash */
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/* Create a faked ISI interrupt as the address was not found */
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do_isi_prot:
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mfspr %r3, SPR_SRR1 /* get srr1 */
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andi. %r2, %r3, 0xffff /* clean upper srr1 */
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addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot
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* violation */
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b isi1
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do_isi:
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mfspr %r3, SPR_SRR1 /* get srr1 */
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andi. %r2, %r3, 0xffff /* clean srr1 */
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addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte
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* not found */
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isi1:
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mtctr %r0 /* restore counter */
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mtspr SPR_SRR1, %r2 /* set srr1 */
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mfmsr %r0 /* get msr */
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xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtmsr %r0 /* flip back to the native gprs */
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ba EXC_ISI /* go to instr. access interrupt */
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CNAME(imisssize) = .-CNAME(imisstrap)
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/*
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* G2 specific: data load TLB miss.
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*/
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.globl CNAME(dlmisstrap),CNAME(dlmisssize)
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CNAME(dlmisstrap):
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mfspr %r2, SPR_HASH1 /* get first pointer */
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addi %r1, 0, 8 /* load 8 for counter */
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mfctr %r0 /* save counter */
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mfspr %r3, SPR_DCMP /* get first compare value */
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addi %r2, %r2, -8 /* pre dec the pointer */
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dm0:
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mtctr %r1 /* load counter */
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dm1:
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lwzu %r1, 8(%r2) /* get next pte */
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cmp 0, 0, %r1, %r3 /* see if found pte */
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bdnzf 2, dm1 /* dec count br if cmp ne and if
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* count not zero */
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bne data_sec_hash /* if not found set up second hash
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* or exit */
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lwz %r1, +4(%r2) /* load tlb entry lower-word */
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mtctr %r0 /* restore counter */
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mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
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mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtspr SPR_RPA, %r1 /* set the pte */
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ori %r1, %r1, 0x100 /* set reference bit */
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srwi %r1, %r1, 8 /* get byte 7 of pte */
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tlbld %r0 /* load the dtlb */
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stb %r1, +6(%r2) /* update page table */
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rfi /* return to executing program */
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data_sec_hash:
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andi. %r1, %r3, 0x0040 /* see if we have done second hash */
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bne do_dsi /* if so, go to DSI interrupt */
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mfspr %r2, SPR_HASH2 /* get the second pointer */
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ori %r3, %r3, 0x0040 /* change the compare value */
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addi %r1, 0, 8 /* load 8 for counter */
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addi %r2, %r2, -8 /* pre dec for update on load */
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b dm0 /* try second hash */
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CNAME(dlmisssize) = .-CNAME(dlmisstrap)
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/*
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* G2 specific: data store TLB miss.
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*/
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.globl CNAME(dsmisstrap),CNAME(dsmisssize)
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CNAME(dsmisstrap):
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mfspr %r2, SPR_HASH1 /* get first pointer */
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addi %r1, 0, 8 /* load 8 for counter */
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mfctr %r0 /* save counter */
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mfspr %r3, SPR_DCMP /* get first compare value */
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addi %r2, %r2, -8 /* pre dec the pointer */
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ds0:
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mtctr %r1 /* load counter */
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ds1:
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lwzu %r1, 8(%r2) /* get next pte */
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cmp 0, 0, %r1, %r3 /* see if found pte */
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bdnzf 2, ds1 /* dec count br if cmp ne and if
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* count not zero */
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bne data_store_sec_hash /* if not found set up second hash
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* or exit */
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lwz %r1, +4(%r2) /* load tlb entry lower-word */
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andi. %r3, %r1, 0x80 /* check the C-bit */
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beq data_store_chk_prot /* if (C==0)
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* go check protection modes */
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ds2:
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mtctr %r0 /* restore counter */
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mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
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mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtspr SPR_RPA, %r1 /* set the pte */
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tlbld %r0 /* load the dtlb */
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rfi /* return to executing program */
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data_store_sec_hash:
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andi. %r1, %r3, 0x0040 /* see if we have done second hash */
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bne do_dsi /* if so, go to DSI interrupt */
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mfspr %r2, SPR_HASH2 /* get the second pointer */
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ori %r3, %r3, 0x0040 /* change the compare value */
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addi %r1, 0, 8 /* load 8 for counter */
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addi %r2, %r2, -8 /* pre dec for update on load */
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b ds0 /* try second hash */
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/* Check the protection before setting PTE(c-bit) */
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data_store_chk_prot:
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rlwinm. %r3,%r1,30,0,1 /* test PP */
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bge- chk0 /* if (PP == 00 or PP == 01)
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* goto chk0: */
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andi. %r3, %r1, 1 /* test PP[0] */
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beq+ chk2 /* return if PP[0] == 0 */
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b do_dsi_prot /* else DSIp */
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chk0:
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mfspr %r3,SPR_SRR1 /* get old msr */
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andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */
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beq chk2 /* if (KEY==0) goto chk2: */
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b do_dsi_prot /* else do_dsi_prot */
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chk2:
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ori %r1, %r1, 0x180 /* set reference and change bit */
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sth %r1, 6(%r2) /* update page table */
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b ds2 /* and back we go */
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/* Create a faked DSI interrupt as the address was not found */
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do_dsi:
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mfspr %r3, SPR_SRR1 /* get srr1 */
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rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
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* load/store, zero rest */
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addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte
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* not found */
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b dsi1
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do_dsi_prot:
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mfspr %r3, SPR_SRR1 /* get srr1 */
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rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
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*load/store, zero rest */
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addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot
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* violation */
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dsi1:
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mtctr %r0 /* restore counter */
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andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */
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mtspr SPR_SRR1, %r2 /* set srr1 */
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mtspr SPR_DSISR, %r1 /* load the dsisr */
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mfspr %r1, SPR_DMISS /* get miss address */
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rlwinm. %r2,%r2,0,31,31 /* test LE bit */
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beq dsi2 /* if little endian then: */
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xor %r1, %r1, 0x07 /* de-mung the data address */
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dsi2:
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mtspr SPR_DAR, %r1 /* put in dar */
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mfmsr %r0 /* get msr */
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xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtmsr %r0 /* flip back to the native gprs */
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ba EXC_DSI /* branch to DSI interrupt */
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CNAME(dsmisssize) = .-CNAME(dsmisstrap)
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/*
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* Similar to the above for DSI
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* Has to handle BAT spills
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