From 60185d89654911ddfe8094b8701dc9e45ea0f11d Mon Sep 17 00:00:00 2001 From: Brandon Bergren Date: Mon, 6 Jul 2020 15:15:37 +0000 Subject: [PATCH] [PowerPC] XIVE dispatch tweaks * Only read the DPCPU pointer once per xive_dispatch call. * Optimize HE decoding for the common cases. Reported by: jhibbits (in irc) Reviewed by: jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25545 --- sys/powerpc/powernv/xive.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/sys/powerpc/powernv/xive.c b/sys/powerpc/powernv/xive.c index 9f5b80a15d10..349559e58d74 100644 --- a/sys/powerpc/powernv/xive.c +++ b/sys/powerpc/powernv/xive.c @@ -507,6 +507,7 @@ xive_dispatch(device_t dev, struct trapframe *tf) sc = device_get_softc(dev); + xive_cpud = DPCPU_PTR(xive_cpu_data); for (;;) { ack = xive_read_2(sc, XIVE_TM_SPC_ACK); cppr = (ack & 0xff); @@ -515,19 +516,17 @@ xive_dispatch(device_t dev, struct trapframe *tf) if (he == TM_QW3_NSR_HE_NONE) break; - switch (he) { - case TM_QW3_NSR_HE_NONE: - goto end; - case TM_QW3_NSR_HE_POOL: - case TM_QW3_NSR_HE_LSI: + + else if (__predict_false(he != TM_QW3_NSR_HE_PHYS)) { + /* + * We don't support TM_QW3_NSR_HE_POOL or + * TM_QW3_NSR_HE_LSI interrupts. + */ device_printf(dev, "Unexpected interrupt he type: %d\n", he); goto end; - case TM_QW3_NSR_HE_PHYS: - break; } - xive_cpud = DPCPU_PTR(xive_cpu_data); xive_write_1(sc, XIVE_TM_CPPR, cppr); for (;;) {