powerpc/booke: Simplify the MPC85XX PCIe root complex driver
Summary: Due to bugs in the enumeration code, fsl_pcib_init() was not configuring sub-bridges properly, so devices hanging off a separate bridge would not be found. Since the generic PCI code already supports probing child buses, just delete this code and initialize only the device itself, letting the generic code handle all the additional probing and initializing. This also deletes setup for some PCI peripherals found on some MPC85XX evaluation boards. The code can be resurrected if needed, but overly complicated this code in the first place. Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D22050
This commit is contained in:
Justin Hibbits
parent
1558015e3e
commit
6087140822
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354005
@ -40,5 +40,6 @@
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#define SYS_RES_DRQ 2 /* isa dma lines */
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#define SYS_RES_MEMORY 3 /* i/o memory */
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#define SYS_RES_IOPORT 4 /* i/o ports */
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#define PCI_RES_BUS 5 /* PCI bus numbers */
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#endif /* !_MACHINE_RESOURCE_H_ */
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@ -144,10 +144,6 @@ struct fsl_pcib_softc {
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int sc_busnr;
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int sc_pcie;
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uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
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/* Devices that need special attention. */
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int sc_devfn_tundra;
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int sc_devfn_via_ide;
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};
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struct fsl_pcib_err_dr {
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@ -187,7 +183,6 @@ static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
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static void fsl_pcib_err_init(device_t);
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static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
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uint64_t, uint64_t);
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static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
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static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
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uint64_t, uint64_t);
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@ -277,8 +272,8 @@ fsl_pcib_attach(device_t dev)
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{
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struct fsl_pcib_softc *sc;
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phandle_t node;
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uint32_t cfgreg;
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int error, maxslot, rid;
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uint32_t cfgreg, brctl;
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int error, rid;
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uint8_t ltssm, capptr;
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sc = device_get_softc(dev);
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@ -336,15 +331,17 @@ fsl_pcib_attach(device_t dev)
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PCIM_CMD_PORTEN;
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fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
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sc->sc_devfn_tundra = -1;
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sc->sc_devfn_via_ide = -1;
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/*
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* Scan bus using firmware configured, 0 based bus numbering.
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*/
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maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
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fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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/* Reset the bus. Needed for Radeon video cards. */
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brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
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PCIR_BRIDGECTL_1, 1);
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brctl |= PCIB_BCR_SECBUS_RESET;
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fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
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PCIR_BRIDGECTL_1, brctl, 1);
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DELAY(100000);
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brctl &= ~PCIB_BCR_SECBUS_RESET;
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fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
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PCIR_BRIDGECTL_1, brctl, 1);
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DELAY(100000);
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if (sc->sc_pcie) {
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ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
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@ -513,10 +510,7 @@ fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
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return (~0);
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devfn = DEVFN(bus, slot, func);
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if (devfn == sc->sc_devfn_tundra)
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return (~0);
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if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
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return (1);
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return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
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}
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@ -531,126 +525,6 @@ fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
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}
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static void
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fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
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int slot, int fn)
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{
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if (device == 0x0686) {
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fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
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} else if (device == 0x0571) {
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sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
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}
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}
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static int
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fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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{
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int secbus;
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int old_pribus, old_secbus, old_subbus;
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int new_pribus, new_secbus, new_subbus;
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int slot, func, maxfunc;
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uint16_t vendor, device;
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uint8_t brctl, command, hdrtype, subclass;
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secbus = bus;
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for (slot = 0; slot <= maxslot; slot++) {
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maxfunc = 0;
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for (func = 0; func <= maxfunc; func++) {
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hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (func == 0 && (hdrtype & PCIM_MFDEV))
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maxfunc = PCI_FUNCMAX;
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vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_VENDOR, 2);
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device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_DEVICE, 2);
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if (vendor == 0x1957 && device == 0x3fff) {
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sc->sc_devfn_tundra = DEVFN(bus, slot, func);
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continue;
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}
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command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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if (vendor == 0x1106)
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fsl_pcib_init_via(sc, device, bus, slot, func);
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/*
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* Handle PCI-PCI bridges
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*/
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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/* Allow all DEVTYPE 1 devices */
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if (hdrtype != PCIM_HDRTYPE_BRIDGE)
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continue;
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brctl = fsl_pcib_read_config(sc->sc_dev, bus, slot, func,
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PCIR_BRIDGECTL_1, 1);
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brctl |= PCIB_BCR_SECBUS_RESET;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_BRIDGECTL_1, brctl, 1);
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DELAY(100000);
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brctl &= ~PCIB_BCR_SECBUS_RESET;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_BRIDGECTL_1, brctl, 1);
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DELAY(100000);
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secbus++;
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/* Read currect bus register configuration */
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old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_PRIBUS_1, 1);
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old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SECBUS_1, 1);
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old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SUBBUS_1, 1);
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if (bootverbose)
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printf("PCI: reading firmware bus numbers for "
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"secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus);
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new_pribus = bus;
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new_secbus = secbus;
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secbus = fsl_pcib_init(sc, secbus,
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(subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
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new_subbus = secbus;
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if (bootverbose)
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printf("PCI: translate firmware bus numbers "
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"for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus,
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new_pribus, new_secbus, new_subbus);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PRIBUS_1, new_pribus, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_SECBUS_1, new_secbus, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_SUBBUS_1, new_subbus, 1);
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}
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}
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return (secbus);
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}
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static void
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fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
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uint64_t size, uint64_t pci_start)
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