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smc: Rename constants for control register from CTR* to CTRL*.

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This avoids a conflict with the recently-added CTR macro in
<sys/ktr.h>.
This commit is contained in:
John Baldwin 2022-04-12 17:11:28 -07:00
parent c0a42a0451
commit 613e07c07f
2 changed files with 12 additions and 12 deletions
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6
sys/dev/smc/if_smc.c
View File

@ -1175,9 +1175,9 @@ smc_reset(struct smc_softc *sc)
* Set up the control register.
*/
smc_select_bank(sc, 1);
ctr = smc_read_2(sc, CTR);
ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
smc_write_2(sc, CTR, ctr);
ctr = smc_read_2(sc, CTRL);
ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE;
smc_write_2(sc, CTRL, ctr);
/*
* Reset the MMU.

18
sys/dev/smc/if_smcreg.h
View File

@ -140,15 +140,15 @@
#define GPR 0xa
/* Bank 1, Offset 0xc: Control Register */
#define CTR 0xa
#define CTR_STORE 0x0001 /* Store registers to EEPROM */
#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */
#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
#define CTRL 0xa
#define CTRL_STORE 0x0001 /* Store registers to EEPROM */
#define CTRL_RELOAD 0x0002 /* Reload registers from EEPROM */
#define CTRL_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
#define CTRL_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
#define CTRL_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
#define CTRL_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
#define CTRL_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
#define CTRL_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
/* Bank 2, Offset 0x0: MMU Command Register */
#define MMUCR 0x0