smc: Rename constants for control register from CTR* to CTRL*.
This avoids a conflict with the recently-added CTR macro in <sys/ktr.h>.
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c0a42a0451
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@ -1175,9 +1175,9 @@ smc_reset(struct smc_softc *sc)
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* Set up the control register.
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*/
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smc_select_bank(sc, 1);
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ctr = smc_read_2(sc, CTR);
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ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
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smc_write_2(sc, CTR, ctr);
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ctr = smc_read_2(sc, CTRL);
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ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE;
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smc_write_2(sc, CTRL, ctr);
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/*
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* Reset the MMU.
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@ -140,15 +140,15 @@
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#define GPR 0xa
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/* Bank 1, Offset 0xc: Control Register */
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#define CTR 0xa
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#define CTR_STORE 0x0001 /* Store registers to EEPROM */
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#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */
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#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
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#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
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#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
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#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
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#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
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#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
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#define CTRL 0xa
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#define CTRL_STORE 0x0001 /* Store registers to EEPROM */
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#define CTRL_RELOAD 0x0002 /* Reload registers from EEPROM */
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#define CTRL_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
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#define CTRL_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
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#define CTRL_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
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#define CTRL_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
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#define CTRL_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
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#define CTRL_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
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/* Bank 2, Offset 0x0: MMU Command Register */
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#define MMUCR 0x0
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