Provide macros to extract the sub-fields of the CAP_LO and CAP_HI registers.
These macros make places where we extract these easier to read. The shift and mask stuff is also a bit tedious and error prone. Start with the CAP_LO and CAP_HI registers since their scope is somewhat constrained. This is style chagne only, no functional changes. Reviewed by: chuck Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D20979
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=350114
@ -69,6 +69,14 @@
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#define NVME_CAP_LO_REG_AMS_MASK (0x3)
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#define NVME_CAP_LO_REG_TO_SHIFT (24)
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#define NVME_CAP_LO_REG_TO_MASK (0xFF)
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#define NVME_CAP_LO_MQES(x) \
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(((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
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#define NVME_CAP_LO_CQR(x) \
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(((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
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#define NVME_CAP_LO_AMS(x) \
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(((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
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#define NVME_CAP_LO_TO(x) \
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(((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
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#define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
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#define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
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@ -78,6 +86,14 @@
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#define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
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#define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
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#define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
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#define NVME_CAP_HI_DSTRD(x) \
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(((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
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#define NVME_CAP_HI_CSS_NVM(x) \
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(((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
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#define NVME_CAP_HI_MPSMIN(x) \
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(((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
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#define NVME_CAP_HI_MPSMAX(x) \
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(((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
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#define NVME_CC_REG_EN_SHIFT (0)
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#define NVME_CC_REG_EN_MASK (0x1)
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@ -137,7 +137,7 @@ nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr)
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* the MQES field in the capabilities register.
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*/
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cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
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mqes = (cap_lo >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK;
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mqes = NVME_CAP_LO_MQES(cap_lo);
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num_entries = min(num_entries, mqes + 1);
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num_trackers = NVME_IO_TRACKERS;
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@ -1246,16 +1246,16 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
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* other than zero, but this driver is not set up to handle that.
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*/
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cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
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dstrd = (cap_hi >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK;
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dstrd = NVME_CAP_HI_DSTRD(cap_hi);
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if (dstrd != 0)
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return (ENXIO);
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mpsmin = (cap_hi >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK;
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mpsmin = NVME_CAP_HI_MPSMIN(cap_hi);
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ctrlr->min_page_size = 1 << (12 + mpsmin);
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/* Get ready timeout value from controller, in units of 500ms. */
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cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
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to = ((cap_lo >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) + 1;
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to = NVME_CAP_LO_TO(cap_lo) + 1;
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ctrlr->ready_timeout_in_ms = to * 500;
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timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD;
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