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Remove redundant cache initialization in JZ4780 SMP startup code

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This was done out of pure paranoia when hunting for bugs in cache
and is not really required.
This commit is contained in:
Alexander Kabaev 2017-01-06 00:07:36 +00:00
parent 284829482e
commit 631f432b0d
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=311463
1 changed files with 5 additions and 22 deletions
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27
sys/mips/ingenic/jz4780_mpboot.S
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@ -27,36 +27,19 @@
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include <machine/cache_r4k.h>
#include "assym.s"
#define CACHE_SIZE (32 * 1024)
#define CACHE_LINESIZE 32
.text
.set noat
.set noreorder
.section .text.mpentry_jz4780
.balign 0x10000
/*
* JZ4870 has stricter alignment requirement for
* CPU entry point. Enforce it in CPU-specific
* file.
*/
GLOBAL(jz4780_mpentry)
/* Initialize caches */
li t0, MIPS_KSEG0_START
ori t1, t0, CACHE_SIZE
mtc0 zero, MIPS_COP_0_TAG_LO
COP0_SYNC
1: cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_I, 0(t0)
cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0)
bne t0, t1, 1b
addiu t0, t0, CACHE_LINESIZE
/* Set TLB page mask */
mtc0 zero, MIPS_COP_0_TLB_PG_MASK
COP0_SYNC
j mpentry
nop