Add support for frobbing Intel StrataFlash Protection Registers:
o add CFI_SUPPORT_STRATAFLASH compile option to enable support o add new ioctls to get/set the factory and user/oem segments of the PR and to get/set Protection Lock Register that fuses the user segment o add #defines for bits in the status register o update cfi_wait_ready to take an offset so it can be used to wait for PR write completion and replace constants w/ symbolic names Note: writing the user segment isn't correct; committing now to get review. Sponsored by: Carlson Wireless Reviewed by: imp, Chris Anderson
This commit is contained in:
Sam Leffler
parent
b8bd4a9751
commit
63425a7f25
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=188156
@ -804,3 +804,7 @@ TDMA_TXRATE_11A_DEFAULT opt_tdma.h
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# Virtualize the network stack
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VIMAGE opt_global.h
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VIMAGE_GLOBALS opt_global.h
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# Common Flash Interface (CFI) options
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CFI_SUPPORT_STRATAFLASH opt_cfi.h
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CFI_ARMEDANDDANGEROUS opt_cfi.h
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@ -30,6 +30,8 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cfi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -70,7 +72,6 @@ cfi_read(struct cfi_softc *sc, u_int ofs)
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val = ~0;
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break;
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}
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return (val);
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}
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@ -300,10 +301,10 @@ cfi_detach(device_t dev)
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}
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static int
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cfi_wait_ready(struct cfi_softc *sc, u_int timeout)
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cfi_wait_ready(struct cfi_softc *sc, u_int ofs, u_int timeout)
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{
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int done, error;
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uint32_t st0, st;
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uint32_t st0 = 0, st = 0;
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done = 0;
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error = 0;
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@ -315,21 +316,27 @@ cfi_wait_ready(struct cfi_softc *sc, u_int timeout)
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switch (sc->sc_cmdset) {
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case CFI_VEND_INTEL_ECS:
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case CFI_VEND_INTEL_SCS:
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st = cfi_read(sc, sc->sc_wrofs);
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done = (st & 0x80);
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st = cfi_read(sc, ofs);
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done = (st & CFI_INTEL_STATUS_WSMS);
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if (done) {
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if (st & 0x02)
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/* NB: bit 0 is reserved */
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st &= ~(CFI_INTEL_XSTATUS_RSVD |
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CFI_INTEL_STATUS_WSMS |
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CFI_INTEL_STATUS_RSVD);
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if (st & CFI_INTEL_STATUS_DPS)
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error = EPERM;
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else if (st & 0x10)
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else if (st & CFI_INTEL_STATUS_PSLBS)
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error = EIO;
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else if (st & 0x20)
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else if (st & CFI_INTEL_STATUS_ECLBS)
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error = ENXIO;
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else if (st)
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error = EACCES;
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}
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break;
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case CFI_VEND_AMD_SCS:
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case CFI_VEND_AMD_ECS:
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st0 = cfi_read(sc, sc->sc_wrofs);
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st = cfi_read(sc, sc->sc_wrofs);
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st0 = cfi_read(sc, ofs);
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st = cfi_read(sc, ofs);
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done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
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break;
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}
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@ -337,7 +344,7 @@ cfi_wait_ready(struct cfi_softc *sc, u_int timeout)
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if (!done && !error)
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error = ETIMEDOUT;
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if (error)
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printf("\nerror=%d\n", error);
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printf("\nerror=%d (st 0x%x st0 0x%x)\n", error, st, st0);
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return (error);
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}
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@ -369,7 +376,7 @@ cfi_write_block(struct cfi_softc *sc)
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/* Better safe than sorry... */
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return (ENODEV);
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}
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error = cfi_wait_ready(sc, sc->sc_erase_timeout);
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error = cfi_wait_ready(sc, sc->sc_wrofs, sc->sc_erase_timeout);
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if (error)
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goto out;
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@ -411,7 +418,7 @@ cfi_write_block(struct cfi_softc *sc)
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intr_restore(intr);
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error = cfi_wait_ready(sc, sc->sc_write_timeout);
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error = cfi_wait_ready(sc, sc->sc_wrofs, sc->sc_write_timeout);
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if (error)
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goto out;
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}
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@ -422,3 +429,145 @@ cfi_write_block(struct cfi_softc *sc)
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return (error);
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}
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#ifdef CFI_SUPPORT_STRATAFLASH
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/*
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* Intel StrataFlash Protection Register Support.
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*
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* The memory includes a 128-bit Protection Register that can be
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* used for security. There are two 64-bit segments; one is programmed
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* at the factory with a unique 64-bit number which is immutable.
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* The other segment is left blank for User (OEM) programming.
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* Once the User/OEM segment is programmed it can be locked
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* to prevent future programming by writing bit 0 of the Protection
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* Lock Register (PLR). The PLR can written only once.
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*/
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static uint16_t
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cfi_get16(struct cfi_softc *sc, int off)
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{
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uint16_t v = bus_space_read_2(sc->sc_tag, sc->sc_handle, off<<1);
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return v;
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}
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static void
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cfi_put16(struct cfi_softc *sc, int off, uint16_t v)
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{
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bus_space_write_2(sc->sc_tag, sc->sc_handle, off<<1, v);
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}
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/*
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* Read the factory-defined 64-bit segment of the PR.
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*/
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int
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cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *id)
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{
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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cfi_write(sc, 0, CFI_INTEL_READ_ID);
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*id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(0)))<<48 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(1)))<<32 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(2)))<<16 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(3)));
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return 0;
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}
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/*
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* Read the User/OEM 64-bit segment of the PR.
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*/
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int
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cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
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{
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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cfi_write(sc, 0, CFI_INTEL_READ_ID);
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*id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(4)))<<48 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(5)))<<32 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(6)))<<16 |
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((uint64_t)cfi_get16(sc, CFI_INTEL_PR(7)));
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return 0;
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}
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/*
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* Write the User/OEM 64-bit segment of the PR.
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*/
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int
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cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
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{
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register_t intr;
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int i, error;
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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for (i = 7; i >= 4; i--, id >>= 16) {
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intr = intr_disable();
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cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
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cfi_put16(sc, CFI_INTEL_PR(i), id&0xffff);
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intr_restore(intr);
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error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS,
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sc->sc_write_timeout);
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if (error)
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break;
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}
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return error;
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}
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/*
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* Read the contents of the Protection Lock Register.
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*/
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int
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cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *plr)
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{
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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cfi_write(sc, 0, CFI_INTEL_READ_ID);
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*plr = cfi_get16(sc, CFI_INTEL_PLR);
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return 0;
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}
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/*
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* Write the Protection Lock Register to lock down the
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* user-settable segment of the Protection Register.
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* NOTE: this operation is not reversible.
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*/
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int
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cfi_intel_set_plr(struct cfi_softc *sc)
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{
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#ifdef CFI_ARMEDANDDANGEROUS
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register_t intr;
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#endif
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int error;
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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#ifdef CFI_ARMEDANDDANGEROUS
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/* worthy of console msg */
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device_printf(sc->sc_dev, "set PLR\n");
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intr = intr_disable();
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cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
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cfi_put16(sc, CFI_INTEL_PLR, 0xFFFD);
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intr_restore(intr);
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error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, sc->sc_write_timeout);
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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#else
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device_printf(sc->sc_dev, "%s: PLR not set, "
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"CFI_ARMEDANDDANGEROUS not configured\n", __func__);
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error = ENXIO;
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#endif
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return error;
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}
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#endif /* CFI_SUPPORT_STRATAFLASH */
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@ -30,6 +30,8 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cfi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -255,14 +257,13 @@ cfi_devioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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sc = dev->si_drv1;
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error = 0;
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switch(cmd) {
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switch (cmd) {
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case CFIOCQRY:
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if (sc->sc_writing) {
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error = cfi_block_finish(sc);
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if (error)
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break;
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}
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rq = (struct cfiocqry *)data;
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if (rq->offset >= sc->sc_size / sc->sc_width)
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return (ESPIPE);
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@ -274,6 +275,23 @@ cfi_devioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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error = copyout(&val, rq->buffer++, 1);
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}
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break;
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#ifdef CFI_SUPPORT_STRATAFLASH
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case CFIOCGFACTORYPR:
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error = cfi_intel_get_factory_pr(sc, (uint64_t *)data);
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break;
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case CFIOCGOEMPR:
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error = cfi_intel_get_oem_pr(sc, (uint64_t *)data);
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break;
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case CFIOCSOEMPR:
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error = cfi_intel_set_oem_pr(sc, *(uint64_t *)data);
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break;
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case CFIOCGPLR:
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error = cfi_intel_get_plr(sc, (uint32_t *)data);
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break;
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case CFIOCSPLR:
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error = cfi_intel_set_plr(sc);
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break;
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#endif /* CFI_SUPPORT_STRATAFLASH */
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default:
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error = ENOIOCTL;
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break;
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@ -104,6 +104,28 @@ struct cfi_qry {
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#define CFI_BCS_CONFIRM 0xd0
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#define CFI_BCS_READ_ARRAY 0xff
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/* Intel commands. */
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#define CFI_INTEL_READ_ID 0x90 /* Read Identifier */
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#define CFI_INTEL_PP_SETUP 0xc0 /* Protection Program Setup */
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/* NB: these are addresses for 16-bit accesses */
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#define CFI_INTEL_PLR 0x80 /* Protection Lock Register */
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#define CFI_INTEL_PR(n) (0x81+(n)) /* Protection Register */
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/* Status register definitions */
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#define CFI_INTEL_STATUS_WSMS 0x0080 /* Write Machine Status */
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#define CFI_INTEL_STATUS_ESS 0x0040 /* Erase Suspend Status */
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#define CFI_INTEL_STATUS_ECLBS 0x0020 /* Erase and Clear Lock-Bit Status */
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#define CFI_INTEL_STATUS_PSLBS 0x0010 /* Program and Set Lock-Bit Status */
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#define CFI_INTEL_STATUS_VPENS 0x0008 /* Programming Voltage Status */
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#define CFI_INTEL_STATUS_PSS 0x0004 /* Program Suspend Status */
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#define CFI_INTEL_STATUS_DPS 0x0002 /* Device Protect Status */
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#define CFI_INTEL_STATUS_RSVD 0x0001 /* reserved */
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/* eXtended Status register definitions */
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#define CFI_INTEL_XSTATUS_WBS 0x8000 /* Write Buffer Status */
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#define CFI_INTEL_XSTATUS_RSVD 0x7f00 /* reserved */
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/* AMD commands. */
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#define CFI_AMD_BLOCK_ERASE 0x30
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#define CFI_AMD_UNLOCK_ACK 0x55
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@ -74,4 +74,11 @@ uint32_t cfi_read(struct cfi_softc *, u_int);
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uint8_t cfi_read_qry(struct cfi_softc *, u_int);
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int cfi_write_block(struct cfi_softc *);
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#ifdef CFI_SUPPORT_STRATAFLASH
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int cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *);
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int cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *);
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int cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t);
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int cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *);
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int cfi_intel_set_plr(struct cfi_softc *sc);
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#endif /* CFI_SUPPORT_STRATAFLASH */
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#endif /* _DEV_CFI_VAR_H_ */
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@ -44,4 +44,10 @@ struct cfiocqry {
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#define CFIOCQRY _IOWR('q', 0, struct cfiocqry)
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/* Intel StrataFlash Protection Register support */
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#define CFIOCGFACTORYPR _IOR('q', 1, uint64_t) /* get factory protection reg */
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#define CFIOCGOEMPR _IOR('q', 2, uint64_t) /* get oem protection reg */
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#define CFIOCSOEMPR _IOW('q', 3, uint64_t) /* set oem protection reg */
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#define CFIOCGPLR _IOR('q', 4, uint32_t) /* get protection lock reg */
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#define CFIOCSPLR _IO('q', 5) /* set protection log reg */
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#endif /* _SYS_CFICTL_H_ */
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