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Adjust DMA alignment for USB stack.

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It should be at least as large as the maximum value of caheline size
for currently known CPUs.

MFC after:	2 weeks
This commit is contained in:
Michal Meloun 2020-09-20 17:28:24 +00:00
parent 1c62664f24
commit 6507a8fecb
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=365929
1 changed files with 1 additions and 0 deletions
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sys/arm64/conf/GENERIC
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@ -218,6 +218,7 @@ device uart_snps
device pl011
# USB support
options USB_HOST_ALIGN=64 # Align usb buffers to cache line size.
device aw_usbphy # Allwinner USB PHY
device rk_usb2phy # Rockchip USB2PHY
device rk_typec_phy # Rockchip TypeC PHY