[arswitch] add initial functionality for AR8327 ATU management.
* Add the bulk of the ATU table read function * Correct how the ATU function and WAIT bits work TODO: * more testing, figure out how the multi-vlan table stuff works and push that up to userspace
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46b59ac82b
commit
65d59686e1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=328823
@ -1100,16 +1100,78 @@ ar8327_atu_flush_port(struct arswitch_softc *sc, int port)
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return (ret);
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}
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/*
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* Fetch a single entry from the ATU.
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*/
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static int
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ar8327_atu_fetch_table(struct arswitch_softc *sc, etherswitch_atu_entry_t *e,
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int atu_fetch_op)
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{
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uint32_t ret0, ret1, ret2, val;
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/* XXX TODO */
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return (ENXIO);
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ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
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switch (atu_fetch_op) {
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case 0:
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/* Initialise things for the first fetch */
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DPRINTF(sc, ARSWITCH_DBG_ATU, "%s: initializing\n", __func__);
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(void) ar8327_atu_wait_ready(sc);
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arswitch_writereg(sc->sc_dev,
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AR8327_REG_ATU_FUNC, AR8327_ATU_FUNC_OP_GET_NEXT);
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arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA0, 0);
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arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA1, 0);
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arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA2, 0);
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return (0);
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case 1:
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DPRINTF(sc, ARSWITCH_DBG_ATU, "%s: reading next\n", __func__);
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/*
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* Attempt to read the next address entry; don't modify what
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* is there in these registers as its used for the next fetch
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*/
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(void) ar8327_atu_wait_ready(sc);
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/* Begin the next read event; not modifying anything */
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val = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_FUNC);
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val |= AR8327_ATU_FUNC_BUSY;
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arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_FUNC, val);
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/* Wait for it to complete */
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(void) ar8327_atu_wait_ready(sc);
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/* Fetch the ethernet address and ATU status */
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ret0 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA0);
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ret1 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA1);
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ret2 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA2);
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/* If the status is zero, then we're done */
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if (MS(ret2, AR8327_ATU_FUNC_DATA2_STATUS) == 0)
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return (-1);
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/* MAC address */
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e->es_macaddr[5] = MS(ret1, AR8327_ATU_DATA1_MAC_ADDR5);
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e->es_macaddr[4] = MS(ret1, AR8327_ATU_DATA1_MAC_ADDR4);
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e->es_macaddr[3] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR3);
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e->es_macaddr[2] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR2);
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e->es_macaddr[1] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR1);
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e->es_macaddr[0] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR0);
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/* Bitmask of ports this entry is for */
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e->es_portmask = MS(ret1, AR8327_ATU_DATA1_DEST_PORT);
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/* TODO: other flags that are interesting */
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DPRINTF(sc, ARSWITCH_DBG_ATU, "%s: MAC %6D portmask 0x%08x\n",
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__func__,
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e->es_macaddr, ":", e->es_portmask);
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return (0);
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default:
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return (-1);
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}
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return (-1);
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}
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static int
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ar8327_flush_dot1q_vlan(struct arswitch_softc *sc)
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{
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@ -485,11 +485,42 @@
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#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
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#define AR8327_REG_ATU_DATA0 0x600
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#define AR8327_ATU_DATA0_MAC_ADDR3 BITS(0, 8)
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#define AR8327_ATU_DATA0_MAC_ADDR3_S 0
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#define AR8327_ATU_DATA0_MAC_ADDR2 BITS(8, 8)
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#define AR8327_ATU_DATA0_MAC_ADDR2_S 8
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#define AR8327_ATU_DATA0_MAC_ADDR1 BITS(16, 8)
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#define AR8327_ATU_DATA0_MAC_ADDR1_S 16
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#define AR8327_ATU_DATA0_MAC_ADDR0 BITS(24, 8)
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#define AR8327_ATU_DATA0_MAC_ADDR0_S 24
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#define AR8327_REG_ATU_DATA1 0x604
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#define AR8327_ATU_DATA1_MAC_ADDR4 BITS(0, 8)
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#define AR8327_ATU_DATA1_MAC_ADDR4_S 0
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#define AR8327_ATU_DATA1_MAC_ADDR5 BITS(8, 8)
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#define AR8327_ATU_DATA1_MAC_ADDR5_S 0
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#define AR8327_ATU_DATA1_DEST_PORT BITS(16, 7)
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#define AR8327_ATU_DATA1_DEST_PORT_S 16
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#define AR8327_ATU_DATA1_CROSS_PORT_STATE_EN BIT(23)
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#define AR8327_ATU_DATA1_PRI BITS(24, 3)
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#define AR8327_ATU_DATA1_SVL_ENTRY BIT(27)
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#define AR8327_ATU_DATA1_PRI_OVER_EN BIT(28)
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#define AR8327_ATU_DATA1_MIRROR_EN BIT(29)
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#define AR8327_ATU_DATA1_SA_DROP_EN BIT(30)
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#define AR8327_ATU_DATA1_HASH_HIGH_ADDR BIT(31)
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#define AR8327_REG_ATU_DATA2 0x608
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#define AR8327_ATU_FUNC_DATA2_STATUS BITS(0, 4)
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#define AR8327_ATU_FUNC_DATA2_STATUS_S 0
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#define AR8327_ATU_FUNC_DATA2_VLAN_LEAKY_EN BIT(4)
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#define AR8327_ATU_FUNC_DATA2_REDIRECT_TO_CPU BIT(5)
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#define AR8327_ATU_FUNC_DATA2_COPY_TO_CPU BIT(6)
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#define AR8327_ATU_FUNC_DATA2_SHORT_LOOP BIT(7)
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#define AR8327_ATU_FUNC_DATA2_ATU_VID BITS(8, 12)
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#define AR8327_ATU_FUNC_DATA2_ATU_VID_S 8
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#define AR8327_REG_ATU_FUNC 0x60c
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#define AR8327_ATU_FUNC_OP BITS(0, 3)
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#define AR8327_ATU_FUNC_OP BITS(0, 4)
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#define AR8327_ATU_FUNC_OP_NOOP 0x0
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#define AR8327_ATU_FUNC_OP_FLUSH 0x1
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#define AR8327_ATU_FUNC_OP_LOAD 0x2
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@ -499,9 +530,19 @@
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#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
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#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
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#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
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#define AR8327_ATU_FUNC_BUSY BIT(3)
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#define AR8327_ATU_FUNC_FLUSH_STATIC_EN BIT(4)
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#define AR8327_ATU_FUNC_ENTRY_TYPE BIT(5)
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#define AR8327_ATU_FUNC_PORT_NUM BITS(8, 4)
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#define AR8327_ATU_FUNC_PORT_NUM_S 8
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#define AR8327_ATU_FUNC_FULL_VIOLATION BIT(12)
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#define AR8327_ATU_FUNC_MULTI_EN BIT(13) /* for GET_NEXT */
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#define AR8327_ATU_FUNC_PORT_EN BIT(14) /* for GET_NEXT */
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#define AR8327_ATU_FUNC_VID_EN BIT(15) /* for GET_NEXT */
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#define AR8327_ATU_FUNC_ATU_INDEX BITS(16, 5)
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#define AR8327_ATU_FUNC_ATU_INDEX_S 16
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#define AR8327_ATU_FUNC_TRUNK_PORT_NUM BITS(22, 3) /* for CHANGE_TRUNK */
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#define AR8327_ATU_FUNC_TRUNK_PORT_NUM_S 22
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#define AR8327_ATU_FUNC_BUSY BIT(31)
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#define AR8327_REG_VTU_FUNC0 0x0610
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#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
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