Disable setting the MII port speed.
This seems to break at least my test board here (AR71xx + AR8316 switch PHY). Since I do have a whole sleuth of "normal" PHY boards (with an AR71xx on a normal PHY port), I'll do some further testing with those to determine whether this is a general issue, or whether it's limited to the behaviour of the "fake" dedicated PHY port mode on these atheros switches.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=234992
@ -932,7 +932,19 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
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ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
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/* set MII registers */
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/*
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* This was introduced to match what the Linux ag71xx ethernet
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* driver does. For the AR71xx case, it does set the port
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* MII speed. However, if this is done, non-gigabit speeds
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* are not at all reliable when speaking via RGMII through
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* 'bridge' PHY port that's pretending to be a local PHY.
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*
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* Until that gets root caused, and until an AR71xx + normal
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* PHY board is tested, leave this disabled.
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*/
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#if 0
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ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
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#endif
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}
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