Use aperture base address from north bridge. Some BIOS does not encode
misc. control registers correctly and it is inconsistent with north bridge. In fact, there are too many broken BIOS implementations out there and we cannot fix every possible combination but at least it is consistent with what we advertise with ioctl(2).
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commit
668e25a26c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=161518
@ -182,14 +182,9 @@ agp_amd64_attach(device_t dev)
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sc->n_mctrl = n;
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if (bootverbose) {
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if (bootverbose)
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device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
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sc->n_mctrl);
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for (i = 0; i < sc->n_mctrl; i++)
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device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
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pci_cfgregread(0, sc->mctrl[i], 3,
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AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
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}
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if ((error = agp_generic_attach(dev)))
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return error;
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@ -380,11 +375,11 @@ agp_amd64_apbase_fixup(device_t dev)
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uint32_t apbase;
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int i;
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apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
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sc->apbase = rman_get_start(sc->agp.as_aperture);
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apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
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apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
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sc->apbase = apbase << 25;
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pci_cfgregwrite(0, sc->mctrl[i], 3,
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AGP_AMD64_APBASE, apbase, 4);
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}
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static void
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@ -182,14 +182,9 @@ agp_amd64_attach(device_t dev)
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sc->n_mctrl = n;
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if (bootverbose) {
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if (bootverbose)
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device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
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sc->n_mctrl);
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for (i = 0; i < sc->n_mctrl; i++)
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device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
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pci_cfgregread(0, sc->mctrl[i], 3,
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AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
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}
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if ((error = agp_generic_attach(dev)))
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return error;
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@ -380,11 +375,11 @@ agp_amd64_apbase_fixup(device_t dev)
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uint32_t apbase;
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int i;
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apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
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sc->apbase = rman_get_start(sc->agp.as_aperture);
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apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
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for (i = 0; i < sc->n_mctrl; i++)
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pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
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apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
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sc->apbase = apbase << 25;
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pci_cfgregwrite(0, sc->mctrl[i], 3,
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AGP_AMD64_APBASE, apbase, 4);
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}
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static void
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