- Remove the old sparc64 OFW PCI code (as opposed to the former
"options OFW_NEWPCI"). This is a bit overdue, the new sparc64 OFW PCI code which is meant to replace the old one is in place for 10 months and enabled by default in GENERIC for 8 months. FreeBSD 5.2 and 5.2.1 also shipped with the new code enabled by default. - Some minor clean-up, e.g. remove functions that encapsulated the #ifdefs for OFW_NEWPCI, remove unused resp. no longer required includes, etc. Approved by: tmm, no objections on freebsd-sparc64
This commit is contained in:
Marius Strobl
parent
60f798c1c8
commit
66a79ac95d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=129051
@ -54,9 +54,9 @@ sparc64/isa/ofw_isa.c optional ebus
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sparc64/isa/ofw_isa.c optional isa
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sparc64/pci/apb.c optional pci
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sparc64/pci/ofw_pci.c optional pci
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sparc64/pci/ofw_pcib.c optional pci ofw_newpci
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sparc64/pci/ofw_pcib_subr.c optional pci ofw_newpci
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sparc64/pci/ofw_pcibus.c optional pci ofw_newpci
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sparc64/pci/ofw_pcib.c optional pci
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sparc64/pci/ofw_pcib_subr.c optional pci
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sparc64/pci/ofw_pcibus.c optional pci
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sparc64/pci/ofw_pci_if.m optional pci
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sparc64/pci/psycho.c optional pci
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sparc64/sbus/sbus.c optional sbus
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@ -9,7 +9,6 @@ GFB_NO_MODE_CHANGE opt_gfb.h
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PSYCHO_DEBUG opt_psycho.h
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DEBUGGER_ON_POWERFAIL opt_psycho.h
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OFW_PCI_DEBUG opt_ofw_pci.h
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OFW_NEWPCI opt_ofw_pci.h
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# Debug IOMMU inserts/removes using diagnostic accesses. Very loud.
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IOMMU_DIAG opt_iommu.h
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PMAP_STATS opt_pmap.h
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@ -76,14 +76,6 @@ device sbus
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device central
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device fhc
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# New OpenFirmware PCI framework. This fixes a number of interrupt-
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# routing problems and changes the device enumeration to be hopefully
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# closer to Solaris. Be aware that, because of the latter, enabling or
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# disabling this option may require reconfiguration, and can even
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# cause the machine to not boot without manual intervention before the
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# fstab is adjusted.
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options OFW_NEWPCI
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# Floppy drives
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#device fdc
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@ -31,14 +31,6 @@ device sbus
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device central
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device fhc
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# New OpenFirmware PCI framework. This fixes a number of interrupt-
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# routing problems and changes the device enumeration to be hopefully
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# closer to Solaris. Be aware that, because of the latter, enabling or
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# disabling this option may require reconfiguration, and can even
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# cause the machine to not boot without manual intervention before the
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# fstab is adjusted.
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#options OFW_NEWPCI
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#####################################################################
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# HARDWARE DEVICE CONFIGURATION
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@ -46,8 +46,6 @@
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* there are machines with both ISA and EBus.
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*/
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -59,7 +57,6 @@
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#include <sys/rman.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <machine/ofw_bus.h>
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#include <machine/resource.h>
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@ -99,9 +96,7 @@ struct ebus_softc {
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int sc_nrange;
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int sc_nimap;
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#ifdef OFW_NEWPCI
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struct ofw_bus_iinfo sc_iinfo;
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#endif
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};
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static device_probe_t ebus_probe;
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@ -151,25 +146,13 @@ static devclass_t ebus_devclass;
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DRIVER_MODULE(ebus, pci, ebus_driver, ebus_devclass, 0, 0);
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static phandle_t
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ebus_get_busnode(device_t dev)
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{
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#ifdef OFW_NEWPCI
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return (ofw_pci_get_node(dev));
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#else
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return (ofw_pci_find_node(pci_get_bus(dev), pci_get_slot(dev),
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pci_get_function(dev)));
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#endif
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}
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static int
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ebus_probe(device_t dev)
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{
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char name[10];
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phandle_t node;
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if ((node = ebus_get_busnode(dev)) == 0)
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if ((node = ofw_pci_get_node(dev)) == 0)
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return (ENXIO);
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OF_getprop(node, "name", &name, sizeof(name));
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@ -200,7 +183,7 @@ ebus_attach(device_t dev)
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int i, rnum, rid;
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sc = device_get_softc(dev);
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sc->sc_node = node = ebus_get_busnode(dev);
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sc->sc_node = node = ofw_pci_get_node(dev);
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sc->sc_nrange = OF_getprop_alloc(node, "ranges",
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sizeof(*sc->sc_range), (void **)&sc->sc_range);
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@ -239,9 +222,7 @@ ebus_attach(device_t dev)
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}
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}
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#ifdef OFW_NEWPCI
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ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_isa_intr_t));
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#endif
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/*
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* Now attach our children.
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@ -490,17 +471,10 @@ ebus_setup_dinfo(device_t dev, struct ebus_softc *sc, phandle_t node,
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nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs),
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(void **)&intrs);
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for (i = 0; i < nintr; i++) {
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#ifdef OFW_NEWPCI
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rintr = ofw_isa_route_intr(dev, node, &sc->sc_iinfo, intrs[i]);
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if (rintr == PCI_INVALID_IRQ) {
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#else
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rintr = ofw_bus_route_intr(node, intrs[i], ofw_pci_orb_callback,
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dev);
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if (rintr == ORIR_NOTFOUND) {
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#endif
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if (rintr == PCI_INVALID_IRQ)
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panic("ebus_setup_dinfo: could not map ebus "
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"interrupt %d", intrs[i]);
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}
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resource_list_add(&edi->edi_rl, SYS_RES_IRQ, i,
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rintr, rintr, 1);
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}
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@ -37,8 +37,6 @@
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*/
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typedef u_int32_t pcell_t;
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#ifdef OFW_NEWPCI
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struct ofw_bus_iinfo {
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u_int8_t *opi_imap;
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u_int8_t *opi_imapmsk;
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@ -52,13 +50,4 @@ int ofw_bus_lookup_imap(phandle_t, struct ofw_bus_iinfo *, void *, int,
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int ofw_bus_search_intrmap(void *, int, void *, int, void *, int, void *,
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void *, void *, int);
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#else
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typedef int obr_callback_t(phandle_t, u_int8_t *, int, u_int8_t *, int,
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u_int8_t **, int *, void *);
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u_int32_t ofw_bus_route_intr(phandle_t, int, obr_callback_t *, void *);
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#endif
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#endif /* !_MACHINE_OFW_BUS_H_ */
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@ -29,33 +29,25 @@
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* $FreeBSD$
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*/
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <isa/isa_common.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/intr_machdep.h>
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#include <machine/ofw_bus.h>
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#include <machine/resource.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <sparc64/pci/ofw_pci.h>
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#include <sparc64/isa/ofw_isa.h>
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@ -65,19 +57,16 @@ bus_space_handle_t isa_io_hdl;
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bus_space_tag_t isa_mem_bt = NULL;
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bus_space_handle_t isa_mem_hdl;
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u_int64_t isa_io_base;
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u_int64_t isa_io_limit;
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u_int64_t isa_mem_base;
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u_int64_t isa_mem_limit;
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static u_int64_t isa_io_base;
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static u_int64_t isa_io_limit;
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static u_int64_t isa_mem_base;
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static u_int64_t isa_mem_limit;
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device_t isa_bus_device;
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static phandle_t isab_node;
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static ofw_pci_intr_t isa_ino[8];
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#ifdef OFW_NEWPCI
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struct ofw_bus_iinfo isa_iinfo;
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#endif
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/*
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* XXX: This is really partly partly PCI-specific, but unfortunately is
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@ -117,26 +106,17 @@ isa_init(device_t dev)
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device_t bridge;
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phandle_t node;
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ofw_isa_intr_t ino;
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#ifndef OFW_NEWPCI
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ofw_pci_intr_t rino;
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#endif
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struct isa_ranges *br;
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int nbr, i;
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/* The parent of the bus must be a PCI-ISA bridge. */
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bridge = device_get_parent(dev);
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#ifdef OFW_NEWPCI
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isab_node = ofw_pci_get_node(bridge);
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#else
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isab_node = ofw_pci_node(bridge);
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#endif
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nbr = OF_getprop_alloc(isab_node, "ranges", sizeof(*br), (void **)&br);
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if (nbr <= 0)
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panic("isa_init: cannot get bridge range property");
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#ifdef OFW_NEWPCI
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ofw_bus_setup_iinfo(isab_node, &isa_iinfo, sizeof(ofw_isa_intr_t));
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#endif
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/*
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* This is really a bad kludge; however, it is needed to provide
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@ -150,13 +130,8 @@ isa_init(device_t dev)
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continue;
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if (ino > 7)
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panic("isa_init: XXX: ino too large");
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#ifdef OFW_NEWPCI
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isa_ino[ino] = ofw_isa_route_intr(bridge, node, &isa_iinfo,
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ino);
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#else
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rino = ofw_bus_route_intr(node, ino, ofw_pci_orb_callback, dev);
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isa_ino[ino] = rino == ORIR_NOTFOUND ? PCI_INVALID_IRQ : rino;
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#endif
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}
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for (nbr -= 1; nbr >= 0; nbr--) {
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@ -35,14 +35,11 @@
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* Helper functions which can be used in both ISA and EBus code.
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*/
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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@ -100,7 +97,6 @@ ofw_isa_range_map(struct isa_ranges *range, int nrange, u_long *start,
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*start, *end);
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}
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#ifdef OFW_NEWPCI
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ofw_pci_intr_t
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ofw_isa_route_intr(device_t bridge, phandle_t node, struct ofw_bus_iinfo *ii,
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ofw_isa_intr_t intr)
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@ -122,4 +118,3 @@ ofw_isa_route_intr(device_t bridge, phandle_t node, struct ofw_bus_iinfo *ii,
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}
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return (mintr);
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}
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#endif /* OFW_NEWPCI */
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@ -64,27 +64,11 @@ struct isa_ranges {
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typedef u_int32_t ofw_isa_intr_t;
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struct isa_imap {
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u_int32_t phys_hi; /* high phys addr mask */
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u_int32_t phys_lo; /* low phys addr mask */
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ofw_isa_intr_t intr; /* interrupt mask */
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phandle_t cnode; /* child node */
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ofw_pci_intr_t cintr; /* child interrupt */
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};
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struct isa_imap_msk {
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u_int32_t phys_hi; /* high phys addr */
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u_int32_t phys_lo; /* low phys addr */
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ofw_isa_intr_t intr; /* interrupt */
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};
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int ofw_isa_range_restype(struct isa_ranges *);
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/* Map an IO range. Returns the resource type of the range. */
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int ofw_isa_range_map(struct isa_ranges *, int, u_long *, u_long *, int *);
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#ifdef OFW_NEWPCI
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ofw_pci_intr_t ofw_isa_route_intr(device_t, phandle_t, struct ofw_bus_iinfo *,
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ofw_isa_intr_t);
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#endif
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#endif /* !_SPARC64_ISA_OFW_ISA_H_ */
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@ -37,7 +37,7 @@
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* Support for the Sun APB (Advanced PCI Bridge) PCI-PCI bridge.
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* This bridge does not fully comply to the PCI bridge specification, and is
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* therefore not supported by the generic driver.
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* We can use some pf the pcib methods anyway.
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* We can use some of the pcib methods anyway.
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*/
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#include "opt_ofw_pci.h"
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@ -45,11 +45,9 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <machine/bus.h>
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#include <machine/ofw_bus.h>
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@ -76,9 +74,6 @@ struct apb_softc {
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static device_probe_t apb_probe;
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static device_attach_t apb_attach;
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static bus_alloc_resource_t apb_alloc_resource;
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#ifndef OFW_NEWPCI
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static pcib_route_interrupt_t apb_route_interrupt;
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#endif
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static device_method_t apb_methods[] = {
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/* Device interface */
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@ -103,17 +98,11 @@ static device_method_t apb_methods[] = {
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, pcib_read_config),
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DEVMETHOD(pcib_write_config, pcib_write_config),
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#ifdef OFW_NEWPCI
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DEVMETHOD(pcib_route_interrupt, ofw_pcib_gen_route_interrupt),
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#else
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DEVMETHOD(pcib_route_interrupt, apb_route_interrupt),
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#endif
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/* ofw_pci interface */
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#ifdef OFW_NEWPCI
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DEVMETHOD(ofw_pci_get_node, ofw_pcib_gen_get_node),
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DEVMETHOD(ofw_pci_adjust_busrange, ofw_pcib_gen_adjust_busrange),
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#endif
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{ 0, 0 }
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};
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@ -190,13 +179,7 @@ apb_attach(device_t dev)
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*/
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sc->sc_iomap = pci_read_config(dev, APBR_IOMAP, 1);
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sc->sc_memmap = pci_read_config(dev, APBR_MEMMAP, 1);
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#ifdef OFW_NEWPCI
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ofw_pcib_gen_setup(dev);
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#else
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sc->sc_bsc.ops_pcib_sc.dev = dev;
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sc->sc_bsc.ops_pcib_sc.secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
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sc->sc_bsc.ops_pcib_sc.subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
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#endif
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if (bootverbose) {
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device_printf(dev, " secondary bus %d\n",
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@ -211,11 +194,6 @@ apb_attach(device_t dev)
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printf("\n");
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}
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#ifndef OFW_NEWPCI
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if (sc->sc_bsc.ops_pcib_sc.secbus == 0)
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panic("apb_attach: APB with uninitialized secbus");
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#endif
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device_add_child(dev, "pci", sc->sc_bsc.ops_pcib_sc.secbus);
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return (bus_generic_attach(dev));
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}
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@ -233,8 +211,8 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
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sc = device_get_softc(dev);
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/*
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* If this is a "default" allocation against this rid, we can't work
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* out where it's coming from (we should actually never see these) so we
|
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* just have to punt.
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* out where it's coming from (we should actually never see these) so
|
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* we just have to punt.
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*/
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if ((start == 0) && (end == ~0)) {
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device_printf(dev, "can't decode default resource id %d for "
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@ -291,31 +269,3 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
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return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
|
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count, flags));
|
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}
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#ifndef OFW_NEWPCI
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/*
|
||||
* Route an interrupt across a PCI bridge - we need to rely on the firmware
|
||||
* here.
|
||||
*/
|
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static int
|
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apb_route_interrupt(device_t pcib, device_t dev, int pin)
|
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{
|
||||
|
||||
/*
|
||||
* XXX: ugly loathsome hack:
|
||||
* We can't use ofw_pci_route_intr() here; the device passed may be
|
||||
* the one of a bridge, so the original device can't be recovered.
|
||||
*
|
||||
* We need to use the firmware to route interrupts, however it has
|
||||
* no interface which could be used to interpret intpins; instead,
|
||||
* all assignments are done by device.
|
||||
*
|
||||
* The MI pci code will try to reroute interrupts of 0, although they
|
||||
* are correct; all other interrupts are preinitialized, so if we
|
||||
* get here, the intline is either 0 (so return 0), or we hit a
|
||||
* device which was not preinitialized (e.g. hotplugged stuff), in
|
||||
* which case we are lost.
|
||||
*/
|
||||
return (0);
|
||||
}
|
||||
#endif /* !OFW_NEWPCI */
|
||||
|
||||
@ -38,138 +38,18 @@
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <dev/ofw/ofw_pci.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cache.h>
|
||||
#include <machine/iommureg.h>
|
||||
#include <machine/ofw_bus.h>
|
||||
#include <machine/ver.h>
|
||||
|
||||
#include <sparc64/pci/ofw_pci.h>
|
||||
|
||||
#include "pcib_if.h"
|
||||
|
||||
u_int8_t pci_bus_cnt;
|
||||
phandle_t *pci_bus_map;
|
||||
int pci_bus_map_sz;
|
||||
static u_int8_t pci_bus_cnt;
|
||||
static phandle_t *pci_bus_map;
|
||||
static int pci_bus_map_sz;
|
||||
|
||||
#define PCI_BUS_MAP_INC 10
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
/* Do not swizzle on a PCI bus node with no interrupt-map propery. */
|
||||
#define OPQ_NO_SWIZZLE 1
|
||||
/*
|
||||
* INOs < 255 are really intpin numbers; use a driver method to figure out
|
||||
* the real INO.
|
||||
*/
|
||||
#define OPQ_INO_CALLBACK 2
|
||||
/*
|
||||
* Do not map EBus interrupts at PCI buses, but assume that they are fully
|
||||
* specified already.
|
||||
*/
|
||||
#define OPQ_EBUS_NOMAP 4
|
||||
|
||||
static struct ofw_pci_quirk {
|
||||
char *opq_model;
|
||||
int opq_quirks;
|
||||
} ofw_pci_quirks[] = {
|
||||
{ "SUNW,Ultra-4", OPQ_INO_CALLBACK | OPQ_EBUS_NOMAP },
|
||||
{ "SUNW,Ultra-1-Engine", OPQ_NO_SWIZZLE },
|
||||
};
|
||||
#define OPQ_NENT (sizeof(ofw_pci_quirks) / sizeof(ofw_pci_quirks[0]))
|
||||
|
||||
static int pci_quirks;
|
||||
|
||||
#define OFW_PCI_PCIBUS "pci"
|
||||
#define OFW_PCI_EBUS "ebus"
|
||||
|
||||
int
|
||||
ofw_pci_orb_callback(phandle_t node, u_int8_t *pintptr, int pintsz,
|
||||
u_int8_t *pregptr, int pregsz, u_int8_t **rintr, int *terminate,
|
||||
void *cookie)
|
||||
{
|
||||
device_t dev = cookie;
|
||||
struct ofw_pci_register preg;
|
||||
ofw_pci_intr_t pintr, intr;
|
||||
u_int slot;
|
||||
char type[32];
|
||||
int found = 0;
|
||||
|
||||
if ((pci_quirks & OPQ_EBUS_NOMAP) != 0 &&
|
||||
OF_getprop(node, "name", type, sizeof(type)) != -1 &&
|
||||
strcmp(type, OFW_PCI_EBUS) == 0) {
|
||||
*terminate = 1;
|
||||
return (-1);
|
||||
}
|
||||
if (pintsz != sizeof(pintr) || pregsz < sizeof(preg))
|
||||
return (-1);
|
||||
bcopy(pintptr, &pintr, sizeof(pintr));
|
||||
bcopy(pregptr, &preg, sizeof(preg));
|
||||
slot = OFW_PCI_PHYS_HI_DEVICE(preg.phys_hi);
|
||||
|
||||
if ((pci_quirks & OPQ_INO_CALLBACK) != 0 && pintr <= 255) {
|
||||
/*
|
||||
* The e450 has no interrupt maps at all, and it usually has
|
||||
* full interrupt numbers, including IGN, in the interrupt
|
||||
* properties. There is one exception, however: the property
|
||||
* values for external PCI devices seem to always be below 255
|
||||
* and describe the interrupt pin to be used on the slot, while
|
||||
* we have to figure out the base INO by looking at the slot
|
||||
* number (which we do using an ofw_pci method).
|
||||
*
|
||||
* Of course, there is an exception to that nice rule:
|
||||
* in the ebus case, the interrupt property has the correct
|
||||
* INO (but without IGN). This is dealt with above.
|
||||
*/
|
||||
intr = OFW_PCI_GUESS_INO(dev, node, slot, pintr);
|
||||
found = intr != 255;
|
||||
*terminate = found;
|
||||
}
|
||||
if (!found && (pci_quirks & OPQ_NO_SWIZZLE) == 0 &&
|
||||
OF_getprop(node, "device_type", type, sizeof(type)) != -1 &&
|
||||
strcmp(type, OFW_PCI_PCIBUS) == 0 && pintr >= 1 && pintr <= 4) {
|
||||
/*
|
||||
* Handle a quirk found on some Netra t1 models: there exist
|
||||
* PCI bridges without interrupt maps, where we apparently must
|
||||
* do the PCI swizzle and continue to map on at the parent.
|
||||
*/
|
||||
intr = (slot + pintr + 3) % 4 + 1;
|
||||
*terminate = 0;
|
||||
found = 1;
|
||||
}
|
||||
|
||||
if (found) {
|
||||
*rintr = malloc(sizeof(intr), M_OFWPROP, M_WAITOK);
|
||||
bcopy(&intr, *rintr, sizeof(intr));
|
||||
return (sizeof(intr));
|
||||
} else
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static ofw_pci_intr_t
|
||||
ofw_pci_route_intr(device_t dev, phandle_t node, ofw_pci_intr_t ign)
|
||||
{
|
||||
u_int32_t rv;
|
||||
|
||||
rv = ofw_bus_route_intr(node, ORIP_NOINT, ofw_pci_orb_callback, dev);
|
||||
if (rv == ORIR_NOTFOUND)
|
||||
return (PCI_INVALID_IRQ);
|
||||
/*
|
||||
* Some machines (notably the SPARCengine Ultra AX and the e450) have
|
||||
* no mappings at all, but use complete interrupt vector number
|
||||
* including the IGN. Catch this case and remove the IGN.
|
||||
*/
|
||||
if (rv > ign)
|
||||
rv -= ign;
|
||||
return (rv);
|
||||
}
|
||||
#endif /* !OFW_NEWCPI */
|
||||
|
||||
u_int8_t
|
||||
ofw_pci_alloc_busno(phandle_t node)
|
||||
{
|
||||
@ -193,199 +73,3 @@ ofw_pci_alloc_busno(phandle_t node)
|
||||
pci_bus_map[n] = node;
|
||||
return (n);
|
||||
}
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
/*
|
||||
* Initialize bridge bus numbers for bridges that implement the primary,
|
||||
* secondary and subordinate bus number registers.
|
||||
*/
|
||||
void
|
||||
ofw_pci_binit(device_t busdev, struct ofw_pci_bdesc *obd)
|
||||
{
|
||||
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
printf("PCI-PCI bridge at %u/%u/%u: setting bus #s to %u/%u/%u\n",
|
||||
obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus,
|
||||
obd->obd_secbus, obd->obd_subbus);
|
||||
#endif /* OFW_PCI_DEBUG */
|
||||
PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
|
||||
PCIR_PRIBUS_1, obd->obd_bus, 1);
|
||||
PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
|
||||
PCIR_SECBUS_1, obd->obd_secbus, 1);
|
||||
PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
|
||||
PCIR_SUBBUS_1, obd->obd_subbus, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Walk the PCI bus hierarchy, starting with the root PCI bus and descending
|
||||
* through bridges, and initialize the interrupt line and latency timer
|
||||
* configuration registers of attached devices using firmware information,
|
||||
* as well as the the bus numbers and ranges of the bridges.
|
||||
*/
|
||||
void
|
||||
ofw_pci_init(device_t dev, phandle_t bushdl, ofw_pci_intr_t ign,
|
||||
struct ofw_pci_bdesc *obd)
|
||||
{
|
||||
struct ofw_pci_register pcir;
|
||||
struct ofw_pci_bdesc subobd, *tobd;
|
||||
phandle_t node;
|
||||
char type[32];
|
||||
int i, intr, freemap;
|
||||
u_int slot, busno, func, sub, lat;
|
||||
u_int8_t clnsz;
|
||||
|
||||
/* Initialize the quirk list. */
|
||||
for (i = 0; i < OPQ_NENT; i++) {
|
||||
if (strcmp(sparc64_model, ofw_pci_quirks[i].opq_model) == 0) {
|
||||
pci_quirks = ofw_pci_quirks[i].opq_quirks;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((node = OF_child(bushdl)) == 0)
|
||||
return;
|
||||
freemap = 0;
|
||||
busno = obd->obd_secbus;
|
||||
/*
|
||||
* Compute the value to write into the cache line size register.
|
||||
* The role of the streaming cache is unclear in write invalidate
|
||||
* transfers, so it is made sure that it's line size is always reached.
|
||||
*/
|
||||
clnsz = imax(cache.ec_linesize, STRBUF_LINESZ);
|
||||
KASSERT((clnsz / STRBUF_LINESZ) * STRBUF_LINESZ == clnsz &&
|
||||
(clnsz / cache.ec_linesize) * cache.ec_linesize == clnsz &&
|
||||
(clnsz / 4) * 4 == clnsz, ("bogus cache line size %d", clnsz));
|
||||
|
||||
do {
|
||||
if (node == -1)
|
||||
panic("ofw_pci_init_intr: OF_child failed");
|
||||
if (OF_getprop(node, "device_type", type, sizeof(type)) == -1)
|
||||
type[0] = '\0';
|
||||
else
|
||||
type[sizeof(type) - 1] = '\0';
|
||||
if (OF_getprop(node, "reg", &pcir, sizeof(pcir)) == -1)
|
||||
panic("ofw_pci_init: OF_getprop failed");
|
||||
slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
|
||||
func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
|
||||
PCIB_WRITE_CONFIG(dev, busno, slot, func, PCIR_CACHELNSZ,
|
||||
clnsz / 4, 1);
|
||||
if (strcmp(type, OFW_PCI_PCIBUS) == 0) {
|
||||
/*
|
||||
* This is a pci-pci bridge, initalize the bus number and
|
||||
* recurse to initialize the child bus. The hierarchy is
|
||||
* usually at most 2 levels deep, so recursion is
|
||||
* feasible.
|
||||
*/
|
||||
subobd.obd_bus = busno;
|
||||
subobd.obd_slot = slot;
|
||||
subobd.obd_func = func;
|
||||
sub = ofw_pci_alloc_busno(node);
|
||||
subobd.obd_secbus = subobd.obd_subbus = sub;
|
||||
/* Assume this bridge is mostly standard conforming. */
|
||||
subobd.obd_init = ofw_pci_binit;
|
||||
subobd.obd_super = obd;
|
||||
/*
|
||||
* Need to change all subordinate bus registers of the
|
||||
* bridges above this one now so that configuration
|
||||
* transactions will get through.
|
||||
*/
|
||||
for (tobd = obd; tobd != NULL; tobd = tobd->obd_super) {
|
||||
tobd->obd_subbus = sub;
|
||||
tobd->obd_init(dev, tobd);
|
||||
}
|
||||
subobd.obd_init(dev, &subobd);
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
device_printf(dev, "%s: descending to "
|
||||
"subordinate PCI bus\n", __func__);
|
||||
#endif /* OFW_PCI_DEBUG */
|
||||
ofw_pci_init(dev, node, ign, &subobd);
|
||||
} else {
|
||||
/*
|
||||
* Initialize the latency timer register for
|
||||
* busmaster devices to work properly. This is another
|
||||
* task which the firmware does not always perform.
|
||||
* The Min_Gnt register can be used to compute it's
|
||||
* recommended value: it contains the desired latency
|
||||
* in units of 1/4 us. To calculate the correct latency
|
||||
* timer value, a bus clock of 33 and no wait states
|
||||
* should be assumed.
|
||||
*/
|
||||
lat = PCIB_READ_CONFIG(dev, busno, slot, func,
|
||||
PCIR_MINGNT, 1) * 33 / 4;
|
||||
if (lat != 0) {
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
printf("device %d/%d/%d: latency timer %d -> "
|
||||
"%d\n", busno, slot, func,
|
||||
PCIB_READ_CONFIG(dev, busno, slot, func,
|
||||
PCIR_LATTIMER, 1), lat);
|
||||
#endif /* OFW_PCI_DEBUG */
|
||||
PCIB_WRITE_CONFIG(dev, busno, slot, func,
|
||||
PCIR_LATTIMER, imin(lat, 255), 1);
|
||||
}
|
||||
|
||||
/* Initialize the intline registers. */
|
||||
if ((intr = ofw_pci_route_intr(dev, node, ign)) !=
|
||||
PCI_INVALID_IRQ) {
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
device_printf(dev, "%s: mapping intr for "
|
||||
"%d/%d/%d to %d (preset was %d)\n",
|
||||
__func__, busno, slot, func, intr,
|
||||
(int)PCIB_READ_CONFIG(dev, busno, slot,
|
||||
func, PCIR_INTLINE, 1));
|
||||
#endif /* OFW_PCI_DEBUG */
|
||||
PCIB_WRITE_CONFIG(dev, busno, slot, func,
|
||||
PCIR_INTLINE, intr, 1);
|
||||
} else {
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
device_printf(dev, "%s: no interrupt "
|
||||
"mapping found for %d/%d/%d (preset %d)\n",
|
||||
__func__, busno, slot, func,
|
||||
(int)PCIB_READ_CONFIG(dev, busno, slot,
|
||||
func, PCIR_INTLINE, 1));
|
||||
#endif /* OFW_PCI_DEBUG */
|
||||
/*
|
||||
* The firmware initializes to 0 instead of
|
||||
* 255.
|
||||
*/
|
||||
PCIB_WRITE_CONFIG(dev, busno, slot, func,
|
||||
PCIR_INTLINE, PCI_INVALID_IRQ, 1);
|
||||
}
|
||||
}
|
||||
} while ((node = OF_peer(node)) != 0);
|
||||
}
|
||||
|
||||
phandle_t
|
||||
ofw_pci_find_node(int bus, int slot, int func)
|
||||
{
|
||||
phandle_t node, bnode;
|
||||
struct ofw_pci_register pcir;
|
||||
|
||||
/*
|
||||
* Retrieve the bus node from the mapping that was created on
|
||||
* initialization. The bus numbers the firmware uses cannot be trusted,
|
||||
* so they might have needed to be changed and this is necessary.
|
||||
*/
|
||||
if (bus >= pci_bus_map_sz)
|
||||
return (0);
|
||||
bnode = pci_bus_map[bus];
|
||||
if (bnode == 0)
|
||||
return (0);
|
||||
for (node = OF_child(bnode); node != 0 && node != -1;
|
||||
node = OF_peer(node)) {
|
||||
if (OF_getprop(node, "reg", &pcir, sizeof(pcir)) == -1)
|
||||
continue;
|
||||
if (OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi) == slot &&
|
||||
OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi) == func)
|
||||
return (node);
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
phandle_t
|
||||
ofw_pci_node(device_t dev)
|
||||
{
|
||||
|
||||
return (ofw_pci_find_node(pci_get_bus(dev), pci_get_slot(dev),
|
||||
pci_get_function(dev)));
|
||||
}
|
||||
#endif /* OFW_NEWPCI */
|
||||
|
||||
@ -46,26 +46,8 @@ typedef u_int32_t ofw_pci_intr_t;
|
||||
#define PCI_CS_MEM32 0x02
|
||||
#define PCI_CS_MEM64 0x03
|
||||
|
||||
struct ofw_pci_imap {
|
||||
u_int32_t phys_hi;
|
||||
u_int32_t phys_mid;
|
||||
u_int32_t phys_lo;
|
||||
ofw_pci_intr_t intr;
|
||||
phandle_t child_node;
|
||||
phandle_t child_intr;
|
||||
};
|
||||
|
||||
struct ofw_pci_imap_msk {
|
||||
u_int32_t phys_hi;
|
||||
u_int32_t phys_mid;
|
||||
u_int32_t phys_lo;
|
||||
ofw_pci_intr_t intr;
|
||||
};
|
||||
|
||||
u_int8_t ofw_pci_alloc_busno(phandle_t);
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
|
||||
static __inline phandle_t
|
||||
ofw_pci_get_node(device_t dev)
|
||||
{
|
||||
@ -73,26 +55,4 @@ ofw_pci_get_node(device_t dev)
|
||||
return (OFW_PCI_GET_NODE(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
struct ofw_pci_bdesc;
|
||||
typedef void ofw_pci_binit_t(device_t, struct ofw_pci_bdesc *);
|
||||
|
||||
struct ofw_pci_bdesc {
|
||||
u_int obd_bus;
|
||||
u_int obd_slot;
|
||||
u_int obd_func;
|
||||
u_int obd_secbus;
|
||||
u_int obd_subbus;
|
||||
ofw_pci_binit_t *obd_init;
|
||||
struct ofw_pci_bdesc *obd_super;
|
||||
};
|
||||
|
||||
obr_callback_t ofw_pci_orb_callback;
|
||||
ofw_pci_binit_t ofw_pci_binit;
|
||||
void ofw_pci_init(device_t, phandle_t, ofw_pci_intr_t, struct ofw_pci_bdesc *);
|
||||
phandle_t ofw_pci_find_node(int, int, int);
|
||||
phandle_t ofw_pci_node(device_t);
|
||||
#endif
|
||||
|
||||
#endif /* ! _SPARC64_PCI_OFW_PCI_H_ */
|
||||
|
||||
@ -34,7 +34,6 @@ INTERFACE ofw_pci;
|
||||
|
||||
CODE {
|
||||
static ofw_pci_intr_pending_t ofw_pci_default_intr_pending;
|
||||
static ofw_pci_guess_ino_t ofw_pci_default_guess_ino;
|
||||
static ofw_pci_get_bus_handle_t ofw_pci_default_get_bus_handle;
|
||||
static ofw_pci_get_node_t ofw_pci_default_get_node;
|
||||
static ofw_pci_adjust_busrange_t ofw_pci_default_adjust_busrange;
|
||||
@ -46,15 +45,6 @@ CODE {
|
||||
return (OFW_PCI_INTR_PENDING(device_get_parent(dev), intr));
|
||||
}
|
||||
|
||||
static ofw_pci_intr_t
|
||||
ofw_pci_default_guess_ino(device_t dev, phandle_t node, u_int slot,
|
||||
u_int pin)
|
||||
{
|
||||
|
||||
return (OFW_PCI_GUESS_INO(device_get_parent(dev), node, slot,
|
||||
pin));
|
||||
}
|
||||
|
||||
static bus_space_handle_t
|
||||
ofw_pci_default_get_bus_handle(device_t dev, int type,
|
||||
bus_space_handle_t childhdl, bus_space_tag_t *tag)
|
||||
@ -85,18 +75,6 @@ METHOD int intr_pending {
|
||||
ofw_pci_intr_t intr;
|
||||
} DEFAULT ofw_pci_default_intr_pending;
|
||||
|
||||
# Let the bus driver guess the INO of the device at the given slot and intpin
|
||||
# on the bus described by the node if it could not be determined from the
|
||||
# firmware properties. Returns 255 if no INO could be found (mapping will
|
||||
# continue at the parent), or the desired INO.
|
||||
# This method is only used in the !OFW_NEWPCI case, and will go away soon.
|
||||
METHOD ofw_pci_intr_t guess_ino {
|
||||
device_t dev;
|
||||
phandle_t node;
|
||||
u_int slot;
|
||||
u_int pin;
|
||||
} DEFAULT ofw_pci_default_guess_ino;
|
||||
|
||||
# Get the bustag for the root bus. This is needed for ISA old-stlye
|
||||
# in[bwl]()/out[bwl]() support, where no tag retrieved from a resource is
|
||||
# passed. The returned tag is used to construct a tag for the whole ISA bus.
|
||||
@ -107,8 +85,8 @@ METHOD bus_space_handle_t get_bus_handle {
|
||||
bus_space_tag_t *tag;
|
||||
} DEFAULT ofw_pci_default_get_bus_handle;
|
||||
|
||||
# Get the firmware node for the device dev on the bus bus. The default mthod
|
||||
# will return 0, which signals that there is no such node.
|
||||
# Get the firmware node for the device dev on the bus. The default method will
|
||||
# return 0, which signals that there is no such node.
|
||||
# This could be an ivar, but isn't to avoid numbering conflicts with standard
|
||||
# pci/pcib ones.
|
||||
METHOD phandle_t get_node {
|
||||
|
||||
@ -39,7 +39,6 @@
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/pciio.h>
|
||||
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
*/
|
||||
|
||||
#include "opt_ofw_pci.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
@ -131,4 +132,3 @@ ofw_pcib_gen_adjust_busrange(device_t bridge, u_int subbus)
|
||||
OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), subbus);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -35,10 +35,8 @@ struct ofw_pcib_gen_softc {
|
||||
* filled.
|
||||
*/
|
||||
struct pcib_softc ops_pcib_sc;
|
||||
#ifdef OFW_NEWPCI
|
||||
phandle_t ops_node;
|
||||
struct ofw_bus_iinfo ops_iinfo;
|
||||
#endif
|
||||
};
|
||||
|
||||
void ofw_pcib_gen_setup(device_t);
|
||||
|
||||
@ -59,7 +59,6 @@
|
||||
#include <machine/ofw_bus.h>
|
||||
#include <machine/ofw_upa.h>
|
||||
#include <machine/resource.h>
|
||||
#include <machine/cpu.h>
|
||||
|
||||
#include <sys/rman.h>
|
||||
|
||||
@ -80,9 +79,6 @@ static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *,
|
||||
bus_addr_t *, u_long *);
|
||||
static void psycho_intr_stub(void *);
|
||||
static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
|
||||
#ifndef OFW_NEWPCI
|
||||
static ofw_pci_binit_t psycho_binit;
|
||||
#endif
|
||||
|
||||
/* Interrupt handlers */
|
||||
static void psycho_ue(void *);
|
||||
@ -114,14 +110,9 @@ static pcib_read_config_t psycho_read_config;
|
||||
static pcib_write_config_t psycho_write_config;
|
||||
static pcib_route_interrupt_t psycho_route_interrupt;
|
||||
static ofw_pci_intr_pending_t psycho_intr_pending;
|
||||
#ifndef OFW_NEWPCI
|
||||
static ofw_pci_guess_ino_t psycho_guess_ino;
|
||||
#endif
|
||||
static ofw_pci_get_bus_handle_t psycho_get_bus_handle;
|
||||
#ifdef OFW_NEWPCI
|
||||
static ofw_pci_get_node_t psycho_get_node;
|
||||
static ofw_pci_adjust_busrange_t psycho_adjust_busrange;
|
||||
#endif
|
||||
|
||||
static device_method_t psycho_methods[] = {
|
||||
/* Device interface */
|
||||
@ -146,14 +137,9 @@ static device_method_t psycho_methods[] = {
|
||||
|
||||
/* ofw_pci interface */
|
||||
DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending),
|
||||
#ifndef OFW_NEWPCI
|
||||
DEVMETHOD(ofw_pci_guess_ino, psycho_guess_ino),
|
||||
#endif
|
||||
DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle),
|
||||
#ifdef OFW_NEWPCI
|
||||
DEVMETHOD(ofw_pci_get_node, psycho_get_node),
|
||||
DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange),
|
||||
#endif
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
@ -297,9 +283,6 @@ psycho_attach(device_t dev)
|
||||
struct psycho_softc *osc = NULL;
|
||||
struct psycho_softc *asc;
|
||||
struct upa_regs *reg;
|
||||
#ifndef OFW_NEWPCI
|
||||
struct ofw_pci_bdesc obd;
|
||||
#endif
|
||||
struct psycho_desc *desc;
|
||||
phandle_t node;
|
||||
u_int64_t csr;
|
||||
@ -583,27 +566,7 @@ psycho_attach(device_t dev)
|
||||
PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS,
|
||||
sc->sc_secbus, 1);
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t));
|
||||
#else
|
||||
obd.obd_bus = obd.obd_secbus = sc->sc_secbus;
|
||||
obd.obd_subbus = sc->sc_subbus;
|
||||
obd.obd_slot = PCS_DEVICE;
|
||||
obd.obd_func = PCS_FUNC;
|
||||
obd.obd_init = psycho_binit;
|
||||
obd.obd_super = NULL;
|
||||
|
||||
/*
|
||||
* Initialize the interrupt registers of all devices hanging from
|
||||
* the host bridge directly or indirectly via PCI-PCI bridges.
|
||||
* The MI code (and the PCI spec) assume that this is done during
|
||||
* system initialization, however the firmware does not do this
|
||||
* at least on some models, and we probably shouldn't trust that
|
||||
* the firmware uses the same model as this driver if it does.
|
||||
* Additionally, set up the bus numbers and ranges.
|
||||
*/
|
||||
ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd);
|
||||
#endif /* OFW_NEWPCI */
|
||||
|
||||
device_add_child(dev, "pci", sc->sc_secbus);
|
||||
return (bus_generic_attach(dev));
|
||||
@ -792,21 +755,6 @@ psycho_iommu_init(struct psycho_softc *sc, int tsbsize)
|
||||
iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0);
|
||||
}
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
static void
|
||||
psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd)
|
||||
{
|
||||
|
||||
#ifdef PSYCHO_DEBUG
|
||||
printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n",
|
||||
obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus,
|
||||
obd->obd_secbus, obd->obd_subbus);
|
||||
#endif /* PSYCHO_DEBUG */
|
||||
PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func,
|
||||
PCSR_SUBBUS, obd->obd_subbus, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
psycho_maxslots(device_t dev)
|
||||
{
|
||||
@ -815,32 +763,6 @@ psycho_maxslots(device_t dev)
|
||||
return (PCI_SLOTMAX);
|
||||
}
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
/*
|
||||
* Keep a table of quirky PCI devices that need fixups before the MI PCI code
|
||||
* creates the resource lists. This needs to be moved around once other bus
|
||||
* drivers are added. Moving it to the MI code should maybe be reconsidered
|
||||
* if one of these devices appear in non-sparc64 boxen. It's likely that not
|
||||
* all BIOSes/firmwares can deal with them.
|
||||
*/
|
||||
struct psycho_dquirk {
|
||||
u_int32_t dq_devid;
|
||||
int dq_quirk;
|
||||
};
|
||||
|
||||
/* Quirk types. May be or'ed together. */
|
||||
#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */
|
||||
|
||||
static struct psycho_dquirk dquirks[] = {
|
||||
{ 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */
|
||||
{ 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */
|
||||
{ 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */
|
||||
{ 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */
|
||||
};
|
||||
#endif /* !OFW_NEWPCI */
|
||||
|
||||
#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0]))
|
||||
|
||||
static u_int32_t
|
||||
psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
int width)
|
||||
@ -848,9 +770,6 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
struct psycho_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
u_long offset = 0;
|
||||
#ifndef OFW_NEWPCI
|
||||
u_int32_t devid;
|
||||
#endif
|
||||
u_int8_t byte;
|
||||
u_int16_t shrt;
|
||||
u_int32_t wrd;
|
||||
@ -884,30 +803,6 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
#endif
|
||||
r = -1;
|
||||
}
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
if (reg == PCIR_INTPIN && r == 0) {
|
||||
/* Check for DQT_BAD_INTPIN quirk. */
|
||||
devid = psycho_read_config(dev, bus, slot, func,
|
||||
PCIR_DEVVENDOR, 4);
|
||||
for (i = 0; i < NDQUIRKS; i++) {
|
||||
if (dquirks[i].dq_devid == devid) {
|
||||
/*
|
||||
* Need to set the intpin to a value != 0 so
|
||||
* that the MI code will think that this device
|
||||
* has an interrupt.
|
||||
* Just use 1 (intpin a) for now. This is, of
|
||||
* course, bogus, but since interrupts are
|
||||
* routed in advance, this does not really
|
||||
* matter.
|
||||
*/
|
||||
if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0)
|
||||
r = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* !OFW_NEWPCI */
|
||||
return (r);
|
||||
}
|
||||
|
||||
@ -940,7 +835,6 @@ psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
static int
|
||||
psycho_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
{
|
||||
#ifdef OFW_NEWPCI
|
||||
struct psycho_softc *sc = device_get_softc(bridge);
|
||||
struct ofw_pci_register reg;
|
||||
bus_addr_t intrmap;
|
||||
@ -975,24 +869,6 @@ psycho_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n",
|
||||
(int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
|
||||
return (mintr);
|
||||
#else
|
||||
/*
|
||||
* XXX: ugly loathsome hack:
|
||||
* We can't use ofw_pci_route_intr() here; the device passed may be
|
||||
* the one of a bridge, so the original device can't be recovered.
|
||||
*
|
||||
* We need to use the firmware to route interrupts, however it has
|
||||
* no interface which could be used to interpret intpins; instead,
|
||||
* all assignments are done by device.
|
||||
*
|
||||
* The MI pci code will try to reroute interrupts of 0, although they
|
||||
* are correct; all other interrupts are preinitialized, so if we
|
||||
* get here, the intline is either 0 (so return 0), or we hit a
|
||||
* device which was not preinitialized (e.g. hotplugged stuff), in
|
||||
* which case we are lost.
|
||||
*/
|
||||
return (0);
|
||||
#endif /* OFW_NEWPCI */
|
||||
}
|
||||
|
||||
static int
|
||||
@ -1238,33 +1114,6 @@ psycho_intr_pending(device_t dev, ofw_pci_intr_t intr)
|
||||
return (diag != 0);
|
||||
}
|
||||
|
||||
#ifndef OFW_NEWPCI
|
||||
static ofw_pci_intr_t
|
||||
psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin)
|
||||
{
|
||||
struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev);
|
||||
bus_addr_t intrmap;
|
||||
|
||||
/*
|
||||
* If this is not for one of our direct children (i.e. we are mapping
|
||||
* at our node), tell the interrupt mapper to go on - we need the
|
||||
* slot number of the device or it's topmost parent bridge to guess
|
||||
* the INO.
|
||||
*/
|
||||
if (node != sc->sc_node)
|
||||
return (PCI_INVALID_IRQ);
|
||||
/*
|
||||
* Actually guess the INO. We always assume that this is a non-OBIO
|
||||
* device, and use from the slot number to determine it.
|
||||
* We only need to do this on e450s, it seems; here, the slot numbers
|
||||
* for bus A are one-based, while those for bus B seemingly have an
|
||||
* offset of 2 (hence the factor of 3 below).
|
||||
*/
|
||||
intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half);
|
||||
return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1);
|
||||
}
|
||||
#endif /* !OFW_NEWPCI */
|
||||
|
||||
static bus_space_handle_t
|
||||
psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl,
|
||||
bus_space_tag_t *tag)
|
||||
@ -1284,7 +1133,6 @@ psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl,
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
static phandle_t
|
||||
psycho_get_node(device_t bus, device_t dev)
|
||||
{
|
||||
@ -1311,7 +1159,6 @@ psycho_adjust_busrange(device_t dev, u_int subbus)
|
||||
PCSR_SUBBUS, subbus, 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static bus_space_tag_t
|
||||
psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
|
||||
|
||||
@ -67,9 +67,7 @@ struct psycho_softc {
|
||||
struct resource *sc_irq_res[6];
|
||||
void *sc_ihand[6];
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
struct ofw_bus_iinfo sc_iinfo;
|
||||
#endif
|
||||
|
||||
struct upa_ranges *sc_range;
|
||||
int sc_nrange;
|
||||
|
||||
@ -64,8 +64,6 @@
|
||||
* bits left.
|
||||
*/
|
||||
|
||||
#include "opt_ofw_pci.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/systm.h>
|
||||
@ -86,8 +84,6 @@ ofw_bus_searchprop(phandle_t node, char *propname, void *buf, int buflen)
|
||||
return (-1);
|
||||
}
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
|
||||
void
|
||||
ofw_bus_setup_iinfo(phandle_t node, struct ofw_bus_iinfo *ii, int intrsz)
|
||||
{
|
||||
@ -181,7 +177,7 @@ ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
|
||||
i = imapsz;
|
||||
tsz = physsz + intrsz + sizeof(phandle_t) + rintrsz;
|
||||
while (i > 0) {
|
||||
KASSERT(i >= tsz, ("ofw_bus_find_intr: truncated map"));
|
||||
KASSERT(i >= tsz, ("ofw_bus_search_intrmap: truncated map"));
|
||||
bcopy(mptr + physsz + intrsz, &parent, sizeof(parent));
|
||||
if (ofw_bus_searchprop(parent, "#interrupt-cells",
|
||||
&pintrsz, sizeof(pintrsz)) == -1)
|
||||
@ -200,168 +196,3 @@ ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
#else
|
||||
/*
|
||||
* Map an interrupt using the firmware reg, interrupt-map and
|
||||
* interrupt-map-mask properties.
|
||||
* The interrupt is returned in *result, which is malloc()'ed. The size of
|
||||
* the interrupt specifiaction is returned.
|
||||
*/
|
||||
static int
|
||||
ofw_bus_find_intr(u_int8_t *intr, int intrsz, u_int8_t *regs, int physsz,
|
||||
u_int8_t *imap, int imapsz, u_int8_t *imapmsk, u_int8_t **result)
|
||||
{
|
||||
phandle_t parent;
|
||||
char *ref;
|
||||
u_int8_t *mptr;
|
||||
pcell_t pintrsz;
|
||||
int i, rsz, tsz;
|
||||
|
||||
rsz = -1;
|
||||
ref = malloc(physsz + intrsz, M_TEMP, M_WAITOK);
|
||||
if (imapmsk != NULL) {
|
||||
for (i = 0; i < physsz; i++)
|
||||
ref[i] = regs[i] & imapmsk[i];
|
||||
for (i = 0; i < intrsz; i++)
|
||||
ref[physsz + i] = intr[i] & imapmsk[physsz + i];
|
||||
} else {
|
||||
bcopy(regs, ref, physsz);
|
||||
bcopy(intr, ref + physsz, intrsz);
|
||||
}
|
||||
mptr = imap;
|
||||
i = imapsz;
|
||||
while (i > 0) {
|
||||
KASSERT(i >= physsz + sizeof(parent),
|
||||
("ofw_bus_find_intr: truncated map"));
|
||||
bcopy(mptr + physsz + intrsz, &parent, sizeof(parent));
|
||||
if (ofw_bus_searchprop(parent, "#interrupt-cells",
|
||||
&pintrsz, sizeof(pintrsz)) == -1)
|
||||
pintrsz = 1; /* default */
|
||||
pintrsz *= sizeof(pcell_t);
|
||||
KASSERT(i >= physsz + intrsz + sizeof(parent) +
|
||||
pintrsz, ("ofw_bus_find_intr: truncated map"));
|
||||
if (bcmp(ref, mptr, physsz + intrsz) == 0) {
|
||||
*result = malloc(pintrsz, M_OFWPROP, M_WAITOK);
|
||||
bcopy(mptr + physsz + intrsz + sizeof(parent),
|
||||
*result, pintrsz);
|
||||
rsz = pintrsz;
|
||||
break;
|
||||
}
|
||||
tsz = physsz + intrsz + sizeof(phandle_t) + pintrsz;
|
||||
mptr += tsz;
|
||||
i -= tsz;
|
||||
}
|
||||
free(ref, M_TEMP);
|
||||
return (rsz);
|
||||
}
|
||||
|
||||
/*
|
||||
* Apply the OpenFirmware algorithm for mapping an interrupt. First, the
|
||||
* 'interrupts' and 'reg' properties are retrieved; those are matched against
|
||||
* the interrupt map of the next higher node. If there is no match or no such
|
||||
* propery, we go to the next higher node, using the 'reg' property of the node
|
||||
* that was just processed unusccessfully.
|
||||
* When a match occurs, we should continue to search, using the new interrupt
|
||||
* specification that was just found; this is currently not performed
|
||||
* (see below).
|
||||
* When the root node is reached with at least one successful mapping performed,
|
||||
* and the format is right, the interrupt number is returned.
|
||||
*
|
||||
* This should work for all bus systems.
|
||||
*/
|
||||
u_int32_t
|
||||
ofw_bus_route_intr(phandle_t node, int intrp, obr_callback_t *cb, void *cookie)
|
||||
{
|
||||
u_int8_t *reg, *intr, *tintr, *imap, *imapmsk;
|
||||
phandle_t parent;
|
||||
pcell_t addrc, ic;
|
||||
u_int32_t rv;
|
||||
int regsz, tisz, isz, imapsz, found;
|
||||
|
||||
found = 0;
|
||||
reg = imap = imapmsk = NULL;
|
||||
if (intrp == ORIP_NOINT) {
|
||||
isz = OF_getprop_alloc(node, "interrupts", 1, (void **)&intr);
|
||||
if (isz < 0)
|
||||
return (ORIR_NOTFOUND);
|
||||
} else {
|
||||
ic = intrp;
|
||||
isz = sizeof(ic);
|
||||
intr = malloc(isz, M_OFWPROP, M_WAITOK);
|
||||
bcopy(&ic, intr, isz);
|
||||
}
|
||||
/*
|
||||
* Note that apparently, remapping at multiple levels is allowed;
|
||||
* however, this causes problems with EBus at least, and seems to never
|
||||
* be needed, so we disable it for now (*sigh*).
|
||||
*/
|
||||
for (parent = OF_parent(node); parent != 0 && !found;
|
||||
parent = OF_parent(node = parent)) {
|
||||
if (reg != NULL)
|
||||
free(reg, M_OFWPROP);
|
||||
regsz = OF_getprop_alloc(node, "reg", 1, (void **)®);
|
||||
if (regsz < 0)
|
||||
panic("ofw_bus_route_intr: could not get reg property");
|
||||
imapsz = OF_getprop_alloc(parent, "interrupt-map", 1,
|
||||
(void **)&imap);
|
||||
if (imapsz == -1) {
|
||||
/*
|
||||
* Use the callback to allow caller-specific workarounds
|
||||
* for firmware bugs (missing properties).
|
||||
*/
|
||||
if (cb != NULL) {
|
||||
tisz = cb(parent, intr, isz, reg, regsz, &tintr,
|
||||
&found, cookie);
|
||||
if (tisz != -1) {
|
||||
isz = tisz;
|
||||
free(intr, M_OFWPROP);
|
||||
intr = tintr;
|
||||
}
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (OF_getprop(parent, "#address-cells", &addrc,
|
||||
sizeof(addrc)) == -1)
|
||||
addrc = 2;
|
||||
addrc *= sizeof(pcell_t);
|
||||
/*
|
||||
* Failures to get the mask are ignored; a full mask is assumed
|
||||
* in this case.
|
||||
*/
|
||||
OF_getprop_alloc(parent, "interrupt-map-mask", 1,
|
||||
(void **)&imapmsk);
|
||||
tisz = ofw_bus_find_intr(intr, isz, reg, addrc, imap, imapsz,
|
||||
imapmsk, &tintr);
|
||||
if (tisz != -1) {
|
||||
found = 1;
|
||||
isz = tisz;
|
||||
free(intr, M_OFWPROP);
|
||||
intr = tintr;
|
||||
}
|
||||
free(imap, M_OFWPROP);
|
||||
if (imapmsk != NULL)
|
||||
free(imapmsk, M_OFWPROP);
|
||||
}
|
||||
if (reg != NULL)
|
||||
free(reg, M_OFWPROP);
|
||||
#if 0
|
||||
/*
|
||||
* Obviously there are some boxes that don't require mapping at all,
|
||||
* for example the U30, which has no interrupt maps for children of
|
||||
* the root PCI bus.
|
||||
*/
|
||||
if (!found) {
|
||||
if (intrp != ORIP_NOINT)
|
||||
return (ORIR_NOTFOUND);
|
||||
panic("ofw_bus_route_intr: 'interrupts' property, but no "
|
||||
"mapping found");
|
||||
}
|
||||
#endif
|
||||
KASSERT(isz == sizeof(u_int32_t),
|
||||
("ofw_bus_route_intr: bad interrupt spec size %d", isz));
|
||||
bcopy(intr, &rv, sizeof(rv));
|
||||
free(intr, M_OFWPROP);
|
||||
return (rv);
|
||||
}
|
||||
#endif /* OFW_NEWPCI */
|
||||
|
||||
@ -29,8 +29,6 @@
|
||||
* Some OpenFirmware helper functions that are likely machine dependent.
|
||||
*/
|
||||
|
||||
#include "opt_ofw_pci.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
@ -65,11 +63,7 @@ OF_getetheraddr2(device_t dev, u_char *addr)
|
||||
{
|
||||
phandle_t node;
|
||||
|
||||
#ifdef OFW_NEWPCI
|
||||
node = ofw_pci_get_node(dev);
|
||||
#else
|
||||
node = ofw_pci_node(dev);
|
||||
#endif
|
||||
if (node <= 0)
|
||||
return (-1);
|
||||
return (OF_getprop(node, "local-mac-address", addr, ETHER_ADDR_LEN));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user