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First pass at removing Alpha kernel support.

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This commit is contained in:
John Baldwin 2006-05-11 22:25:28 +00:00
parent 70bc2d3f4f
commit 67ab9fd759
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=158458
292 changed files with 1 additions and 57962 deletions
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28
sys/alpha/Makefile
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@ -1,28 +0,0 @@
# $FreeBSD$
# Makefile for alpha tags file
# SYS is normally set in Make.tags.inc
# SYS=/sys
TAGDIR= alpha
.include "../kern/Make.tags.inc"
all:
@echo "make tags only"
SALPHA= ${SYS}/alpha/mcbus/*.[ch] ${SYS}/alpha/tlsb/*.[ch] \
${SYS}/alpha/alpha/*.[ch] ${SYS}/alpha/pci/*.[ch] \
${SYS}/alpha/include/*.[ch] ${SYS}/alpha/isa/*.[ch] \
${SYS}/alpha/tc/*.[ch] ${SYS}/alpha/osf1/*.[ch]
AALPHA= ${SYS}/alpha/alpha/*.s
tags::
@rm -f tags
-ctags -wdt ${COMM} ${SALPHA}
egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AALPHA} | \
sed "s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \
>> tags
sort -o tags tags
chmod 444 tags

91
sys/alpha/alpha/api_up1000.c
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@ -1,91 +0,0 @@
/*-
* Copyright (c) 2000 Andrew Gallatin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/termios.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/intr.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/irongatereg.h>
#include <alpha/pci/irongatevar.h>
void api_up1000_init(void);
static void api_up1000_cons_init(void);
void
api_up1000_init()
{
platform.family = "UP1000";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
/* XXX Don't know the system variations, yet. */
platform.model = alpha_unknown_sysname();
}
platform.iobus = "irongate";
platform.cons_init = api_up1000_cons_init;
}
static void
api_up1000_cons_init()
{
struct ctb *ctb;
irongate_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %ld\n",
ctb->ctb_term_type);
}
}

143
sys/alpha/alpha/atomic.s
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@ -1,143 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <machine/asm.h>
.text
LEAF(atomic_set_8, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extbl t2, a0, t0
bis t0, a1, t0
insbl t0, a0, t0
mskbl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_set_8)
LEAF(atomic_clear_8, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extbl t2, a0, t0
bic t0, a1, t0
insbl t0, a0, t0
mskbl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_clear_8)
LEAF(atomic_add_8, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extbl t2, a0, t0
addl t0, a1, t0
insbl t0, a0, t0
mskbl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_add_8)
LEAF(atomic_subtract_8, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extbl t2, a0, t0
subl t0, a1, t0
insbl t0, a0, t0
mskbl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_subtract_8)
LEAF(atomic_set_16, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extwl t2, a0, t0
bis t0, a1, t0
inswl t0, a0, t0
mskwl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_set_16)
LEAF(atomic_clear_16, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extwl t2, a0, t0
bic t0, a1, t0
inswl t0, a0, t0
mskwl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_clear_16)
LEAF(atomic_add_16, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extwl t2, a0, t0
addl t0, a1, t0
inswl t0, a0, t0
mskwl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_add_16)
LEAF(atomic_subtract_16, 2)
bic a0, 7, t1
0: ldq_l t2, 0(t1)
extwl t2, a0, t0
subl t0, a1, t0
inswl t0, a0, t0
mskwl t2, a0, t2
or t2, t0, t0
stq_c t0, 0(t1)
beq t0, 1f
RET
1: br 0b
END(atomic_subtract_16)

108
sys/alpha/alpha/autoconf.c
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@ -1,108 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_bootp.h"
#include "opt_isa.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/reboot.h>
#include <sys/kernel.h>
#include <sys/mount.h>
#include <sys/sysctl.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/md_var.h>
#include <machine/cpuconf.h>
#include <machine/rpb.h>
#include <machine/bootinfo.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_periph.h>
#include <cam/cam_xpt_sim.h>
#include <cam/cam_debug.h>
static void configure_first(void *);
static void configure(void *);
static void configure_final(void *);
SYSINIT(configure1, SI_SUB_CONFIGURE, SI_ORDER_FIRST, configure_first, NULL);
/* SI_ORDER_SECOND is hookable */
SYSINIT(configure2, SI_SUB_CONFIGURE, SI_ORDER_THIRD, configure, NULL);
/* SI_ORDER_MIDDLE is hookable */
SYSINIT(configure3, SI_SUB_CONFIGURE, SI_ORDER_ANY, configure_final, NULL);
#ifdef DEV_ISA
#include <isa/isavar.h>
device_t isa_bus_device = 0;
#endif
/*
* Determine i/o configuration for a machine.
*/
static void
configure_first(void *dummy)
{
device_add_child(root_bus, platform.iobus, 0);
}
static void
configure(void *dummy)
{
root_bus_configure();
/*
* Probe ISA devices after everything.
*/
#ifdef DEV_ISA
if (isa_bus_device)
isa_probe_children(isa_bus_device);
#endif
}
static void
configure_final(void *dummy)
{
/*
* Now we're ready to handle (pending) interrupts.
* XXX this is slightly misplaced.
*/
alpha_pal_swpipl(ALPHA_PSL_IPL_0);
cninit_finish();
cold = 0;
}

1037
sys/alpha/alpha/busdma_machdep.c
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File diff suppressed because it is too large Load Diff

289
sys/alpha/alpha/busspace.c
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@ -1,289 +0,0 @@
/*-
* Copyright (c) 2000 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/kobj.h>
#include <machine/bus.h>
void
busspace_generic_read_multi_1(struct alpha_busspace *space, size_t offset,
u_int8_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_1(space, offset);
}
}
void
busspace_generic_read_multi_2(struct alpha_busspace *space, size_t offset,
u_int16_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_2(space, offset);
}
}
void
busspace_generic_read_multi_4(struct alpha_busspace *space, size_t offset,
u_int32_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_4(space, offset);
}
}
void
busspace_generic_read_region_1(struct alpha_busspace *space, size_t offset,
u_int8_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_1(space, offset);
offset += 1;
}
}
void
busspace_generic_read_region_2(struct alpha_busspace *space, size_t offset,
u_int16_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_2(space, offset);
offset += 2;
}
}
void
busspace_generic_read_region_4(struct alpha_busspace *space, size_t offset,
u_int32_t *addr, size_t count)
{
while (count--) {
*addr++ = space->ab_ops->abo_read_4(space, offset);
offset += 4;
}
}
void
busspace_generic_write_multi_1(struct alpha_busspace *space, size_t offset,
const u_int8_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_1(space, offset, *addr++);
}
}
void
busspace_generic_write_multi_2(struct alpha_busspace *space, size_t offset,
const u_int16_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_2(space, offset, *addr++);
}
}
void
busspace_generic_write_multi_4(struct alpha_busspace *space, size_t offset,
const u_int32_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_4(space, offset, *addr++);
}
}
void
busspace_generic_write_region_1(struct alpha_busspace *space, size_t offset,
const u_int8_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_1(space, offset, *addr++);
offset += 1;
}
}
void
busspace_generic_write_region_2(struct alpha_busspace *space, size_t offset,
const u_int16_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_2(space, offset, *addr++);
offset += 2;
}
}
void
busspace_generic_write_region_4(struct alpha_busspace *space, size_t offset,
const u_int32_t *addr, size_t count)
{
while (count--) {
space->ab_ops->abo_write_4(space, offset, *addr++);
offset += 4;
}
}
void
busspace_generic_set_multi_1(struct alpha_busspace *space, size_t offset,
u_int8_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_1(space, offset, value);
}
}
void
busspace_generic_set_multi_2(struct alpha_busspace *space, size_t offset,
u_int16_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_2(space, offset, value);
}
}
void
busspace_generic_set_multi_4(struct alpha_busspace *space, size_t offset,
u_int32_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_4(space, offset, value);
}
}
void
busspace_generic_set_region_1(struct alpha_busspace *space, size_t offset,
u_int8_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_1(space, offset, value);
offset += 1;
}
}
void
busspace_generic_set_region_2(struct alpha_busspace *space, size_t offset,
u_int16_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_2(space, offset, value);
offset += 2;
}
}
void
busspace_generic_set_region_4(struct alpha_busspace *space, size_t offset,
u_int32_t value, size_t count)
{
while (count--) {
space->ab_ops->abo_write_4(space, offset, value);
offset += 4;
}
}
void
busspace_generic_copy_region_1(struct alpha_busspace *space,
size_t offset1, size_t offset2, size_t count)
{
u_int8_t value;
if (offset1 > offset2) {
while (count--) {
value = space->ab_ops->abo_read_1(space, offset1);
space->ab_ops->abo_write_1(space, offset2, value);
offset1 += 1;
offset2 += 1;
}
} else {
offset1 += count - 1;
offset2 += count - 1;
while (count--) {
value = space->ab_ops->abo_read_1(space, offset1);
space->ab_ops->abo_write_1(space, offset2, value);
offset1 -= 1;
offset2 -= 1;
}
}
}
void
busspace_generic_copy_region_2(struct alpha_busspace *space,
size_t offset1, size_t offset2, size_t count)
{
u_int16_t value;
if (offset1 > offset2) {
while (count--) {
value = space->ab_ops->abo_read_1(space, offset1);
space->ab_ops->abo_write_1(space, offset2, value);
offset1 += 2;
offset2 += 2;
}
} else {
offset1 += 2*(count - 1);
offset2 += 2*(count - 1);
while (count--) {
value = space->ab_ops->abo_read_2(space, offset1);
space->ab_ops->abo_write_2(space, offset2, value);
offset1 -= 2;
offset2 -= 2;
}
}
}
void
busspace_generic_copy_region_4(struct alpha_busspace *space,
size_t offset1, size_t offset2, size_t count)
{
u_int32_t value;
if (offset1 > offset2) {
while (count--) {
value = space->ab_ops->abo_read_4(space, offset1);
space->ab_ops->abo_write_4(space, offset2, value);
offset1 += 4;
offset2 += 4;
}
} else {
offset1 += 4*(count - 1);
offset2 += 4*(count - 1);
while (count--) {
value = space->ab_ops->abo_read_4(space, offset1);
space->ab_ops->abo_write_4(space, offset2, value);
offset1 -= 4;
offset2 -= 4;
}
}
}
void
busspace_generic_barrier(struct alpha_busspace *space, size_t offset, size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
alpha_mb();
else
alpha_wmb();
}

671
sys/alpha/alpha/clock.c
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@ -1,671 +0,0 @@
/*-
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: clock.c 1.18 91/01/21
*
* @(#)clock.c 8.1 (Berkeley) 6/10/93
* $NetBSD: clock.c,v 1.20 1998/01/31 10:32:47 ross Exp $
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_clock.h"
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/queue.h>
#include <sys/smp.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/timetc.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <machine/clockvar.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h> /* for CPU definitions, etc */
#include <machine/ppireg.h>
#include <machine/timerreg.h>
#include <isa/isareg.h>
#define SECMIN ((unsigned)60) /* seconds per minute */
#define SECHOUR ((unsigned)(60*SECMIN)) /* seconds per hour */
#define SECDAY ((unsigned)(24*SECHOUR)) /* seconds per day */
#define SECYR ((unsigned)(365*SECDAY)) /* seconds per common year */
/*
* According to OSF/1's /usr/sys/include/arch/alpha/clock.h,
* the console adjusts the RTC years 13..19 to 93..99 and
* 20..40 to 00..20. (historical reasons?)
* DEC Unix uses an offset to the year to stay outside
* the dangerous area for the next couple of years.
*/
#define UNIX_YEAR_OFFSET 52 /* 41=>1993, 12=>2064 */
static int clock_year_offset = 0;
/*
* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
* can use a simple formula for leap years.
*/
#define LEAPYEAR(y) (((y) % 4) == 0)
device_t clockdev;
int clockinitted;
int adjkerntz; /* local offset from GMT in seconds */
int disable_rtc_set; /* disable resettodr() if != 0 */
int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
struct mtx clock_lock;
static int beeping = 0;
#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif
u_int32_t timer_freq = TIMER_FREQ;
extern int cycles_per_sec;
static timecounter_get_t i8254_get_timecount;
static timecounter_get_t alpha_get_timecount;
static struct timecounter alpha_timecounter = {
alpha_get_timecount, /* get_timecount */
0, /* no poll_pps */
~0u, /* counter_mask */
0, /* frequency */
"alpha", /* name */
800, /* quality */
};
static struct timecounter i8254_timecounter = {
i8254_get_timecount, /* get_timecount */
0, /* no poll_pps */
0xffff, /* counter_mask */
0, /* frequency */
"i8254" /* name */
};
/* Values for timerX_state: */
#define RELEASED 0
#define RELEASE_PENDING 1
#define ACQUIRED 2
#define ACQUIRE_PENDING 3
/* static u_char timer0_state; */
static u_char timer2_state;
static void calibrate_clocks(u_int32_t firmware_freq, u_int32_t *pcc,
u_int32_t *timer);
static void set_timer_freq(u_int freq, int intr_freq);
void
clockattach(device_t dev)
{
u_int32_t pcc, freq, delta;
/*
* Just bookkeeping.
*/
if (clockdev)
panic("clockattach: multiple clocks");
clockdev = dev;
calibrate_clocks(cycles_per_sec, &pcc, &freq);
cycles_per_sec = pcc;
set_cputicker(read_cycle_count, cycles_per_sec, 0);
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type == ST_DEC_21000) {
goto out;
}
/*
* Use the calibrated i8254 frequency if it seems reasonable.
* Otherwise use the default, and don't use the calibrated i586
* frequency.
*/
delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
if (delta < timer_freq / 100) {
#ifndef CLK_USE_I8254_CALIBRATION
if (bootverbose)
printf(
"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
freq = timer_freq;
#endif
timer_freq = freq;
} else {
if (bootverbose)
printf(
"%d Hz differs from default of %d Hz by more than 1%%\n",
freq, timer_freq);
}
set_timer_freq(timer_freq, hz);
out:
#ifdef EVCNT_COUNTERS
evcnt_attach(dev, "intr", &clock_intr_evcnt);
#else
/* nothing */ ;
#endif
}
/*
* Machine-dependent clock routines.
*
* Startrtclock restarts the real-time clock, which provides
* hardclock interrupts to kern_clock.c.
*
* Inittodr initializes the time of day hardware which provides
* date functions. Its primary function is to use some file
* system information in case the hardare clock lost state.
*
* Resettodr restores the time of day hardware after a time change.
*/
/*
* Start the real-time and statistics clocks.
*/
void
cpu_initclocks()
{
if (clockdev == NULL)
panic("cpu_initclocks: no clock attached");
tick = 1000000 / hz; /* number of microseconds between interrupts */
/*
* Establish the clock interrupt; it's a special case.
*
* We establish the clock interrupt this late because if
* we do it at clock attach time, we may have never been at
* spl0() since taking over the system. Some versions of
* PALcode save a clock interrupt, which would get delivered
* when we spl0() in autoconf.c. If established the clock
* interrupt handler earlier, that interrupt would go to
* hardclock, which would then fall over because p->p_stats
* isn't set at that time.
*/
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type != ST_DEC_21000)
tc_init(&i8254_timecounter);
platform.clockintr = hardclock;
if (mp_ncpus == 1) {
alpha_timecounter.tc_frequency = cycles_per_sec;
tc_init(&alpha_timecounter);
}
stathz = hz / 8;
profhz = hz;
/*
* Get the clock started.
*/
CLOCK_INIT(clockdev);
}
static __inline int get_8254_ctr(void);
static __inline int
get_8254_ctr(void)
{
int high, low;
mtx_lock_spin(&clock_lock);
/* Select timer0 and latch counter value. */
outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
low = inb(TIMER_CNTR0);
high = inb(TIMER_CNTR0);
mtx_unlock_spin(&clock_lock);
return ((high << 8) | low);
}
static void
calibrate_clocks(u_int32_t firmware_freq, u_int32_t *pcc, u_int32_t *timer)
{
u_int32_t start_pcc, stop_pcc;
u_int count, prev_count, tot_count;
int sec, start_sec;
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type == ST_DEC_21000) {
if (bootverbose)
printf("Using firmware default frequency of %u Hz\n",
firmware_freq);
*pcc = firmware_freq;
*timer = 0;
return;
}
if (bootverbose)
printf("Calibrating clock(s) ... ");
set_timer_freq(timer_freq, hz);
/* Read the mc146818A seconds counter. */
if (CLOCK_GETSECS(clockdev, &sec))
goto fail;
/* Wait for the mC146818A seconds counter to change. */
start_sec = sec;
for (;;) {
if (CLOCK_GETSECS(clockdev, &sec))
goto fail;
if (sec != start_sec)
break;
}
/* Start keeping track of the PCC and i8254. */
prev_count = get_8254_ctr();
if (prev_count == 0)
goto fail;
tot_count = 0;
start_pcc = alpha_rpcc();
/*
* Wait for the mc146818A seconds counter to change. Read the i8254
* counter for each iteration since this is convenient and only
* costs a few usec of inaccuracy. The timing of the final reads
* of the counters almost matches the timing of the initial reads,
* so the main cause of inaccuracy is the varying latency from
* inside get_8254_ctr() or rtcin(RTC_STATUSA) to the beginning of the
* rtcin(RTC_SEC) that returns a changed seconds count. The
* maximum inaccuracy from this cause is < 10 usec on 486's.
*/
start_sec = sec;
for (;;) {
if (CLOCK_GETSECS(clockdev, &sec))
goto fail;
count = get_8254_ctr();
if (count == 0)
goto fail;
if (count > prev_count)
tot_count += prev_count - (count - 0xffff);
else
tot_count += prev_count - count;
prev_count = count;
if (sec != start_sec)
break;
}
/*
* Read the PCC again to work out frequency.
*/
stop_pcc = alpha_rpcc();
if (bootverbose) {
printf("PCC clock: %u Hz (firmware %u Hz)\n",
stop_pcc - start_pcc, firmware_freq);
printf("i8254 clock: %u Hz\n", tot_count);
}
*pcc = stop_pcc - start_pcc;
*timer = tot_count;
return;
fail:
if (bootverbose)
printf("failed, using firmware default of %u Hz\n",
firmware_freq);
*pcc = firmware_freq;
*timer = 0;
return;
}
static void
set_timer_freq(u_int freq, int intr_freq)
{
mtx_lock_spin(&clock_lock);
timer_freq = freq;
i8254_timecounter.tc_frequency = timer_freq;
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(TIMER_CNTR0, 0);
outb(TIMER_CNTR0, 0);
mtx_unlock_spin(&clock_lock);
}
void
cpu_startprofclock(void)
{
/* nothing to do */
}
void
cpu_stopprofclock(void)
{
/* nothing to do */
}
/*
* This code is defunct after 2099.
* Will Unix still be here then??
*/
static short dayyr[12] = {
0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
};
/*
* Initialze the time of day register, based on the time base which is, e.g.
* from a filesystem. Base provides the time to within six months,
* and the time of year clock (if any) provides the rest.
*/
void
inittodr(time_t base)
{
struct clocktime ct;
struct timespec ts;
int clock_compat_osf1, todr_unreliable;
int days, yr;
if (getenv_int("clock_compat_osf1", &clock_compat_osf1)) {
if (clock_compat_osf1)
clock_year_offset = UNIX_YEAR_OFFSET;
}
todr_unreliable = 0;
CLOCK_GET(clockdev, base, &ct);
#ifdef DEBUG
printf("readclock: %d/%d/%d/%d/%d/%d\n", ct.year, ct.mon, ct.day,
ct.hour, ct.min, ct.sec);
#endif
ct.year += clock_year_offset;
if (ct.year < 70)
ct.year += 100;
/* simple sanity checks */
if (ct.year < 70 || ct.mon < 1 || ct.mon > 12 || ct.day < 1 ||
ct.day > 31 || ct.hour > 23 || ct.min > 59 || ct.sec > 59) {
/*
* Believe the time in the filesystem for lack of
* anything better, resetting the TODR.
*/
ts.tv_sec = base;
printf("WARNING: preposterous real-time clock");
todr_unreliable = 1;
} else {
days = 0;
for (yr = 70; yr < ct.year; yr++)
days += LEAPYEAR(yr) ? 366 : 365;
days += dayyr[ct.mon - 1] + ct.day - 1;
if (LEAPYEAR(yr) && ct.mon > 2)
days++;
/* now have days since Jan 1, 1970; the rest is easy... */
ts.tv_sec = days * SECDAY + ct.hour * SECHOUR +
ct.min * SECMIN + ct.sec;
if (wall_cmos_clock)
ts.tv_sec += adjkerntz;
/*
* The time base comes from a saved time, whereas the real-
* time clock is supposed to represent the current time.
* It is logically not possible for a saved time to be
* larger than the current time, so if that happens, assume
* the real-time clock is off. Warn when the real-time
* clock is off by two or more days.
*/
if (ts.tv_sec < base) {
ts.tv_sec = base;
days = (base - ts.tv_sec) / (60L * 60L * 24L);
if (days >= 2) {
printf("WARNING: real-time clock lost %d days",
days);
todr_unreliable = 1;
}
}
}
ts.tv_nsec = 0;
tc_setclock(&ts);
clockinitted = 1;
if (todr_unreliable) {
printf(" -- CHECK AND RESET THE DATE!\n");
resettodr();
}
}
/*
* Reset the TODR based on the time value; used when the TODR
* has a preposterous value and also when the time is reset
* by the stime system call. Also called when the TODR goes past
* TODRZERO + 100*(SECYEAR+2*SECDAY) (e.g. on Jan 2 just after midnight)
* to wrap the TODR around.
*/
void
resettodr()
{
register int t, t2, s;
struct clocktime ct;
unsigned long tm;
if (disable_rtc_set)
return;
s = splclock();
tm = time_second;
splx(s);
if (!clockinitted)
return;
/* Calculate local time to put in RTC */
tm -= (wall_cmos_clock ? adjkerntz : 0);
/* compute the day of week. */
t2 = tm / SECDAY;
ct.dow = (t2 + 4) % 7; /* 1/1/1970 was thursday */
/* compute the year */
ct.year = 69;
t = t2; /* XXX ? */
while (t2 >= 0) { /* whittle off years */
t = t2;
ct.year++;
t2 -= LEAPYEAR(ct.year) ? 366 : 365;
}
/* t = month + day; separate */
t2 = LEAPYEAR(ct.year);
for (ct.mon = 1; ct.mon < 12; ct.mon++)
if (t < dayyr[ct.mon] + (t2 && ct.mon > 1))
break;
ct.day = t - dayyr[ct.mon - 1] + 1;
if (t2 && ct.mon > 2)
ct.day--;
/* the rest is easy */
t = tm % SECDAY;
ct.hour = t / SECHOUR;
t %= 3600;
ct.min = t / SECMIN;
ct.sec = t % SECMIN;
ct.year = (ct.year - clock_year_offset) % 100;
CLOCK_SET(clockdev, &ct);
}
static unsigned
i8254_get_timecount(struct timecounter *tc)
{
return (0xffff - get_8254_ctr());
}
static unsigned
alpha_get_timecount(struct timecounter* tc)
{
return alpha_rpcc();
}
/*
* The RPCC register actually consists of two halves. The lower half
* is a raw 32-bit counter that wraps. The upper half is defined in
* the Digital UNIX PAL as being a raw per-process cycle count mod 2^32
* that is updated on each call to swpctx. In order to produce a 64-bit
* counter, we just use the lower half and simulate the upper 32-bits.
* The architecture guarantees that there will always be at least one
* clock interrupt in between overlaps in the lower half, so as long as
* we call this function every clock interrupt we should not miss any
* overlaps.
*/
uint64_t
read_cycle_count(void)
{
unsigned pcc_cnt;
/* Assert a critical section? */
pcc_cnt = alpha_rpcc() & 0xffffffff;
if (pcc_cnt < PCPU_GET(last_pcc_cnt))
PCPU_SET(pcc_base, PCPU_GET(pcc_base) + 1);
PCPU_SET(last_pcc_cnt, pcc_cnt);
return (pcc_cnt | ((uint64_t)PCPU_GET(pcc_base) << 32));
}
int
acquire_timer2(int mode)
{
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type == ST_DEC_21000) {
return (0);
}
if (timer2_state != RELEASED)
return (-1);
timer2_state = ACQUIRED;
/*
* This access to the timer registers is as atomic as possible
* because it is a single instruction. We could do better if we
* knew the rate. Use of splclock() limits glitches to 10-100us,
* and this is probably good enough for timer2, so we aren't as
* careful with it as with timer0.
*/
outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
return (0);
}
int
release_timer2(void)
{
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type == ST_DEC_21000) {
return (0);
}
if (timer2_state != ACQUIRED)
return (-1);
timer2_state = RELEASED;
outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
return (0);
}
static void
sysbeepstop(void *chan)
{
ppi_spkr_off(); /* disable counter2 output to speaker */
timer_spkr_release();
beeping = 0;
}
int
sysbeep(int pitch, int period)
{
/*
* XXX: TurboLaser doesn't have an i8254 counter.
* XXX: A replacement is needed, and another method
* XXX: of determining this would be nice.
*/
if (hwrpb->rpb_type == ST_DEC_21000) {
return (0);
}
mtx_lock_spin(&clock_lock);
if (timer_spkr_acquire())
if (!beeping) {
/* Something else owns it. */
mtx_unlock_spin(&clock_lock);
return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
}
if (pitch) pitch = TIMER_DIV(pitch);
spkr_set_pitch(pitch);
mtx_unlock_spin(&clock_lock);
if (!beeping) {
/* enable counter2 output to speaker */
if (pitch) ppi_spkr_on();
beeping = period;
timeout(sysbeepstop, (void *)NULL, period);
}
return (0);
}

52
sys/alpha/alpha/clock_if.m
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@ -1,52 +0,0 @@
#-
# Copyright (c) 1998 Doug Rabson
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $FreeBSD$
#
#include <sys/bus.h>
#include <machine/clockvar.h>
INTERFACE clock;
METHOD void init {
device_t dev;
};
METHOD void get {
device_t dev;
time_t base;
struct clocktime *ct;
};
METHOD void set {
device_t dev;
struct clocktime *ct;
};
METHOD int getsecs {
device_t dev;
int *secp;
};

230
sys/alpha/alpha/cpuconf.c
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@ -1,230 +0,0 @@
/*-
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $NetBSD: cpuconf.c,v 1.10 1998/03/20 21:48:21 thorpej Exp $
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_cpu.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#ifdef DEC_AXPPCI_33
extern void dec_axppci_33_init(int);
#else
#define dec_axppci_33_init platform_not_configured
#endif
#ifdef DEC_KN8AE
extern void dec_kn8ae_init(int);
#else
#define dec_kn8ae_init platform_not_configured
#endif
#ifdef DEC_2100_A50
extern void dec_2100_a50_init(int);
#else
#define dec_2100_a50_init platform_not_configured
#endif
#ifdef DEC_KN20AA
extern void dec_kn20aa_init(int);
#else
#define dec_kn20aa_init platform_not_configured
#endif
#ifdef DEC_EB64PLUS
extern void dec_eb64plus_init(int);
#else
#define dec_eb64plus_init platform_not_configured
#endif
#ifdef DEC_EB164
extern void dec_eb164_init(int);
#else
#define dec_eb164_init platform_not_configured
#endif
#ifdef DEC_KN300
extern void dec_kn300_init(int);
#else
#define dec_kn300_init platform_not_configured
#endif
#ifdef AVALON_A12
extern void avalon_a12_init(int);
#else
#define avalon_a12_init platform_not_configured
#endif
#ifdef DEC_ST550
extern void st550_init(int);
#else
#define st550_init platform_not_configured
#endif
#ifdef DEC_ST6600
extern void st6600_init(int);
#else
#define st6600_init platform_not_configured
#endif
#ifdef DEC_1000A
extern void dec_1000a_init(int);
#else
#define dec_1000a_init platform_not_configured
#endif
#ifdef DEC_2100_A500
extern void dec_2100_a500_init(int);
#else
#define dec_2100_a500_init platform_not_configured
#endif
#ifdef API_UP1000
extern void api_up1000_init(int);
#else
#define api_up1000_init platform_not_configured
#endif
struct cpuinit cpuinit[] = {
cpu_notsupp("???"), /* 0: ??? */
cpu_notsupp("ST_ADU"), /* 1: ADU */
cpu_notsupp("ST_DEC_4000"), /* 2: Cobra */
cpu_notsupp("ST_DEC_7000"), /* 3: Ruby */
cpu_notsupp("DEC_3000_500"), /* 4: Flamingo */
cpu_notsupp("???"), /* 5: simulator */
cpu_notsupp("ST_DEC_2000_300"), /* 6: Jensen */
cpu_notsupp("DEC_3000_300"), /* 7: Pelican */
cpu_init(avalon_a12_init,"ST_AVALON_A12"), /* 8: AVALON */
cpu_init(dec_2100_a500_init, "ST_DEC_2100_A500"), /* 9: Sable */
cpu_notsupp("ST_DEC_APXVME_64"), /* 10: AXPvme */
cpu_init(dec_axppci_33_init,"DEC_AXPPCI_33"), /* 11: NoName */
cpu_init(dec_kn8ae_init,"DEC_KN8AE"), /* 12: Turbolaser */
cpu_init(dec_2100_a50_init,"DEC_2100_A50"), /* 13: Avanti */
cpu_notsupp("ST_DEC_MUSTANG"), /* 14: Mustang */
cpu_init(dec_kn20aa_init,"DEC_KN20AA"), /* 15: Alcor */
cpu_notsupp("cancelled"), /* 16: cancelled */
cpu_init(dec_1000a_init, "ST_DEC_1000"), /* 17: Mikasa */
cpu_notsupp("ST_DEC_EB64"), /* 18: EB64 */
cpu_notsupp("ST_EB66"), /* 19: EB66 */
cpu_init(dec_eb64plus_init,"DEC_EB64PLUS"), /* 20: EB64+ */
cpu_notsupp("ST_ALPHABOOK1"), /* 21: AlphaBook */
cpu_init(dec_kn300_init,"DEC_KN300"), /* 22: Rawhide */
cpu_notsupp("ST_DEC_EV45_PBP"), /* 23: K2 */
cpu_init(dec_2100_a500_init, "ST_DEC_2100A_A500"), /* 24: Lynx */
cpu_notsupp("ST_DEC_ALPHAXL"), /* 25: AlphaXL */
cpu_init(dec_eb164_init,"DEC_EB164"), /* 26: EB164 */
cpu_init(dec_1000a_init,"ST_DEC_1000A"), /* 27: Noritake */
cpu_notsupp("ST_DEC_ALPHAVME_224"), /* 28: Cortex */
cpu_notsupp("unused"), /* 29: unused */
cpu_init(st550_init,"DEC_ST550"), /* 30: Miata */
cpu_notsupp("ST_DEC_XXM"), /* 31: XXM */
cpu_notsupp("ST_DEC_EV56_PBP"), /* 32: Takara */
cpu_notsupp("ST_DEC_ALPHAVME_320"), /* 33: Yukon */
cpu_init(st6600_init, "ST_DEC_ST6600"), /* 34: Tsunami */
cpu_notsupp("ST_DEC_WILDFIRE"), /* 35: Wildfire */
cpu_notsupp("ST_DEC_CUSCO"), /* 36: Cusco */
cpu_notsupp("ST_DEC_EIGER"), /* 37: Eiger */
cpu_notsupp("ST_DEC_TITAN"), /* 38: Titan */
cpu_notsupp("ST_DEC_MARVEL") /* 39: Marvel */
};
int ncpuinit = (sizeof(cpuinit) / sizeof(cpuinit[0]));
struct cpuinit api_cpuinit[] = {
cpu_notsupp("???"), /* 0: ??? */
cpu_init(api_up1000_init,"API_UP1000"), /* 1: ST_API_UP1000 */
};
int napi_cpuinit = (sizeof(api_cpuinit) / sizeof(api_cpuinit[0]));
void setPQL2(int *const size, int *const ways);
void
setPQL2(int *const size, int *const ways)
{
return;
}
void
platform_not_configured(int cputype)
{
struct cpuinit *cpu;
int cpuidx;
cputype = hwrpb->rpb_type;
if (cputype < 1)
cputype *= -1;
if (cputype >= API_ST_BASE) {
cpuidx = cputype - API_ST_BASE;
cpu = api_cpuinit;
} else {
cpuidx = cputype;
cpu = cpuinit;
}
printf("\n");
printf("Support for system type %d is not present in this kernel.\n",
cputype);
printf("Please build a kernel with \"options %s\" and reboot.\n",
cpu[cpuidx].option);
printf("\n");
panic("platform not configured\n");
}
void
platform_not_supported(int cputype)
{
const char *typestr;
cputype = hwrpb->rpb_type;
if (cputype < 1)
cputype *= -1;
if (cputype >= ncpuinit)
typestr = "???";
else
typestr = cpuinit[cputype].option;
printf("\n");
printf("FreeBSD does not yet support system type %d (%s).\n", cputype,
typestr);
printf("\n");
panic("platform not supported");
}

1089
sys/alpha/alpha/db_disasm.c
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File diff suppressed because it is too large Load Diff

700
sys/alpha/alpha/db_instruction.h
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@ -1,700 +0,0 @@
/* $NetBSD: db_instruction.h,v 1.4 1997/09/16 22:53:32 thorpej Exp $ */
/*-
* Mach Operating System
* Copyright (c) 1993,1992 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*
* $FreeBSD$
*/
/*
* File: alpha_instruction.h
* Author: Alessandro Forin, Carnegie Mellon University
* Date: 11/91
*
* Alpha Instruction set definition
*
* Reference: "Alpha System Reference Manual", V4.0, April 1991
*
*/
#ifndef _ALPHA_INSTRUCTION_H_
#define _ALPHA_INSTRUCTION_H_ 1
#if !defined(ASSEMBLER)
/*
* All instructions are in one of five formats:
* Memory, Branch, Operate, Floating-point Operate, PAL
*
* One minor departure from DEC's conventions is we use names
* for registers that are more akin their software use, e.g.
* rather then bluntly call them Ra/Rb/Rc we make clear which
* one is a source (Rs) and which one is a destination (Rd).
* When a second source register is defined we call it Rt.
*/
typedef union {
/*
* All instructions are 32 bits wide
*/
unsigned int bits;
/*
* Generic instruction pseudo format; look at
* opcode to see how to interpret the rest.
*/
struct {
unsigned bits : 26,
opcode : 6;
} generic_format;
/*
* Memory instructions contain a 16 bit
* signed immediate value and two register
* specifiers
*/
struct {
signed short displacement;
unsigned rs : 5,
rd : 5,
opcode : 6;
} mem_format;
/*
* Branch instruction contain a 21 bit offset,
* which is sign-extended, shifted and combined
* with the PC to form a 64 bit destination address.
*
* In computed jump instructions the opcode is further
* specified in the offset field, the rest of it is
* used as branch target hint. The destination of the
* jump is the source register.
*/
struct {
signed int displacement : 21;
unsigned rd : 5,
opcode : 6;
} branch_format;
struct {
signed int hint : 14;
unsigned action : 2,
rs : 5,
rd : 5,
opcode : 6;
} jump_format;
struct {
signed int offset : 16;
unsigned rb : 5;
unsigned ra : 5;
unsigned opcode : 6;
} memory_format;
/*
* Operate instructions are of two types, with
* a second source register or with a literal
* specifier. Bit 12 sez which is which.
*/
struct {
unsigned rc : 5,
function : 7,
is_lit : 1,
sbz_or_litlo : 3,
rb_or_lithi : 5,
ra : 5,
opcode : 6;
} operate_generic_format;
struct {
unsigned rd : 5,
function : 7,
sbz : 4,
rt : 5,
rs : 5,
opcode : 6;
} operate_reg_format;
struct {
unsigned rd : 5,
function : 7,
one : 1,
literal : 8,
rs : 5,
opcode : 6;
} operate_lit_format;
/*
* Floating point operate instruction are quite
* uniform in the encoding. As for the semantics..
*/
struct {
unsigned fd : 5,
function : 11,
ft : 5,
fs : 5,
opcode : 6;
} float_format;
/*
* PAL instructions just define the major opcode
*/
struct {
unsigned function : 26,
opcode : 6;
} pal_format;
} alpha_instruction;
#endif /* !defined(ASSEMBLER) */
/*
*
* Encoding of regular instructions (Appendix C op cit)
*
*/
/* OPCODE, bits 26..31 */
#define op_pal 0x00 /* see PAL sub-table */
/* 1..7 reserved */
#define op_lda 0x08
#define op_ldah 0x09
#define op_ldbu 0x0a
#define op_ldq_u 0x0b
#define op_ldwu 0x0c
#define op_stw 0x0d
#define op_stb 0x0e
#define op_stq_u 0x0f
#define op_arit 0x10 /* see ARIT sub-table */
#define op_logical 0x11 /* see LOGICAL sub-table */
#define op_bit 0x12 /* see BIT sub-table */
#define op_mul 0x13 /* see MUL sub-table */
/* reserved */
#define op_vax_float 0x15 /* see FLOAT sub-table */
#define op_ieee_float 0x16 /* see FLOAT sub-table */
#define op_any_float 0x17 /* see FLOAT sub-table */
#define op_special 0x18 /* see SPECIAL sub-table */
#define op_pal19 0x19 /* reserved for pal code */
#define op_j 0x1a /* see JUMP sub-table */
#define op_pal1b 0x1b /* reserved for pal code */
#define op_intmisc 0x1c /* see INTMISC sub-table */
#define op_pal1d 0x1d /* reserved for pal code */
#define op_pal1e 0x1e /* reserved for pal code */
#define op_pal1f 0x1f /* reserved for pal code */
#define op_ldf 0x20
#define op_ldg 0x21
#define op_lds 0x22
#define op_ldt 0x23
#define op_stf 0x24
#define op_stg 0x25
#define op_sts 0x26
#define op_stt 0x27
#define op_ldl 0x28
#define op_ldq 0x29
#define op_ldl_l 0x2a
#define op_ldq_l 0x2b
#define op_stl 0x2c
#define op_stq 0x2d
#define op_stl_c 0x2e
#define op_stq_c 0x2f
#define op_br 0x30
#define op_fbeq 0x31
#define op_fblt 0x32
#define op_fble 0x33
#define op_bsr 0x34
#define op_fbne 0x35
#define op_fbge 0x36
#define op_fbgt 0x37
#define op_blbc 0x38
#define op_beq 0x39
#define op_blt 0x3a
#define op_ble 0x3b
#define op_blbs 0x3c
#define op_bne 0x3d
#define op_bge 0x3e
#define op_bgt 0x3f
/* PAL, "function" opcodes (bits 0..25) */
/*
* What we will implement is TBD. These are the unprivileged ones
* that we probably have to support for compat reasons.
*/
/* See <machine/pal.h> */
/* ARIT, "function" opcodes (bits 5..11) */
#define op_addl 0x00
#define op_s4addl 0x02
#define op_subl 0x09
#define op_s4subl 0x0b
#define op_cmpbge 0x0f
#define op_s8addl 0x12
#define op_s8subl 0x1b
#define op_cmpult 0x1d
#define op_addq 0x20
#define op_s4addq 0x22
#define op_subq 0x29
#define op_s4subq 0x2b
#define op_cmpeq 0x2d
#define op_s8addq 0x32
#define op_s8subq 0x3b
#define op_cmpule 0x3d
#define op_addl_v 0x40
#define op_subl_v 0x49
#define op_cmplt 0x4d
#define op_addq_v 0x60
#define op_subq_v 0x69
#define op_cmple 0x6d
/* LOGICAL, "function" opcodes (bits 5..11) */
#define op_and 0x00
#define op_andnot 0x08 /* bic */
#define op_cmovlbs 0x14
#define op_cmovlbc 0x16
#define op_or 0x20 /* bis */
#define op_cmoveq 0x24
#define op_cmovne 0x26
#define op_ornot 0x28
#define op_xor 0x40
#define op_cmovlt 0x44
#define op_cmovge 0x46
#define op_xornot 0x48 /* eqv */
#define op_amask 0x61
#define op_cmovle 0x64
#define op_cmovgt 0x66
#define op_implver 0x6c
/* BIT, "function" opcodes (bits 5..11) */
#define op_mskbl 0x02
#define op_extbl 0x06
#define op_insbl 0x0b
#define op_mskwl 0x12
#define op_extwl 0x16
#define op_inswl 0x1b
#define op_mskll 0x22
#define op_extll 0x26
#define op_insll 0x2b
#define op_zap 0x30
#define op_zapnot 0x31
#define op_mskql 0x32
#define op_srl 0x34
#define op_extql 0x36
#define op_sll 0x39
#define op_insql 0x3b
#define op_sra 0x3c
#define op_mskwh 0x52
#define op_inswh 0x57
#define op_extwh 0x5a
#define op_msklh 0x62
#define op_inslh 0x67
#define op_extlh 0x6a
#define op_extqh 0x7a
#define op_insqh 0x77
#define op_mskqh 0x72
/* MUL, "function" opcodes (bits 5..11) */
#define op_mull 0x00
#define op_mulq_v 0x60
#define op_mull_v 0x40
#define op_umulh 0x30
#define op_mulq 0x20
/* SPECIAL, "displacement" opcodes (bits 0..15) */
#define op_draint 0x0000
#define op_mb 0x4000
#define op_fetch 0x8000
#define op_fetch_m 0xa000
#define op_rpcc 0xc000
#define op_rc 0xe000
#define op_rs 0xf000
/* JUMP, "action" opcodes (bits 14..15) */
#define op_jmp 0x0
#define op_jsr 0x1
#define op_ret 0x2
#define op_jcr 0x3
/* INTMISC, "function" opcodes (operate format) */
#define op_sextb 0x00
#define op_sextw 0x01
#define op_ctpop 0x30
#define op_perr 0x31
#define op_ctlz 0x32
#define op_cttz 0x33
#define op_unpkbw 0x34
#define op_unpkbl 0x35
#define op_pkwb 0x36
#define op_pklb 0x37
#define op_minsb8 0x38
#define op_minsw4 0x39
#define op_minub8 0x3a
#define op_minuw4 0x3b
#define op_maxub8 0x3c
#define op_maxuw4 0x3d
#define op_maxsb8 0x3e
#define op_maxsw4 0x3f
#define op_ftoit 0x70
#define op_ftois 0x78
/*
*
* Encoding of floating point instructions (pagg. C-5..6 op cit)
*
* Load and store operations use opcodes op_ldf..op_stt
*/
/* any FLOAT, "function" opcodes (bits 5..11) */
#define op_cvtlq 0x010
#define op_cpys 0x020
#define op_cpysn 0x021
#define op_cpyse 0x022
#define op_mt_fpcr 0x024
#define op_mf_fpcr 0x025
#define op_fcmoveq 0x02a
#define op_fcmovne 0x02b
#define op_fcmovlt 0x02c
#define op_fcmovge 0x02d
#define op_fcmovle 0x02e
#define op_fcmovgt 0x02f
#define op_cvtql 0x030
#define op_cvtql_v 0x130
#define op_cvtql_sv 0x330
/* ieee FLOAT, "function" opcodes (bits 5..11) */
#define op_adds_c 0x000
#define op_subs_c 0x001
#define op_muls_c 0x002
#define op_divs_c 0x003
#define op_addt_c 0x020
#define op_subt_c 0x021
#define op_mult_c 0x022
#define op_divt_c 0x023
#define op_cvtts_c 0x02c
#define op_cvttq_c 0x02f
#define op_cvtqs_c 0x03c
#define op_cvtqt_c 0x03e
#define op_adds_m 0x040
#define op_subs_m 0x041
#define op_muls_m 0x042
#define op_divs_m 0x043
#define op_addt_m 0x060
#define op_subt_m 0x061
#define op_mult_m 0x062
#define op_divt_m 0x063
#define op_cvtts_m 0x06c
#define op_cvtqs_m 0x07c
#define op_cvtqt_m 0x07e
#define op_adds 0x080
#define op_subs 0x081
#define op_muls 0x082
#define op_divs 0x083
#define op_addt 0x0a0
#define op_subt 0x0a1
#define op_mult 0x0a2
#define op_divt 0x0a3
#define op_cmptun 0x0a4
#define op_cmpteq 0x0a5
#define op_cmptlt 0x0a6
#define op_cmptle 0x0a7
#define op_cvtts 0x0ac
#define op_cvttq 0x0af
#define op_cvtqs 0x0bc
#define op_cvtqt 0x0be
#define op_adds_d 0x0c0
#define op_subs_d 0x0c1
#define op_muls_d 0x0c2
#define op_divs_d 0x0c3
#define op_addt_d 0x0e0
#define op_subt_d 0x0e1
#define op_mult_d 0x0e2
#define op_divt_d 0x0e3
#define op_cvtts_d 0x0ec
#define op_cvtqs_d 0x0fc
#define op_cvtqt_d 0x0fe
#define op_adds_uc 0x100
#define op_subs_uc 0x101
#define op_muls_uc 0x102
#define op_divs_uc 0x103
#define op_addt_uc 0x120
#define op_subt_uc 0x121
#define op_mult_uc 0x122
#define op_divt_uc 0x123
#define op_cvtts_uc 0x12c
#define op_cvttq_vc 0x12f
#define op_adds_um 0x140
#define op_subs_um 0x141
#define op_muls_um 0x142
#define op_divs_um 0x143
#define op_addt_um 0x160
#define op_subt_um 0x161
#define op_mult_um 0x162
#define op_divt_um 0x163
#define op_cvtts_um 0x16c
#define op_adds_u 0x180
#define op_subs_u 0x181
#define op_muls_u 0x182
#define op_divs_u 0x183
#define op_addt_u 0x1a0
#define op_subt_u 0x1a1
#define op_mult_u 0x1a2
#define op_divt_u 0x1a3
#define op_cvtts_u 0x1ac
#define op_cvttq_v 0x1af
#define op_adds_ud 0x1c0
#define op_subs_ud 0x1c1
#define op_muls_ud 0x1c2
#define op_divs_ud 0x1c3
#define op_addt_ud 0x1e0
#define op_subt_ud 0x1e1
#define op_mult_ud 0x1e2
#define op_divt_ud 0x1e3
#define op_cvtts_ud 0x1ec
#define op_adds_suc 0x500
#define op_subs_suc 0x501
#define op_muls_suc 0x502
#define op_divs_suc 0x503
#define op_addt_suc 0x520
#define op_subt_suc 0x521
#define op_mult_suc 0x522
#define op_divt_suc 0x523
#define op_cvtts_suc 0x52c
#define op_cvttq_svc 0x52f
#define op_adds_sum 0x540
#define op_subs_sum 0x541
#define op_muls_sum 0x542
#define op_divs_sum 0x543
#define op_addt_sum 0x560
#define op_subt_sum 0x561
#define op_mult_sum 0x562
#define op_divt_sum 0x563
#define op_cvtts_sum 0x56c
#define op_adds_su 0x580
#define op_subs_su 0x581
#define op_muls_su 0x582
#define op_divs_su 0x583
#define op_addt_su 0x5a0
#define op_subt_su 0x5a1
#define op_mult_su 0x5a2
#define op_divt_su 0x5a3
#define op_cmptun_su 0x5a4
#define op_cmpteq_su 0x5a5
#define op_cmptlt_su 0x5a6
#define op_cmptle_su 0x5a7
#define op_cvtts_su 0x5ac
#define op_cvttq_sv 0x5af
#define op_adds_sud 0x5c0
#define op_subs_sud 0x5c1
#define op_muls_sud 0x5c2
#define op_divs_sud 0x5c3
#define op_addt_sud 0x5e0
#define op_subt_sud 0x5e1
#define op_mult_sud 0x5e2
#define op_divt_sud 0x5e3
#define op_cvtts_sud 0x5ec
#define op_adds_suic 0x700
#define op_subs_suic 0x701
#define op_muls_suic 0x702
#define op_divs_suic 0x703
#define op_addt_suic 0x720
#define op_subt_suic 0x721
#define op_mult_suic 0x722
#define op_divt_suic 0x723
#define op_cvtts_suic 0x72c
#define op_cvttq_svic 0x72f
#define op_cvtqs_suic 0x73c
#define op_cvtqt_suic 0x73e
#define op_adds_suim 0x740
#define op_subs_suim 0x741
#define op_muls_suim 0x742
#define op_divs_suim 0x743
#define op_addt_suim 0x760
#define op_subt_suim 0x761
#define op_mult_suim 0x762
#define op_divt_suim 0x763
#define op_cvtts_suim 0x76c
#define op_cvtqs_suim 0x77c
#define op_cvtqt_suim 0x77e
#define op_adds_sui 0x780
#define op_subs_sui 0x781
#define op_muls_sui 0x782
#define op_divs_sui 0x783
#define op_addt_sui 0x7a0
#define op_subt_sui 0x7a1
#define op_mult_sui 0x7a2
#define op_divt_sui 0x7a3
#define op_cvtts_sui 0x7ac
#define op_cvttq_svi 0x7af
#define op_cvtqs_sui 0x7bc
#define op_cvtqt_sui 0x7be
#define op_adds_suid 0x7c0
#define op_subs_suid 0x7c1
#define op_muls_suid 0x7c2
#define op_divs_suid 0x7c3
#define op_addt_suid 0x7e0
#define op_subt_suid 0x7e1
#define op_mult_suid 0x7e2
#define op_divt_suid 0x7e3
#define op_cvtts_suid 0x7ec
#define op_cvtqs_suid 0x7fc
#define op_cvtqt_suid 0x7fe
/* vax FLOAT, "function" opcodes (bits 5..11) */
#define op_addf_c 0x000
#define op_subf_c 0x001
#define op_mulf_c 0x002
#define op_divf_c 0x003
#define op_cvtdg_c 0x01e
#define op_addg_c 0x020
#define op_subg_c 0x021
#define op_mulg_c 0x022
#define op_divg_c 0x023
#define op_cvtgf_c 0x02c
#define op_cvtgd_c 0x02d
#define op_cvtgqg_c 0x02f
#define op_cvtqf_c 0x03c
#define op_cvtqg_c 0x03e
#define op_addf 0x080
#define op_subf 0x081
#define op_mulf 0x082
#define op_divf 0x083
#define op_cvtdg 0x09e
#define op_addg 0x0a0
#define op_subg 0x0a1
#define op_mulg 0x0a2
#define op_divg 0x0a3
#define op_cmpgeq 0x0a5
#define op_cmpglt 0x0a6
#define op_cmpgle 0x0a7
#define op_cvtgf 0x0ac
#define op_cvtgd 0x0ad
#define op_cvtgq 0x0af
#define op_cvtqf 0x0bc
#define op_cvtqg 0x0be
#define op_addf_uc 0x100
#define op_subf_uc 0x101
#define op_mulf_uc 0x102
#define op_divf_uc 0x103
#define op_cvtdg_uc 0x11e
#define op_addg_uc 0x120
#define op_subg_uc 0x121
#define op_mulg_uc 0x122
#define op_divg_uc 0x123
#define op_cvtgf_uc 0x12c
#define op_cvtgd_uc 0x12d
#define op_cvtgqg_vc 0x12f
#define op_addf_u 0x180
#define op_subf_u 0x181
#define op_mulf_u 0x182
#define op_divf_u 0x183
#define op_cvtdg_u 0x19e
#define op_addg_u 0x1a0
#define op_subg_u 0x1a1
#define op_mulg_u 0x1a2
#define op_divg_u 0x1a3
#define op_cvtgf_u 0x1ac
#define op_cvtgd_u 0x1ad
#define op_cvtgqg_v 0x1af
#define op_addf_sc 0x400
#define op_subf_sc 0x401
#define op_mulf_sc 0x402
#define op_divf_sc 0x403
#define op_cvtdg_sc 0x41e
#define op_addg_sc 0x420
#define op_subg_sc 0x421
#define op_mulg_sc 0x422
#define op_divg_sc 0x423
#define op_cvtgf_sc 0x42c
#define op_cvtgd_sc 0x42d
#define op_cvtgqg_sc 0x42f
#define op_cvtqf_sc 0x43c
#define op_cvtqg_sc 0x43e
#define op_addf_s 0x480
#define op_subf_s 0x481
#define op_mulf_s 0x482
#define op_divf_s 0x483
#define op_cvtdg_s 0x49e
#define op_addg_s 0x4a0
#define op_subg_s 0x4a1
#define op_mulg_s 0x4a2
#define op_divg_s 0x4a3
#define op_cmpgeq_s 0x4a5
#define op_cmpglt_s 0x4a6
#define op_cmpgle_s 0x4a7
#define op_cvtgf_s 0x4ac
#define op_cvtgd_s 0x4ad
#define op_cvtgqg_s 0x4af
#define op_cvtqf_s 0x4bc
#define op_cvtqg_s 0x4be
#define op_addf_suc 0x500
#define op_subf_suc 0x501
#define op_mulf_suc 0x502
#define op_divf_suc 0x503
#define op_cvtdg_suc 0x51e
#define op_addg_suc 0x520
#define op_subg_suc 0x521
#define op_mulg_suc 0x522
#define op_divg_suc 0x523
#define op_cvtgf_suc 0x52c
#define op_cvtgd_suc 0x52d
#define op_cvtgqg_svc 0x52f
#define op_addf_su 0x580
#define op_subf_su 0x581
#define op_mulf_su 0x582
#define op_divf_su 0x583
#define op_cvtdg_su 0x59e
#define op_addg_su 0x5a0
#define op_subg_su 0x5a1
#define op_mulg_su 0x5a2
#define op_divg_su 0x5a3
#define op_cvtgf_su 0x5ac
#define op_cvtgd_su 0x5ad
#define op_cvtgqg_sv 0x5af
#endif /* _ALPHA_INSTRUCTION_H_ */

452
sys/alpha/alpha/db_interface.c
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@ -1,452 +0,0 @@
/*-
* Mach Operating System
* Copyright (c) 1992,1991,1990 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*
* db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
*/
/*
* Parts of this file are derived from Mach 3:
*
* File: alpha_instruction.c
* Author: Alessandro Forin, Carnegie Mellon University
* Date: 6/92
*/
/*
* Interface to DDB.
*
* Modified for NetBSD/alpha by:
*
* Christopher G. Demetriou, Carnegie Mellon University
*
* Jason R. Thorpe, Numerical Aerospace Simulation Facility,
* NASA Ames Research Center
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
/* __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.2 1997/09/16 19:07:19 thorpej Exp $"); */
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/kernel.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/smp.h>
#include <vm/vm.h>
#include <machine/db_machdep.h>
#include <machine/pal.h>
#include <machine/prom.h>
#include <alpha/alpha/db_instruction.h>
#include <ddb/ddb.h>
#include <ddb/db_access.h>
#include <ddb/db_sym.h>
#include <ddb/db_variables.h>
static db_varfcn_t db_frame;
struct db_variable db_regs[] = {
{ "v0", (db_expr_t *)FRAME_V0, db_frame },
{ "t0", (db_expr_t *)FRAME_T0, db_frame },
{ "t1", (db_expr_t *)FRAME_T1, db_frame },
{ "t2", (db_expr_t *)FRAME_T2, db_frame },
{ "t3", (db_expr_t *)FRAME_T3, db_frame },
{ "t4", (db_expr_t *)FRAME_T4, db_frame },
{ "t5", (db_expr_t *)FRAME_T5, db_frame },
{ "t6", (db_expr_t *)FRAME_T6, db_frame },
{ "t7", (db_expr_t *)FRAME_T7, db_frame },
{ "s0", (db_expr_t *)FRAME_S0, db_frame },
{ "s1", (db_expr_t *)FRAME_S1, db_frame },
{ "s2", (db_expr_t *)FRAME_S2, db_frame },
{ "s3", (db_expr_t *)FRAME_S3, db_frame },
{ "s4", (db_expr_t *)FRAME_S4, db_frame },
{ "s5", (db_expr_t *)FRAME_S5, db_frame },
{ "s6", (db_expr_t *)FRAME_S6, db_frame },
{ "a0", (db_expr_t *)FRAME_A0, db_frame },
{ "a1", (db_expr_t *)FRAME_A1, db_frame },
{ "a2", (db_expr_t *)FRAME_A2, db_frame },
{ "a3", (db_expr_t *)FRAME_A3, db_frame },
{ "a4", (db_expr_t *)FRAME_A4, db_frame },
{ "a5", (db_expr_t *)FRAME_A5, db_frame },
{ "t8", (db_expr_t *)FRAME_T8, db_frame },
{ "t9", (db_expr_t *)FRAME_T9, db_frame },
{ "t10", (db_expr_t *)FRAME_T10, db_frame },
{ "t11", (db_expr_t *)FRAME_T11, db_frame },
{ "ra", (db_expr_t *)FRAME_RA, db_frame },
{ "t12", (db_expr_t *)FRAME_T12, db_frame },
{ "at", (db_expr_t *)FRAME_AT, db_frame },
{ "gp", (db_expr_t *)FRAME_GP, db_frame },
{ "sp", (db_expr_t *)FRAME_SP, db_frame },
{ "pc", (db_expr_t *)FRAME_PC, db_frame },
{ "ps", (db_expr_t *)FRAME_PS, db_frame },
{ "ai", (db_expr_t *)FRAME_T11, db_frame },
{ "pv", (db_expr_t *)FRAME_T12, db_frame },
};
struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
static int
db_frame(struct db_variable *vp, db_expr_t *valuep, int op)
{
if (kdb_frame == NULL)
return (0);
if (op == DB_VAR_GET)
*valuep = kdb_frame->tf_regs[(uintptr_t)vp->valuep];
else
kdb_frame->tf_regs[(uintptr_t)vp->valuep] = *valuep;
return (1);
}
/*
* Read bytes from kernel address space for debugger.
*/
int
db_read_bytes(vm_offset_t addr, size_t size, char *data)
{
jmp_buf jb;
void *prev_jb;
char *src;
int ret;
prev_jb = kdb_jmpbuf(jb);
ret = setjmp(jb);
if (ret == 0) {
src = (char *)addr;
while (size-- > 0)
*data++ = *src++;
}
(void)kdb_jmpbuf(prev_jb);
return (ret);
}
/*
* Write bytes to kernel address space for debugger.
*/
int
db_write_bytes(vm_offset_t addr, size_t size, char *data)
{
jmp_buf jb;
void *prev_jb;
char *dst;
int ret;
prev_jb = kdb_jmpbuf(jb);
ret = setjmp(jb);
if (ret == 0) {
dst = (char *)addr;
while (size-- > 0)
*dst++ = *data++;
alpha_pal_imb();
}
(void)kdb_jmpbuf(prev_jb);
return (ret);
}
/*
* Alpha-specific ddb commands:
*
* halt set halt bit in rpb and halt
* reboot set reboot bit in rpb and halt
*/
DB_COMMAND(halt, db_mach_halt)
{
prom_halt(1);
}
DB_COMMAND(reboot, db_mach_reboot)
{
prom_halt(0);
}
/*
* Map Alpha register numbers to trapframe/db_regs_t offsets.
*/
static int reg_to_frame[32] = {
FRAME_V0,
FRAME_T0,
FRAME_T1,
FRAME_T2,
FRAME_T3,
FRAME_T4,
FRAME_T5,
FRAME_T6,
FRAME_T7,
FRAME_S0,
FRAME_S1,
FRAME_S2,
FRAME_S3,
FRAME_S4,
FRAME_S5,
FRAME_S6,
FRAME_A0,
FRAME_A1,
FRAME_A2,
FRAME_A3,
FRAME_A4,
FRAME_A5,
FRAME_T8,
FRAME_T9,
FRAME_T10,
FRAME_T11,
FRAME_RA,
FRAME_T12,
FRAME_AT,
FRAME_GP,
FRAME_SP,
-1, /* zero */
};
u_long
db_register_value(int regno)
{
if (regno > 31 || regno < 0) {
db_printf(" **** STRANGE REGISTER NUMBER %d **** ", regno);
return (0);
}
if (regno == 31)
return (0);
return (kdb_frame->tf_regs[reg_to_frame[regno]]);
}
/*
* Support functions for software single-step.
*/
boolean_t
db_inst_call(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
return ((insn.branch_format.opcode == op_bsr) ||
((insn.jump_format.opcode == op_j) &&
(insn.jump_format.action & 1)));
}
boolean_t
db_inst_return(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
return ((insn.jump_format.opcode == op_j) &&
(insn.jump_format.action == op_ret));
}
boolean_t
db_inst_trap_return(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
return ((insn.pal_format.opcode == op_pal) &&
(insn.pal_format.function == PAL_OSF1_rti));
}
boolean_t
db_inst_branch(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
switch (insn.branch_format.opcode) {
case op_j:
case op_br:
case op_fbeq:
case op_fblt:
case op_fble:
case op_fbne:
case op_fbge:
case op_fbgt:
case op_blbc:
case op_beq:
case op_blt:
case op_ble:
case op_blbs:
case op_bne:
case op_bge:
case op_bgt:
return (TRUE);
}
return (FALSE);
}
boolean_t
db_inst_unconditional_flow_transfer(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
switch (insn.branch_format.opcode) {
case op_j:
case op_br:
return (TRUE);
case op_pal:
switch (insn.pal_format.function) {
case PAL_OSF1_retsys:
case PAL_OSF1_rti:
case PAL_OSF1_callsys:
return (TRUE);
}
}
return (FALSE);
}
boolean_t
db_inst_load(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
/* Loads. */
if (insn.mem_format.opcode == op_ldbu ||
insn.mem_format.opcode == op_ldq_u ||
insn.mem_format.opcode == op_ldwu)
return (TRUE);
if ((insn.mem_format.opcode >= op_ldf) &&
(insn.mem_format.opcode <= op_ldt))
return (TRUE);
if ((insn.mem_format.opcode >= op_ldl) &&
(insn.mem_format.opcode <= op_ldq_l))
return (TRUE);
/* Prefetches. */
if (insn.mem_format.opcode == op_special) {
/* Note: MB is treated as a store. */
if ((insn.mem_format.displacement == (short)op_fetch) ||
(insn.mem_format.displacement == (short)op_fetch_m))
return (TRUE);
}
return (FALSE);
}
boolean_t
db_inst_store(ins)
int ins;
{
alpha_instruction insn;
insn.bits = ins;
/* Stores. */
if (insn.mem_format.opcode == op_stw ||
insn.mem_format.opcode == op_stb ||
insn.mem_format.opcode == op_stq_u)
return (TRUE);
if ((insn.mem_format.opcode >= op_stf) &&
(insn.mem_format.opcode <= op_stt))
return (TRUE);
if ((insn.mem_format.opcode >= op_stl) &&
(insn.mem_format.opcode <= op_stq_c))
return (TRUE);
/* Barriers. */
if (insn.mem_format.opcode == op_special) {
if (insn.mem_format.displacement == op_mb)
return (TRUE);
}
return (FALSE);
}
db_addr_t
db_branch_taken(int ins, db_addr_t pc)
{
alpha_instruction insn;
db_addr_t newpc;
insn.bits = ins;
switch (insn.branch_format.opcode) {
/*
* Jump format: target PC is (contents of instruction's "RB") & ~3.
*/
case op_j:
newpc = db_register_value(insn.jump_format.rs) & ~3;
break;
/*
* Branch format: target PC is
* (new PC) + (4 * sign-ext(displacement)).
*/
case op_br:
case op_fbeq:
case op_fblt:
case op_fble:
case op_bsr:
case op_fbne:
case op_fbge:
case op_fbgt:
case op_blbc:
case op_beq:
case op_blt:
case op_ble:
case op_blbs:
case op_bne:
case op_bge:
case op_bgt:
newpc = (insn.branch_format.displacement << 2) + (pc + 4);
break;
default:
printf("DDB: db_inst_branch_taken on non-branch!\n");
newpc = pc; /* XXX */
}
return (newpc);
}
void
db_show_mdpcpu(struct pcpu *pc)
{
db_printf("ipis = 0x%lx\n", pc->pc_pending_ipis);
db_printf("next ASN = %d\n", pc->pc_next_asn);
}

410
sys/alpha/alpha/db_trace.c
View File

@ -1,410 +0,0 @@
/* $NetBSD: db_trace.c,v 1.9 2000/12/13 03:16:36 mycroft Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Ross Harvey.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
/*__KERNEL_RCSID(0, "$NetBSD: db_trace.c,v 1.9 2000/12/13 03:16:36 mycroft Exp $");*/
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kdb.h>
#include <sys/linker.h>
#include <sys/proc.h>
#include <sys/stack.h>
#include <sys/sysent.h>
#include <machine/db_machdep.h>
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <ddb/ddb.h>
#include <ddb/db_sym.h>
#include <ddb/db_access.h>
#include <ddb/db_variables.h>
#include <ddb/db_output.h>
#include <alpha/alpha/db_instruction.h>
/*
* Information about the `standard' Alpha function prologue.
*/
struct prologue_info {
int pi_reg_offset[32]; /* offset of registers in stack frame */
u_int32_t pi_regmask; /* which registers are in frame */
int pi_frame_size; /* frame size */
};
/*
* We use several symbols to take special action:
*
* Trap vectors, which use a different (fixed-size) stack frame:
*
* XentArith
* XentIF
* XentInt
* XentMM
* XentSys
* XentUna
*/
static struct special_symbol {
uintptr_t ss_val;
const char *ss_note;
} special_symbols[] = {
{ (uintptr_t)&XentArith, "arithmetic trap" },
{ (uintptr_t)&XentIF, "instruction fault" },
{ (uintptr_t)&XentInt, "interrupt" },
{ (uintptr_t)&XentMM, "memory management fault" },
{ (uintptr_t)&XentSys, "syscall" },
{ (uintptr_t)&XentUna, "unaligned access fault" },
{ (uintptr_t)&XentRestart, "console restart" },
{ 0, NULL }
};
/*
* Decode the function prologue for the function we're in, and note
* which registers are stored where, and how large the stack frame is.
*/
static int
decode_prologue(db_addr_t callpc, db_addr_t func,
struct prologue_info *pi)
{
long signed_immediate;
alpha_instruction ins;
db_expr_t pc;
pi->pi_regmask = 0;
pi->pi_frame_size = 0;
#define CHECK_FRAMESIZE \
do { \
if (pi->pi_frame_size != 0) { \
db_printf("frame size botch: adjust register offsets?\n"); \
return (1); \
} \
} while (0)
for (pc = func; pc < callpc; pc += sizeof(alpha_instruction)) {
ins.bits = *(unsigned int *)pc;
if (ins.memory_format.opcode == op_lda &&
ins.memory_format.ra == 30 &&
ins.memory_format.rb == 30) {
/*
* GCC 2.7-style stack adjust:
*
* lda sp, -64(sp)
*/
signed_immediate = (long)ins.mem_format.displacement;
#if 1
if (signed_immediate > 0) {
db_printf("prologue botch: displacement %ld\n",
signed_immediate);
return (1);
}
#endif
CHECK_FRAMESIZE;
pi->pi_frame_size += -signed_immediate;
} else if (ins.operate_lit_format.opcode == op_arit &&
ins.operate_lit_format.function == op_subq &&
ins.operate_lit_format.rs == 30 &&
ins.operate_lit_format.rd == 30) {
/*
* EGCS-style stack adjust:
*
* subq sp, 64, sp
*/
CHECK_FRAMESIZE;
pi->pi_frame_size += ins.operate_lit_format.literal;
} else if (ins.mem_format.opcode == op_stq &&
ins.mem_format.rs == 30 &&
ins.mem_format.rd != 31) {
/* Store of (non-zero) register onto the stack. */
signed_immediate = (long)ins.mem_format.displacement;
pi->pi_regmask |= 1 << ins.mem_format.rd;
pi->pi_reg_offset[ins.mem_format.rd] = signed_immediate;
}
}
return (0);
}
static int
sym_is_trapsymbol(uintptr_t v)
{
int i;
for (i = 0; special_symbols[i].ss_val != 0; ++i)
if (v == special_symbols[i].ss_val)
return 1;
return 0;
}
static void
decode_syscall(int number, struct thread *td)
{
struct proc *p;
c_db_sym_t sym;
db_expr_t diff;
sy_call_t *f;
const char *symname;
p = (td != NULL) ? td->td_proc : NULL;
db_printf(" (%d", number);
if (p != NULL && 0 <= number && number < p->p_sysent->sv_size) {
f = p->p_sysent->sv_table[number].sy_call;
sym = db_search_symbol((db_addr_t)f, DB_STGY_ANY, &diff);
if (sym != DB_SYM_NULL && diff == 0) {
db_symbol_values(sym, &symname, NULL);
db_printf(", %s, %s", p->p_sysent->sv_name, symname);
}
}
db_printf(")");
}
static int
db_backtrace(struct thread *td, db_addr_t frame, db_addr_t pc, int count)
{
struct prologue_info pi;
struct trapframe *tf;
const char *symname;
c_db_sym_t sym;
db_expr_t diff;
db_addr_t symval;
u_long last_ipl, tfps;
int i, quit;
if (count == -1)
count = 1024;
last_ipl = ~0L;
tf = NULL;
quit = 0;
db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
while (count-- && !quit) {
sym = db_search_symbol(pc, DB_STGY_ANY, &diff);
if (sym == DB_SYM_NULL)
return (ENOENT);
db_symbol_values(sym, &symname, (db_expr_t *)&symval);
if (pc < symval) {
db_printf("symbol botch: pc 0x%lx < "
"func 0x%lx (%s)\n", pc, symval, symname);
return (0);
}
/*
* XXX Printing out arguments is Hard. We'd have to
* keep lots of state as we traverse the frame, figuring
* out where the arguments to the function are stored
* on the stack.
*
* Even worse, they may be stored to the stack _after_
* being modified in place; arguments are passed in
* registers.
*
* So, in order for this to work reliably, we pretty much
* have to have a kernel built with `cc -g':
*
* - The debugging symbols would tell us where the
* arguments are, how many there are, if there were
* any passed on the stack, etc.
*
* - Presumably, the compiler would be careful to
* store the argument registers on the stack before
* modifying the registers, so that a debugger could
* know what those values were upon procedure entry.
*
* Because of this, we don't bother. We've got most of the
* benefit of back tracking without the arguments, and we
* could get the arguments if we use a remote source-level
* debugger (for serious debugging).
*/
db_printf("%s() at ", symname);
db_printsym(pc, DB_STGY_PROC);
db_printf("\n");
/*
* If we are in a trap vector, frame points to a
* trapframe.
*/
if (sym_is_trapsymbol(symval)) {
tf = (struct trapframe *)frame;
for (i = 0; special_symbols[i].ss_val != 0; ++i)
if (symval == special_symbols[i].ss_val)
db_printf("--- %s",
special_symbols[i].ss_note);
tfps = tf->tf_regs[FRAME_PS];
if (symval == (uintptr_t)&XentSys)
decode_syscall(tf->tf_regs[FRAME_V0], td);
if ((tfps & ALPHA_PSL_IPL_MASK) != last_ipl) {
last_ipl = tfps & ALPHA_PSL_IPL_MASK;
if (symval != (uintptr_t)&XentSys)
db_printf(" (from ipl %ld)", last_ipl);
}
db_printf(" ---\n");
if (tfps & ALPHA_PSL_USERMODE) {
db_printf("--- user mode ---\n");
break; /* Terminate search. */
}
frame = (db_addr_t)(tf + 1);
pc = tf->tf_regs[FRAME_PC];
continue;
}
/*
* This is a bit trickier; we must decode the function
* prologue to find the saved RA.
*
* XXX How does this interact w/ alloca()?!
*/
if (decode_prologue(pc, symval, &pi))
return (0);
if ((pi.pi_regmask & (1 << 26)) == 0) {
/*
* No saved RA found. We might have RA from
* the trap frame, however (e.g trap occurred
* in a leaf call). If not, we've found the
* root of the call graph.
*/
if (tf)
pc = tf->tf_regs[FRAME_RA];
else {
db_printf("--- root of call graph ---\n");
break;
}
} else
pc = *(u_long *)(frame + pi.pi_reg_offset[26]);
frame += pi.pi_frame_size;
tf = NULL;
}
return (0);
}
void
db_trace_self(void)
{
register_t pc, sp;
__asm __volatile(
" mov $30,%0 \n"
" lda %1,1f \n"
"1:\n"
: "=r" (sp), "=r" (pc));
db_backtrace(curthread, sp, pc, -1);
}
int
db_trace_thread(struct thread *thr, int count)
{
struct pcb *ctx;
ctx = kdb_thr_ctx(thr);
return (db_backtrace(thr, ctx->pcb_hw.apcb_ksp, ctx->pcb_context[7],
count));
}
void
stack_save(struct stack *st)
{
struct prologue_info pi;
linker_symval_t symval;
c_linker_sym_t sym;
vm_offset_t callpc, frame;
long offset;
register_t pc, sp;
stack_zero(st);
__asm __volatile(
" mov $30,%0 \n"
" lda %1,1f \n"
"1:\n"
: "=r" (sp), "=r" (pc));
callpc = (vm_offset_t)pc;
frame = (vm_offset_t)sp;
while (1) {
/*
* search_symbol/symbol_values are slow
*/
if (linker_ddb_search_symbol((caddr_t)callpc, &sym, &offset) != 0)
break;
if (linker_ddb_symbol_values(sym, &symval) != 0)
break;
if (callpc < (vm_offset_t)symval.value)
break;
if (stack_put(st, callpc) == -1)
break;
if (decode_prologue(callpc, (db_addr_t)symval.value, &pi))
break;
if ((pi.pi_regmask & (1 << 26)) == 0)
break;
callpc = *(vm_offset_t *)(frame + pi.pi_reg_offset[26]);
frame += pi.pi_frame_size;
}
}
int
db_md_set_watchpoint(addr, size)
db_expr_t addr;
db_expr_t size;
{
return (-1);
}
int
db_md_clr_watchpoint(addr, size)
db_expr_t addr;
db_expr_t size;
{
return (-1);
}
void
db_md_list_watchpoints()
{
return;
}

366
sys/alpha/alpha/dec_1000a.c
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@ -1,366 +0,0 @@
/* $NetBSD: dec_1000a.c,v 1.5 1999/04/15 22:06:47 thorpej Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is based on dec_kn20aa.c, written by Chris G. Demetriou at
* Carnegie-Mellon University. Platform support for Noritake, Pintake, and
* Corelle by Ross Harvey with copyright assignment by permission of Avalon
* Computer Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
/*-
* Additional Copyright (c) 1999 by Andrew Gallatin
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <alpha/pci/apecsvar.h>
#include <alpha/pci/ciavar.h>
#include <dev/pci/pcivar.h>
void dec_1000a_init(int);
static void dec_1000a_cons_init(void);
static void dec_1000_intr_map(void *);
static void dec_1000_intr_disable(int);
static void dec_1000_intr_enable(int);
static void dec_1000_intr_init(void);
static void dec_1000a_intr_map(void *);
static void dec_1000a_intr_disable(int);
static void dec_1000a_intr_enable(int);
static void dec_1000a_intr_init(void);
static const struct alpha_variation_table dec_1000_variations[] = {
{ 0, "AlphaServer 1000" },
{ 0, NULL },
};
static const struct alpha_variation_table dec_1000a_variations[] = {
{ 0, "AlphaServer 1000A" },
{ 0, NULL },
};
void
dec_1000a_init(int cputype)
{
u_int64_t variation;
platform.family = "AlphaServer 1000/1000A";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
cputype == ST_DEC_1000 ? dec_1000_variations
: dec_1000a_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
switch(LOCATE_PCS(hwrpb, 0)->pcs_proc_type & PCS_PROC_MAJOR) {
case PCS_PROC_EV4:
case PCS_PROC_EV45:
platform.iobus = "apecs";
break;
default:
platform.iobus = "cia";
break;
}
platform.cons_init = dec_1000a_cons_init;
switch (cputype) {
case ST_DEC_1000:
platform.pci_intr_map = dec_1000_intr_map;
platform.pci_intr_disable = dec_1000_intr_disable;
platform.pci_intr_enable = dec_1000_intr_enable;
platform.pci_intr_init = dec_1000_intr_init;
break;
default:
platform.pci_intr_map = dec_1000a_intr_map;
platform.pci_intr_disable = dec_1000a_intr_disable;
platform.pci_intr_enable = dec_1000a_intr_enable;
platform.pci_intr_init = dec_1000a_intr_init;
break;
}
}
static void
dec_1000a_cons_init()
{
struct ctb *ctb;
if(strcmp(platform.iobus, "cia") == 0) {
cia_init();
} else {
apecs_init();
}
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %d\n",
(int)ctb->ctb_term_type);
}
}
static void
dec_1000_intr_map(arg)
void *arg;
{
pcicfgregs *cfg;
cfg = (pcicfgregs *)arg;
if (cfg->intpin == 0) /* No IRQ used. */
return;
if (!(1 <= cfg->intpin && cfg->intpin <= 4))
goto bad;
switch(cfg->slot) {
case 6:
if(cfg->intpin != 1)
break;
cfg->intline = 0xc; /* integrated ncr scsi */
return;
break;
case 11:
case 12:
case 13:
cfg->intline = (cfg->slot - 11) * 4 + cfg->intpin - 1;
return;
break;
}
bad: printf("dec_1000_intr_map: can't map dev %d pin %d\n",
cfg->slot, cfg->intpin);
}
/*
* Read and write the mystery ICU IMR registers
* on the AlphaServer 1000.
*/
#define IR() inw(0x536)
#define IW(x) outw(0x536, (x))
/*
* Enable and disable interrupts at the ICU level.
*/
static void
dec_1000_intr_enable(irq)
int irq;
{
IW(IR() | 1 << irq);
}
static void
dec_1000_intr_disable(irq)
int irq;
{
IW(IR() & ~(1 << irq));
}
static void
dec_1000_intr_init()
{
/*
* Initialize mystery ICU.
*/
IW(0); /* XXX ?? */
/*
* Enable cascade interrupt.
*/
dec_1000_intr_enable(2);
}
/*
* Read and write the mystery ICU IMR registers
* on the AlphaServer 1000a.
*/
#define IRA(o) inw(0x54a + 2*(o))
#define IWA(o, v) outw(0x54a + 2*(o), (v))
#define IMR2IRQ(bn) ((bn) - 1)
#define IRQ2IMR(irq) ((irq) + 1)
static void
dec_1000a_intr_map(arg)
void *arg;
{
pcicfgregs *cfg;
int device, imrbit;
/*
* Get bit number in mystery ICU imr.
*/
static const signed char imrmap[][4] = {
# define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 }
# define IRQNONE { 0, 0, 0, 0 }
/* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */
/* 1 */ IRQSPLIT(8),
/* 2 */ IRQSPLIT(10),
/* 3 */ IRQSPLIT(12),
/* 4 */ IRQSPLIT(14),
/* 5 */ { 1, 0, 0, 0 }, /* Corelle */
/* 6 */ { 10, 0, 0, 0 }, /* Corelle */
/* 7 */ IRQNONE,
/* 8 */ { 1, 0, 0, 0 }, /* isp behind ppb */
/* 9 */ IRQNONE,
/* 10 */ IRQNONE,
/* 11 */ IRQSPLIT(2),
/* 12 */ IRQSPLIT(4),
/* 13 */ IRQSPLIT(6),
/* 14 */ IRQSPLIT(8) /* Corelle */
};
cfg = (pcicfgregs *)arg;
device = cfg->slot;
if (cfg->intpin == 0) /* No IRQ used. */
return;
if (!(1 <= cfg->intpin && cfg->intpin <= 4))
goto bad;
if (0 <= device && device < sizeof imrmap / sizeof imrmap[0]) {
imrbit = imrmap[device][cfg->intpin - 1];
if (imrbit) {
cfg->intline = IMR2IRQ(imrbit);
return;
}
}
bad: printf("dec_1000a_intr_map: can't map dev %d pin %d\n",
device, cfg->intpin);
}
static void
dec_1000a_intr_enable(irq)
int irq;
{
int imrval, i;
imrval = IRQ2IMR(irq);
i = imrval >= 16;
IWA(i, IRA(i) | 1 << (imrval & 0xf));
}
static void
dec_1000a_intr_disable(irq)
int irq;
{
int imrval, i;
imrval = IRQ2IMR(irq);
i = imrval >= 16;
IWA(i, IRA(i) & ~(1 << (imrval & 0xf)));
}
static void
dec_1000a_intr_init()
{
/*
* Initialize mystery ICU.
*/
IWA(0, IRA(0) & 1);
IWA(1, IRA(0) & 3);
/*
* Enable cascade interrupt.
*/
dec_1000a_intr_enable(2);
}

217
sys/alpha/alpha/dec_2100_a50.c
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@ -1,217 +0,0 @@
/* $NetBSD: dec_2100_a50.c,v 1.39 1998/04/17 02:45:19 mjacob Exp $ */
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
/*-
* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/apecsvar.h>
void dec_2100_a50_init(void);
static void dec_2100_a50_cons_init(void);
static void dec_2100_a50_intr_map(void *);
const struct alpha_variation_table dec_2100_a50_variations[] = {
{ SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" },
{ SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" },
{ SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" },
{ SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" },
{ SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" },
{ SV_ST_AVANTI_4_233, "AlphaStation 255/233" },
{ 0, NULL },
};
void
dec_2100_a50_init()
{
u_int64_t variation;
platform.family = "AlphaStation 200/400 (\"Avanti\")";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if (variation == SV_ST_AVANTI_XXX) {
/* XXX apparently the same? */
variation = SV_ST_AVANTI;
}
if ((platform.model = alpha_variation_name(variation,
dec_2100_a50_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "apecs";
platform.cons_init = dec_2100_a50_cons_init;
platform.pci_intr_map = dec_2100_a50_intr_map;
}
static void
dec_2100_a50_cons_init()
{
struct ctb *ctb;
apecs_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %ld\n",
ctb->ctb_term_type);
}
}
#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */
void
dec_2100_a50_intr_map(void *arg)
{
u_int8_t pirqline;
u_int32_t pirqreg;
int pirq;
pcicfgregs *cfg;
pirq = 0; /* gcc -Wuninitialized XXX */
cfg = (pcicfgregs *)arg;
/*
* Slot->interrupt translation. Taken from NetBSD.
*/
if(cfg->intpin == 0)
return;
if(cfg->intpin > 4)
panic("dec_2100_a50_intr_map: bad intpin %d",cfg->intpin);
switch (cfg->slot) {
case 6: /* NCR SCSI */
pirq = 3;
break;
case 11: /* slot 1 */
case 14: /* slot 3 */
switch(cfg->intpin) {
case 1:
case 4:
pirq = 0;
break;
case 2:
pirq = 2;
break;
case 3:
pirq = 1;
break;
default:
panic("dec_2100_a50_intr_map: bogus PCI pin %d\n",
cfg->intpin);
}
break;
case 12: /* slot 2 */
switch (cfg->intpin) {
case 1:
case 4:
pirq = 1;
break;
case 2:
pirq = 0;
break;
case 3:
pirq = 2;
break;
default:
panic("dec_2100_a50_intr_map: bogus PCI pin %d\n",
cfg->intpin);
};
break;
case 13: /* slot 3 */
switch (cfg->intpin) {
case 1:
case 4:
pirq = 2;
break;
case 2:
pirq = 1;
break;
case 3:
pirq = 0;
break;
};
break;
default:
printf("dec_2100_a50_intr_map: weird slot %d\n",
cfg->slot);
/* return; */
}
/*
* Read the SIO IRQ routing register to determine where the
* interrupt will actually be routed. Thank you, NetBSD.
*/
pirqreg = apecs_pcib_read_config(0, 0, 7, 0,
SIO_PCIREG_PIRQ_RTCTRL, 4);
pirqline = (pirqreg >> (pirq * 8)) & 0xff;
if ((pirqline & 0x80) != 0)
panic("bad pirqline %d",pirqline);
pirqline &= 0xf;
cfg->intline = pirqline;
}

115
sys/alpha/alpha/dec_2100_a500.c
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@ -1,115 +0,0 @@
/*-
* Copyright (c) 2000 Andrew Gallatin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/t2var.h>
#include <alpha/pci/t2reg.h>
void dec_2100_a500_init(int);
static void dec_2100_a500_cons_init(void);
static void dec_2100_a500_intr_init(void);
void
dec_2100_a500_init(int cputype)
{
/*
* See if we're a `Sable' or a `Lynx'.
*/
if (cputype == ST_DEC_2100_A500) {
if (alpha_implver() == ALPHA_IMPLVER_EV5)
sable_lynx_base = LYNX_BASE;
else
sable_lynx_base = SABLE_BASE;
platform.family = "DEC AlphaServer 2100";
} else if (cputype == ST_DEC_2100A_A500) {
sable_lynx_base = LYNX_BASE;
platform.family = "DEC AlphaServer 2100A";
} else {
sable_lynx_base = SABLE_BASE;
platform.family = "DEC AlphaServer 2100?????";
}
if ((platform.model = alpha_dsr_sysname()) == NULL) {
platform.model = alpha_unknown_sysname();
}
platform.iobus = "t2";
platform.cons_init = dec_2100_a500_cons_init;
platform.pci_intr_init = dec_2100_a500_intr_init;
t2_init();
}
static void
dec_2100_a500_cons_init()
{
struct ctb *ctb;
t2_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
panic("consinit: unknown console type");
}
}
void
dec_2100_a500_intr_init(void)
{
outb(SLAVE0_ICU, 0);
outb(SLAVE1_ICU, 0);
outb(SLAVE2_ICU, 0);
outb(MASTER_ICU, 0x44);
}

87
sys/alpha/alpha/dec_3000_300.c
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@ -1,87 +0,0 @@
/*-
* Copyright (c) 1997 by Matthew Jacob
* NASA AMES Research Center.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_cpu.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <alpha/tlsb/tlsbreg.h>
#include <alpha/tlsb/gbusreg.h>
#include <alpha/tlsb/zsvar.h>
void dec_3000_300_init(int);
static void dec_3000_300_cons_init(void);
static const struct alpha_variation_table dec_3000_300_variations[] = {
{ SV_ST_PELICAN, "DEC 3000/300 (\"Pelican\")" },
{ SV_ST_PELICA, "DEC 3000/300L (\"Pelica\")" },
{ SV_ST_PELICANPLUS, "DEC 3000/300X (\"Pelican+\")" },
{ SV_ST_PELICAPLUS, "DEC 3000/300LX (\"Pelica+\")" },
{ 0, NULL },
};
void
dec_3000_300_init(int cputype)
{
u_int64_t variation;
platform.family = "DEC 3000/300 (\"Pelican\")";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_3000_300_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "tcasic";
platform.cons_init = dec_3000_300_cons_init;
}
/*
* dec_3000_300_cons_init- not needed right now.
*
*/
static void
dec_3000_300_cons_init(void)
{
return;
}

107
sys/alpha/alpha/dec_3000_500.c
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@ -1,107 +0,0 @@
/*-
* Copyright (c) 1997 by Matthew Jacob
* NASA AMES Research Center.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_cpu.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <alpha/tlsb/tlsbreg.h>
#include <alpha/tlsb/gbusreg.h>
#include <alpha/tlsb/zsvar.h>
void dec_3000_500_init(int);
static void dec_3000_500_cons_init(void);
static const char dec_3000_500_sp[] = "DEC 3000/400 (\"Sandpiper\")";
static const char dec_3000_500_sf[] = "DEC 3000/500 (\"Flamingo\")";
const struct alpha_variation_table dec_3000_500_variations[] = {
{ SV_ST_SANDPIPER, dec_3000_500_sp },
{ SV_ST_FLAMINGO, dec_3000_500_sf },
{ SV_ST_HOTPINK, "DEC 3000/500X (\"Hot Pink\")" },
{ SV_ST_FLAMINGOPLUS, "DEC 3000/800 (\"Flamingo+\")" },
{ SV_ST_SANDPLUS, "DEC 3000/600 (\"Sandpiper+\")" },
{ SV_ST_SANDPIPER45, "DEC 3000/700 (\"Sandpiper45\")" },
{ SV_ST_FLAMINGO45, "DEC 3000/900 (\"Flamingo45\")" },
{ 0, NULL },
};
void
dec_3000_500_init(int cputype)
{
u_int64_t variation;
platform.family = "DEC 3000/500 (\"Flamingo\")";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if (variation == SV_ST_ULTRA) {
/* These are really the same. */
variation = SV_ST_FLAMINGOPLUS;
}
if ((platform.model = alpha_variation_name(variation,
dec_3000_500_variations)) == NULL) {
/*
* This is how things used to be done.
*/
if (variation == SV_ST_RESERVED) {
if (hwrpb->rpb_variation & SV_GRAPHICS)
platform.model = dec_3000_500_sf;
else
platform.model = dec_3000_500_sp;
} else
platform.model = alpha_unknown_sysname();
}
}
platform.iobus = "tcasic";
platform.cons_init = dec_3000_500_cons_init;
}
/*
* dec_3000_500_cons_init- not needed right now.
*
*/
static void
dec_3000_500_cons_init(void)
{
return;
}

237
sys/alpha/alpha/dec_axppci_33.c
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@ -1,237 +0,0 @@
/* $NetBSD: dec_axppci_33.c,v 1.38 1998/07/07 08:49:12 ross Exp $ */
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/lcavar.h>
void dec_axppci_33_init(void);
static void dec_axppci_33_cons_init(void);
static int dec_axppci_33_intr_route (device_t, device_t, int);
const struct alpha_variation_table dec_axppci_33_variations[] = {
{ 0, "Alpha PC AXPpci33 (\"NoName\")" },
{ 0, NULL },
};
#define NSIO_PORT 0x26e /* Hardware enabled option: 0x398 */
#define NSIO_BASE 0
#define NSIO_INDEX NSIO_BASE
#define NSIO_DATA 1
#define NSIO_SIZE 2
#define NSIO_CFG0 0
#define NSIO_CFG1 1
#define NSIO_CFG2 2
#define NSIO_IDE_ENABLE 0x40
void
dec_axppci_33_init()
{
int cfg0val;
u_int64_t variation;
platform.family = "DEC AXPpci";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_axppci_33_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "lca";
platform.cons_init = dec_axppci_33_cons_init;
platform.pci_intr_route = dec_axppci_33_intr_route;
platform.pci_intr_map = NULL;
lca_init();
outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0);
alpha_mb();
cfg0val = inb(NSIO_PORT + NSIO_DATA);
cfg0val |= NSIO_IDE_ENABLE;
outb(NSIO_PORT + NSIO_INDEX, NSIO_CFG0);
alpha_mb();
outb(NSIO_PORT + NSIO_DATA, cfg0val);
alpha_mb();
outb(NSIO_PORT + NSIO_DATA, cfg0val);
}
static void
dec_axppci_33_cons_init()
{
struct ctb *ctb;
lca_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type");
}
}
#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */
static int
dec_axppci_33_intr_route(device_t pcib, device_t dev, int pin)
{
int pirq;
u_int32_t pirqreg;
u_int8_t pirqline;
#ifndef DIAGNOSTIC
pirq = 0; /* XXX gcc -Wuninitialized */
#endif
/*
* Slot->interrupt translation. Taken from NetBSD.
*/
if (pin == 0) {
/* No IRQ used. */
return -1;
}
if (pin > 4) {
printf("dec_axppci_33_intr_route: bad interrupt pin %d\n", pin);
return -1;
}
switch (pci_get_slot(dev)) {
case 6: /* NCR SCSI */
pirq = 3;
break;
case 11: /* slot 1 */
switch (pin) {
case 1:
case 4:
pirq = 0;
break;
case 2:
pirq = 2;
break;
case 3:
pirq = 1;
break;
#ifdef DIAGNOSTIC
default: /* XXX gcc -Wuninitialized */
panic("dec_axppci_33_intr_route: bogus PCI pin %d\n",
pin);
#endif
};
break;
case 12: /* slot 2 */
switch (pin) {
case 1:
case 4:
pirq = 1;
break;
case 2:
pirq = 0;
break;
case 3:
pirq = 2;
break;
#ifdef DIAGNOSTIC
default: /* XXX gcc -Wuninitialized */
panic("dec_axppci_33_intr_route: bogus PCI pin %d\n",
pin);
#endif
};
break;
case 8: /* slot 3 */
switch (pin) {
case 1:
case 4:
pirq = 2;
break;
case 2:
pirq = 1;
break;
case 3:
pirq = 0;
break;
#ifdef DIAGNOSTIC
default: /* XXX gcc -Wuninitialized */
panic("dec_axppci_33_intr_route: bogus PCI pin %d\n",
pin);
#endif
};
break;
default:
printf("dec_axppci_33_intr_route: weird device number %d\n",
pci_get_slot(dev));
return -1;
}
pirqreg = lca_pcib_read_config(0, 0, 7, 0,
SIO_PCIREG_PIRQ_RTCTRL, 4);
pirqline = (pirqreg >> (pirq * 8)) & 0xff;
if ((pirqline & 0x80) != 0)
panic("bad pirqline %d",pirqline);
pirqline &= 0xf;
return(pirqline);
}

113
sys/alpha/alpha/dec_eb164.c
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@ -1,113 +0,0 @@
/* $NetBSD: dec_eb164.c,v 1.26 1998/04/17 02:45:19 mjacob Exp $ */
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <alpha/pci/ciavar.h>
void dec_eb164_init(void);
static void dec_eb164_cons_init(void);
static void eb164_intr_init(void);
extern void eb164_intr_enable(int irq);
extern void eb164_intr_disable(int irq);
extern void eb164_intr_enable_icsr(int irq);
extern void eb164_intr_disable_icsr(int irq);
void
dec_eb164_init()
{
platform.family = "EB164";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
/* XXX Don't know the system variations, yet. */
platform.model = alpha_unknown_sysname();
}
platform.iobus = "cia";
platform.cons_init = dec_eb164_cons_init;
platform.pci_intr_init = eb164_intr_init;
platform.pci_intr_map = NULL;
if (strncmp(platform.model, "Digital AlphaPC 164 ", 20) == 0) {
platform.pci_intr_disable = eb164_intr_disable_icsr;
platform.pci_intr_enable = eb164_intr_enable_icsr;
} else {
platform.pci_intr_disable = eb164_intr_disable;
platform.pci_intr_enable = eb164_intr_enable;
}
}
static void
dec_eb164_cons_init()
{
struct ctb *ctb;
cia_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %d\n",
(int)ctb->ctb_term_type);
}
}
static void
eb164_intr_init()
{
/*
* Enable ISA-PCI cascade interrupt.
*/
eb164_intr_enable(4);
}

152
sys/alpha/alpha/dec_eb64plus.c
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@ -1,152 +0,0 @@
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
/*
* FreeBSD version based on:
* NetBSD: dec_eb64plus.c,v 1.15 1998/11/19 02:20:07 ross Exp
*
* Some info on the Aspen Alpine which might be hard to come by:
* - Hardware is close enough to the DEC EB64+ design to allow it to run
* the EB64+ SRM console firmware
* - 3 PCI slots, closest to the SIMMs: Alpine calls this one slot C
* the middle one Alpine calls slot B
* the 3rd one Alpine calls slot A
* (A, B, C are silkscreened on the PCB)
* - embedded NCR810, located at PCI slot 5
* - 3 ISA slots, hanging off an Intel 82378IB PCI-ISA bridge at PCI slot 8
* - embedded floppy, PC keyboard interface, PS/2 mouse interface, 2 serial
* ports and a parallel port. All of this hanging off the ISA bridge
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/apecsreg.h>
#include <alpha/pci/apecsvar.h>
void dec_eb64plus_init(void);
static void dec_eb64plus_cons_init(void);
static void dec_eb64plus_intr_init(void);
extern void eb64plus_intr_enable(int irq); /* ../pci/pci_eb64plus_intr.s */
extern void eb64plus_intr_disable(int irq); /* ../pci/pci_eb64plus_intr.s */
extern const char * bootdev_protocol(void);
extern int bootdev_boot_dev_type(void);
const struct alpha_variation_table dec_eb64plus_variations[] = {
{ 0, "DEC EB64-plus" },
{ 0, NULL },
};
void
dec_eb64plus_init()
{
u_int64_t variation;
platform.family = "EB64+";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_eb64plus_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "apecs";
platform.cons_init = dec_eb64plus_cons_init;
platform.pci_intr_init = dec_eb64plus_intr_init;
/* SRM handles PCI interrupt mapping */
platform.pci_intr_map = NULL;
/* see ../pci/pci_eb64plus_intr.s for intr. dis/enable */
platform.pci_intr_disable = eb64plus_intr_disable;
platform.pci_intr_enable = eb64plus_intr_enable;
}
/* init the console, serial or graphics */
static void
dec_eb64plus_cons_init()
{
struct ctb *ctb;
apecs_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %d\n",
(int)ctb->ctb_term_type);
}
}
/*
* The SRM console may have left some some interrupts enabled.
*/
static void
dec_eb64plus_intr_init()
{
int i;
/* disable all PCI interrupts */
for(i = 0; i <= 32; i++) /* 32 ?? NetBSD sez so */
eb64plus_intr_disable(i);
/* Enable ISA-PCI cascade interrupt */
eb64plus_intr_enable(4);
}

310
sys/alpha/alpha/dec_kn20aa.c
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@ -1,310 +0,0 @@
/* $NetBSD: dec_kn20aa.c,v 1.38 1998/04/17 02:45:19 mjacob Exp $ */
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/ciareg.h>
#include <alpha/pci/ciavar.h>
void dec_kn20aa_init(void);
static void dec_kn20aa_cons_init(void);
static void dec_kn20aa_intr_init(void);
static int dec_kn20aa_intr_route(device_t pcib, device_t dev, int pin);
static void dec_kn20aa_intr_disable(int);
static void dec_kn20aa_intr_enable(int);
#if 0
static void dec_kn20aa_device_register(struct device *, void *);
#endif
const struct alpha_variation_table dec_kn20aa_variations[] = {
{ 0, "AlphaStation 500 or 600 (KN20AA)" },
{ 0, NULL },
};
void
dec_kn20aa_init()
{
u_int64_t variation;
platform.family = "AlphaStation 500 or 600 (KN20AA)";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_kn20aa_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "cia";
platform.cons_init = dec_kn20aa_cons_init;
platform.pci_intr_init = dec_kn20aa_intr_init;
platform.pci_intr_route = dec_kn20aa_intr_route;
platform.pci_intr_disable = dec_kn20aa_intr_disable;
platform.pci_intr_enable = dec_kn20aa_intr_enable;
}
static void
dec_kn20aa_cons_init()
{
struct ctb *ctb;
cia_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %d\n",
(int)ctb->ctb_term_type);
}
}
#if 0
static void
dec_kn20aa_device_register(dev, aux)
struct device *dev;
void *aux;
{
static int found, initted, scsiboot, netboot;
static struct device *pcidev, *scsidev;
struct bootdev_data *b = bootdev_data;
struct device *parent = dev->dv_parent;
struct cfdata *cf = dev->dv_cfdata;
struct cfdriver *cd = cf->cf_driver;
if (found)
return;
if (!initted) {
scsiboot = (strcmp(b->protocol, "SCSI") == 0);
netboot = (strcmp(b->protocol, "BOOTP") == 0);
#if 0
printf("scsiboot = %d, netboot = %d\n", scsiboot, netboot);
#endif
initted =1;
}
if (pcidev == NULL) {
if (strcmp(cd->cd_name, "pci"))
return;
else {
struct pcibus_attach_args *pba = aux;
if ((b->slot / 1000) != pba->pba_bus)
return;
pcidev = dev;
#if 0
printf("\npcidev = %s\n", pcidev->dv_xname);
#endif
return;
}
}
if (scsiboot && (scsidev == NULL)) {
if (parent != pcidev)
return;
else {
struct pci_attach_args *pa = aux;
if ((b->slot % 1000) != pa->pa_device)
return;
/* XXX function? */
scsidev = dev;
#if 0
printf("\nscsidev = %s\n", scsidev->dv_xname);
#endif
return;
}
}
if (scsiboot &&
(!strcmp(cd->cd_name, "sd") ||
!strcmp(cd->cd_name, "st") ||
!strcmp(cd->cd_name, "cd"))) {
struct scsipibus_attach_args *sa = aux;
if (parent->dv_parent != scsidev)
return;
if (b->unit / 100 != sa->sa_sc_link->scsipi_scsi.target)
return;
/* XXX LUN! */
switch (b->boot_dev_type) {
case 0:
if (strcmp(cd->cd_name, "sd") &&
strcmp(cd->cd_name, "cd"))
return;
break;
case 1:
if (strcmp(cd->cd_name, "st"))
return;
break;
default:
return;
}
/* we've found it! */
booted_device = dev;
#if 0
printf("\nbooted_device = %s\n", booted_device->dv_xname);
#endif
found = 1;
}
if (netboot) {
if (parent != pcidev)
return;
else {
struct pci_attach_args *pa = aux;
if ((b->slot % 1000) != pa->pa_device)
return;
/* XXX function? */
booted_device = dev;
#if 0
printf("\nbooted_device = %s\n", booted_device->dv_xname);
#endif
found = 1;
return;
}
}
}
#endif
#define KN20AA_MAX_IRQ 32
void
dec_kn20aa_intr_init()
{
/*
* Enable ISA-PCI cascade interrupt.
*/
dec_kn20aa_intr_enable(31);
}
static int
dec_kn20aa_intr_route(device_t pcib, device_t dev, int pin)
{
int irq = 255;
int slot = pci_get_slot(dev);
switch (slot) {
case 11:
irq = pin - 1;
break;
case 12:
irq = 4 + pin - 1;
break;
case 7:
irq = 8 + pin - 1;
break;
case 9: /* slot on AlphaStation 600 only */
irq = 12 + pin - 1;
break;
case 8:
irq = 16 + pin - 1;
break;
case 6: /* 21040 on AlphaStation 500 */
if (pin == 1)
irq = 13;
break;
case 10: /* 8275EB on AlphaStation 500 */
break;
default:
printf("dec_kn20aa_intr_route: weird slot %d\n", slot);
}
return (irq);
}
void
dec_kn20aa_intr_enable(irq)
int irq;
{
/*
* From disassembling small bits of the OSF/1 kernel:
* the following appears to enable a given interrupt request.
* "blech." I'd give valuable body parts for better docs or
* for a good decompiler.
*/
alpha_mb();
REGVAL(0x8780000000L + 0x40L) |= (1 << irq); /* XXX */
alpha_mb();
}
void
dec_kn20aa_intr_disable(irq)
int irq;
{
alpha_mb();
REGVAL(0x8780000000L + 0x40L) &= ~(1 << irq); /* XXX */
alpha_mb();
}

106
sys/alpha/alpha/dec_kn300.c
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@ -1,106 +0,0 @@
/*-
* Copyright (c) 2000 by Matthew Jacob
* NASA AMES Research Center.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/termios.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/intr.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/mcbus/mcbusreg.h>
#include <alpha/mcbus/mcbusvar.h>
void dec_kn300_init(void);
void dec_kn300_cons_init(void);
#define ALPHASERVER_4100 "AlphaServer 4100"
const struct alpha_variation_table dec_kn300_variations[] = {
{ 0, ALPHASERVER_4100 },
{ 0, NULL },
};
void
dec_kn300_init()
{
u_int64_t variation;
platform.family = ALPHASERVER_4100;
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_kn300_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "mcbus";
platform.cons_init = dec_kn300_cons_init;
}
void
dec_kn300_cons_init()
{
struct ctb *ctb;
mcbus_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown cons type %ld\n", ctb->ctb_term_type);
}
}

89
sys/alpha/alpha/dec_kn8ae.c
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@ -1,89 +0,0 @@
/* $NetBSD: dec_kn8ae.c,v 1.15 1998/02/13 00:12:50 thorpej Exp $ */
/*-
* Copyright (c) 1997 by Matthew Jacob
* NASA AMES Research Center.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/termios.h>
#include <sys/cons.h>
#include <sys/reboot.h>
#include <sys/bus.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <alpha/tlsb/tlsbreg.h>
#include <alpha/tlsb/gbusreg.h>
#include <alpha/tlsb/zsvar.h>
void dec_kn8ae_init(int);
static void dec_kn8ae_cons_init(void);
static const struct alpha_variation_table dec_kn8ae_variations[] = {
{ 0, "AlphaServer 8400" },
{ 0, NULL },
};
void
dec_kn8ae_init(int cputype)
{
u_int64_t variation;
platform.family = "AlphaServer 8400";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
variation = hwrpb->rpb_variation & SV_ST_MASK;
if ((platform.model = alpha_variation_name(variation,
dec_kn8ae_variations)) == NULL)
platform.model = alpha_unknown_sysname();
}
platform.iobus = "tlsb";
platform.cons_init = dec_kn8ae_cons_init;
}
/*
* Info to retain:
*
* The AXP 8X00 seems to encode the
* type of console in the ctb_type field,
* not the ctb_term_type field.
*/
static void
dec_kn8ae_cons_init(void)
{
boothowto |= RB_SERIAL;
zs_cnattach(TLSB_GBUS_BASE, GBUS_DUART0_OFFSET);
}

240
sys/alpha/alpha/dec_st550.c
View File

@ -1,240 +0,0 @@
/*-
* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
*/
/*-
* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/termios.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/intr.h>
#include <machine/md_var.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/ciareg.h>
#include <alpha/pci/ciavar.h>
void st550_init(void);
static void st550_cons_init(void);
static void st550_intr_init(void);
static void pyxis_intr_enable(int);
static void pyxis_intr_disable(int);
static void st550_intr_enable(int);
static void st550_intr_disable(int);
static void st550_intr_map(void *);
#define ST550_PCI_IRQ_BEGIN 8
#define ST550_PCI_MAX_IRQ 47
void
st550_init()
{
platform.family = "Digital Personal Workstation (Miata)";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
/* XXX Don't know the system variations, yet. */
platform.model = alpha_unknown_sysname();
}
platform.iobus = "cia";
platform.cons_init = st550_cons_init;
platform.pci_intr_init = st550_intr_init;
platform.pci_intr_map = st550_intr_map;
platform.pci_intr_disable = st550_intr_disable;
platform.pci_intr_enable = st550_intr_enable;
}
static void
st550_cons_init()
{
struct ctb *ctb;
cia_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %ld\n",
ctb->ctb_term_type);
}
}
static void
st550_intr_init()
{
/* This is here because we need to disable extraneous pci interrupts. */
int i;
for(i = ST550_PCI_IRQ_BEGIN; i <= ST550_PCI_MAX_IRQ; i++)
pyxis_intr_disable(i);
/* From Linux... */
pyxis_intr_enable(2); /* enable HALT switch */
pyxis_intr_enable(6); /* enable timer */
pyxis_intr_enable(7); /* enable ISA PIC cascade */
}
static void
st550_intr_map(void *arg)
{
pcicfgregs *cfg;
cfg = (pcicfgregs *)arg;
/* There are two main variants of Miata: Miata 1 (Intel SIO)
* and Miata {1.5,2} (Cypress).
*
* The Miata 1 has a CMD PCI IDE wired to compatibility mode at
* slot 4 of bus 0. This variant has the Pyxis DMA bug.
*
* On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
* on device 7 of bus 0. This device has PCI IDE wired to
* compatibility mode on functions 1 and 2.
*
* There will be no interrupt mapping for these devices, so just
* bail out now.
*/
if(cfg->bus == 0) {
if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
/* Miata 1 */
if (cfg->slot == 7)
return;
else if (cfg->func == 4)
return;
} else {
/* Miata 1.5 or Miata 2 */
if (cfg->slot == 7) {
if (cfg->func == 0)
return;
return;
}
}
}
/* Account for the PCI interrupt offset. */
/* cfg->intline += ST550_PCI_IRQ_BEGIN; */
return;
}
/*
* The functions below were written based on a draft copy of the
* 21174 TRM.
*/
static void
pyxis_intr_enable(irq)
int irq;
{
volatile u_int64_t temp;
alpha_mb();
temp = REGVAL64(PYXIS_INT_MASK);
alpha_mb();
temp |= ( 1L << irq );
REGVAL64(PYXIS_INT_MASK) = temp;
alpha_mb();
temp = REGVAL64(PYXIS_INT_MASK);
#if 0
printf("pyxis_intr_enable: enabling %d, current mask= ", irq);
{
int i;
for ( i = 0; i < 61; i++)
if (temp & (1 << i)) {
printf("%d " , i);
}
printf("\n");
}
#endif
}
static void
pyxis_intr_disable(irq)
int irq;
{
volatile u_int64_t temp;
alpha_mb();
temp = REGVAL64(PYXIS_INT_MASK);
temp &= ~(1L << irq );
REGVAL64(PYXIS_INT_MASK) = temp;
alpha_mb();
temp = REGVAL64(PYXIS_INT_MASK);
#if 0
printf("pyxis_intr_disable: disabled %d, current mask ", irq);
{
int i;
for ( i = 0; i < 61; i++)
if (temp & (1 << i)) {
printf("%d ", i);
}
printf("\n");
}
#endif
}
static void
st550_intr_enable(irq)
int irq;
{
pyxis_intr_enable(irq + ST550_PCI_IRQ_BEGIN);
}
static void
st550_intr_disable(irq)
int irq;
{
pyxis_intr_disable(irq + ST550_PCI_IRQ_BEGIN);
}

110
sys/alpha/alpha/dec_st6600.c
View File

@ -1,110 +0,0 @@
/*-
* Copyright (c) 1999 Andrew Gallatin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/termios.h>
#include <machine/clock.h>
#include <machine/cpuconf.h>
#include <machine/md_var.h>
#include <machine/intr.h>
#include <machine/rpb.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <alpha/pci/tsunamivar.h>
void st6600_init(void);
static void st6600_cons_init(void);
static void st6600_intr_init(void);
#define ST6600_PCI_IRQ_BEGIN 8
#define ST6600_PCI_MAX_IRQ 63
void
st6600_init()
{
platform.family = "ST6600";
if ((platform.model = alpha_dsr_sysname()) == NULL) {
/* XXX Don't know the system variations, yet. */
platform.model = alpha_unknown_sysname();
}
platform.iobus = "tsunami";
platform.cons_init = st6600_cons_init;
platform.pci_intr_init = st6600_intr_init;
}
static void
st6600_cons_init()
{
struct ctb *ctb;
tsunami_init();
ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
switch (ctb->ctb_term_type) {
case 2:
boothowto |= RB_SERIAL;
break;
case 3:
boothowto &= ~RB_SERIAL;
break;
default:
printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
panic("consinit: unknown console type %ld\n",
ctb->ctb_term_type);
}
}
static void
st6600_intr_init()
{
int i;
for(i = ST6600_PCI_IRQ_BEGIN; i <= ST6600_PCI_MAX_IRQ; i++)
platform.pci_intr_disable(i);
/* From Linux... */
platform.pci_intr_enable(55);
platform.pci_intr_enable(2);
}

198
sys/alpha/alpha/divrem.m4
View File

@ -1,198 +0,0 @@
/* $FreeBSD$ */
/* $NetBSD: divrem.m4,v 1.5 1996/10/17 04:26:25 cgd Exp $ */
/*-
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* Division and remainder.
*
* The use of m4 is modeled after the sparc code, but the algorithm is
* simple binary long division.
*
* Note that the loops could probably benefit from unrolling.
*/
/*
* M4 Parameters
* NAME name of function to generate
* OP OP=div: t10 / t11 -> t12; OP=rem: t10 % t11 -> t12
* S S=true: signed; S=false: unsigned
* WORDSIZE total number of bits
*/
define(A, `t10')
define(B, `t11')
define(RESULT, `t12')
define(BIT, `t0')
define(I, `t1')
define(CC, `t2')
define(T_0, `t3')
ifelse(S, `true', `define(NEG, `t4')')
#include <machine/asm.h>
NESTED(NAME, 0, 0, t9, 0, 0) /* Get the right ra */
lda sp, -64(sp)
stq BIT, 0(sp)
stq I, 8(sp)
stq CC, 16(sp)
stq T_0, 24(sp)
ifelse(S, `true',
` stq NEG, 32(sp)')
stq A, 40(sp)
stq B, 48(sp)
mov zero, RESULT /* Initialize result to zero */
ifelse(S, `true',
`
/* Compute sign of result. If either is negative, this is easy. */
or A, B, NEG /* not the sign, but... */
srl NEG, WORDSIZE - 1, NEG /* rather, or of high bits */
blbc NEG, Ldoit /* neither negative? do it! */
ifelse(OP, `div',
` xor A, B, NEG /* THIS is the sign! */
', ` mov A, NEG /* sign follows A. */
')
srl NEG, WORDSIZE - 1, NEG /* make negation the low bit. */
srl A, WORDSIZE - 1, I /* is A negative? */
blbc I, LnegB /* no. */
/* A is negative; flip it. */
ifelse(WORDSIZE, `32', `
/* top 32 bits may be random junk */
zap A, 0xf0, A
')
subq zero, A, A
srl B, WORDSIZE - 1, I /* is B negative? */
blbc I, Ldoit /* no. */
LnegB:
/* B is definitely negative, no matter how we got here. */
ifelse(WORDSIZE, `32', `
/* top 32 bits may be random junk */
zap B, 0xf0, B
')
subq zero, B, B
Ldoit:
')
ifelse(WORDSIZE, `32', `
/*
* Clear the top 32 bits of each operand, as they may
* sign extension (if negated above), or random junk.
*/
zap A, 0xf0, A
zap B, 0xf0, B
')
/* kill the special cases. */
beq B, Ldotrap /* division by zero! */
cmpult A, B, CC /* A < B? */
/* RESULT is already zero, from above. A is untouched. */
bne CC, Lret_result
cmpeq A, B, CC /* A == B? */
cmovne CC, 1, RESULT
cmovne CC, zero, A
bne CC, Lret_result
/*
* Find out how many bits of zeros are at the beginning of the divisor.
*/
LBbits:
ldiq T_0, 1 /* I = 0; BIT = 1<<WORDSIZE-1 */
mov zero, I
sll T_0, WORDSIZE-1, BIT
LBloop:
and B, BIT, CC /* if bit in B is set, done. */
bne CC, LAbits
addq I, 1, I /* increment I, shift bit */
srl BIT, 1, BIT
cmplt I, WORDSIZE-1, CC /* if I leaves one bit, done. */
bne CC, LBloop
LAbits:
beq I, Ldodiv /* If I = 0, divide now. */
ldiq T_0, 1 /* BIT = 1<<WORDSIZE-1 */
sll T_0, WORDSIZE-1, BIT
LAloop:
and A, BIT, CC /* if bit in A is set, done. */
bne CC, Ldodiv
subq I, 1, I /* decrement I, shift bit */
srl BIT, 1, BIT
bne I, LAloop /* If I != 0, loop again */
Ldodiv:
sll B, I, B /* B <<= i */
ldiq T_0, 1
sll T_0, I, BIT
Ldivloop:
cmpult A, B, CC
or RESULT, BIT, T_0
cmoveq CC, T_0, RESULT
subq A, B, T_0
cmoveq CC, T_0, A
srl BIT, 1, BIT
srl B, 1, B
beq A, Lret_result
bne BIT, Ldivloop
Lret_result:
ifelse(OP, `div',
`', ` mov A, RESULT
')
ifelse(S, `true',
`
/* Check to see if we should negate it. */
subq zero, RESULT, T_0
cmovlbs NEG, T_0, RESULT
')
ldq BIT, 0(sp)
ldq I, 8(sp)
ldq CC, 16(sp)
ldq T_0, 24(sp)
ifelse(S, `true',
` ldq NEG, 32(sp)')
ldq A, 40(sp)
ldq B, 48(sp)
lda sp, 64(sp)
ret zero, (t9), 1
Ldotrap:
ldiq a0, -2 /* This is the signal to SIGFPE! */
call_pal PAL_gentrap
ifelse(OP, `div',
`', ` mov zero, A /* so that zero will be returned */
')
br zero, Lret_result
END(NAME)

129
sys/alpha/alpha/dump_machdep.c
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@ -1,129 +0,0 @@
/*-
* Copyright (c) 2002 Poul-Henning Kamp
* Copyright (c) 2002 Networks Associates Technology, Inc.
* All rights reserved.
*
* This software was developed for the FreeBSD Project by Poul-Henning Kamp
* and NAI Labs, the Security Research Division of Network Associates, Inc.
* under DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the
* DARPA CHATS research program.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The names of the authors may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/kerneldump.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/md_var.h>
CTASSERT(sizeof(struct kerneldumpheader) == 512);
static struct kerneldumpheader kdh;
void
dumpsys(struct dumperinfo *di)
{
off_t dumplo;
vm_offset_t a, addr;
u_int count, left, u;
void *va;
int i, mb;
printf("Dumping %ld MB\n", Maxmem / (1024*1024 / PAGE_SIZE));
/* Fill in the kernel dump header */
strcpy(kdh.magic, KERNELDUMPMAGIC);
strcpy(kdh.architecture, "alpha");
kdh.version = htod32(KERNELDUMPVERSION);
kdh.architectureversion = htod32(KERNELDUMP_ALPHA_VERSION);
kdh.dumplength = htod64(Maxmem * (off_t)PAGE_SIZE);
kdh.dumptime = htod64(time_second);
kdh.blocksize = htod32(di->blocksize);
strncpy(kdh.hostname, hostname, sizeof kdh.hostname);
strncpy(kdh.versionstring, version, sizeof kdh.versionstring);
if (panicstr != NULL)
strncpy(kdh.panicstring, panicstr, sizeof kdh.panicstring);
kdh.parity = kerneldump_parity(&kdh);
/*
* Check if we will have enough room to save the coredump.
* The partition size needed is the sum of:
* Memory to save + header + trailer + Room to leave untouched
* at partition head. (an arbitrary amount).
*/
if (di->mediasize <
Maxmem * (off_t)PAGE_SIZE + sizeof kdh * 2 + 64*1024) {
printf("\nDump failed. Partition too small.\n");
return;
}
dumplo = di->mediaoffset + di->mediasize - Maxmem * (off_t)PAGE_SIZE;
dumplo -= sizeof kdh * 2;
i = di->dumper(di->priv, &kdh, 0, dumplo, sizeof kdh);
if (i)
printf("\nDump failed writing header (%d)\n", i);
dumplo += sizeof kdh;
i = 0;
addr = 0;
va = 0;
mb = 0;
for (count = 0; count < Maxmem;) {
left = Maxmem - count;
if (left > MAXDUMPPGS)
left = MAXDUMPPGS;
for (u = 0; u < left; u++) {
a = addr + u * PAGE_SIZE;
if (!is_physical_memory(a))
a = 0;
va = pmap_kenter_temporary(trunc_page(a), u);
}
i = count / (16*1024*1024 / PAGE_SIZE);
if (i != mb) {
printf(" %d", count / (1024 * 1024 / PAGE_SIZE));
mb = i;
}
i = di->dumper(di->priv, va, 0, dumplo, left * PAGE_SIZE);
if (i)
break;
count += left;
dumplo += left * PAGE_SIZE;
addr += left * PAGE_SIZE;
}
if (i)
printf("\nDump failed writing data (%d)\n", i);
i = di->dumper(di->priv, &kdh, 0, dumplo, sizeof kdh);
if (i)
printf("\nDump failed writing trailer (%d)\n", i);
di->dumper(di->priv, NULL, 0, 0, 0); /* tell them we are done */
printf("\nDump complete\n");
return;
}

237
sys/alpha/alpha/elf_machdep.c
View File

@ -1,237 +0,0 @@
/*-
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/exec.h>
#include <sys/imgact.h>
#include <sys/malloc.h>
#include <sys/proc.h>
#include <sys/namei.h>
#include <sys/fcntl.h>
#include <sys/sysent.h>
#include <sys/imgact_elf.h>
#include <sys/syscall.h>
#include <sys/signalvar.h>
#include <sys/vnode.h>
#include <sys/linker.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <machine/elf.h>
#include <machine/md_var.h>
struct sysentvec elf64_freebsd_sysvec = {
SYS_MAXSYSCALL,
sysent,
0,
0,
NULL,
0,
NULL,
NULL,
__elfN(freebsd_fixup),
sendsig,
sigcode,
&szsigcode,
0,
"FreeBSD ELF64",
__elfN(coredump),
NULL,
MINSIGSTKSZ,
PAGE_SIZE,
VM_MIN_ADDRESS,
VM_MAXUSER_ADDRESS,
USRSTACK,
PS_STRINGS,
VM_PROT_ALL,
exec_copyout_strings,
exec_setregs,
NULL
};
static Elf64_Brandinfo freebsd_brand_info = {
ELFOSABI_FREEBSD,
EM_ALPHA,
"FreeBSD",
NULL,
"/libexec/ld-elf.so.1",
&elf64_freebsd_sysvec,
NULL,
0,
};
SYSINIT(elf64, SI_SUB_EXEC, SI_ORDER_ANY,
(sysinit_cfunc_t) elf64_insert_brand_entry,
&freebsd_brand_info);
static Elf64_Brandinfo freebsd_brand_oinfo = {
ELFOSABI_FREEBSD,
EM_ALPHA,
"FreeBSD",
NULL,
"/usr/libexec/ld-elf.so.1",
&elf64_freebsd_sysvec,
NULL,
0,
};
SYSINIT(oelf64, SI_SUB_EXEC, SI_ORDER_ANY,
(sysinit_cfunc_t) elf64_insert_brand_entry,
&freebsd_brand_oinfo);
void
elf64_dump_thread(struct thread *td __unused, void *dst __unused,
size_t *off __unused)
{
}
/* Process one elf relocation with addend. */
static int
elf_reloc_internal(linker_file_t lf, Elf_Addr relocbase, const void *data,
int type, int local, elf_lookup_fn lookup)
{
Elf_Addr *where;
Elf_Addr addr;
Elf_Addr addend;
Elf_Size rtype, symidx;
const Elf_Rel *rel;
const Elf_Rela *rela;
switch (type) {
case ELF_RELOC_REL:
rel = (const Elf_Rel *)data;
where = (Elf_Addr *) (relocbase + rel->r_offset);
addend = *where;
rtype = ELF_R_TYPE(rel->r_info);
symidx = ELF_R_SYM(rel->r_info);
break;
case ELF_RELOC_RELA:
rela = (const Elf_Rela *)data;
where = (Elf_Addr *) (relocbase + rela->r_offset);
addend = rela->r_addend;
rtype = ELF_R_TYPE(rela->r_info);
symidx = ELF_R_SYM(rela->r_info);
break;
default:
panic("elf_reloc: unknown relocation mode %d\n", type);
}
if (local) {
if (rtype == R_ALPHA_RELATIVE) {
addr = relocbase + addend;
if (*where != addr)
*where = addr;
}
return (0);
}
switch (rtype) {
case R_ALPHA_NONE:
break;
case R_ALPHA_REFQUAD:
addr = lookup(lf, symidx, 1);
if (addr == 0)
return -1;
addr += addend;
if (*where != addr)
*where = addr;
break;
case R_ALPHA_GLOB_DAT:
addr = lookup(lf, symidx, 1);
if (addr == 0)
return -1;
addr += addend;
if (*where != addr)
*where = addr;
break;
case R_ALPHA_JMP_SLOT:
/* No point in lazy binding for kernel modules. */
addr = lookup(lf, symidx, 1);
if (addr == 0)
return -1;
if (*where != addr)
*where = addr;
break;
case R_ALPHA_RELATIVE:
break;
case R_ALPHA_COPY:
/*
* There shouldn't be copy relocations in kernel
* objects.
*/
printf("kldload: unexpected R_COPY relocation\n");
return -1;
default:
printf("kldload: unexpected relocation type %d\n",
(int) rtype);
return -1;
}
return(0);
}
int
elf_reloc(linker_file_t lf, Elf_Addr relocbase, const void *data, int type,
elf_lookup_fn lookup)
{
return (elf_reloc_internal(lf, relocbase, data, type, 0, lookup));
}
int
elf_reloc_local(linker_file_t lf, Elf_Addr relocbase, const void *data,
int type, elf_lookup_fn lookup)
{
return (elf_reloc_internal(lf, relocbase, data, type, 1, lookup));
}
int
elf_cpu_load_file(linker_file_t lf __unused)
{
return (0);
}
int
elf_cpu_unload_file(linker_file_t lf __unused)
{
return (0);
}

384
sys/alpha/alpha/exception.s
View File

@ -1,384 +0,0 @@
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
* $NetBSD: locore.s,v 1.47 1998/03/22 07:26:32 thorpej Exp $
* $FreeBSD$
*/
#include <machine/asm.h>
#include <assym.s>
/**************************************************************************/
/*
* XentArith:
* System arithmetic trap entry point.
*/
PALVECT(XentArith) /* setup frame, save registers */
/* a0, a1, & a2 already set up */
ldiq a3, ALPHA_KENTRY_ARITH
mov sp, a4 ; .loc 1 __LINE__
CALL(trap)
jmp zero, exception_return
END(XentArith)
/**************************************************************************/
/*
* XentIF:
* System instruction fault trap entry point.
*/
PALVECT(XentIF) /* setup frame, save registers */
/* a0, a1, & a2 already set up */
ldiq a3, ALPHA_KENTRY_IF
mov sp, a4 ; .loc 1 __LINE__
CALL(trap)
jmp zero, exception_return
END(XentIF)
/**************************************************************************/
/*
* XentInt:
* System interrupt entry point.
*/
PALVECT(XentInt) /* setup frame, save registers */
/* a0, a1, & a2 already set up */
mov sp, a3 ; .loc 1 __LINE__
CALL(interrupt)
jmp zero, exception_return
END(XentInt)
/**************************************************************************/
/*
* XentMM:
* System memory management fault entry point.
*/
PALVECT(XentMM) /* setup frame, save registers */
/* a0, a1, & a2 already set up */
ldiq a3, ALPHA_KENTRY_MM
mov sp, a4 ; .loc 1 __LINE__
CALL(trap)
jmp zero, exception_return
END(XentMM)
/**************************************************************************/
/*
* XentSys:
* System call entry point.
*/
ESETUP(XentSys) ; .loc 1 __LINE__
stq v0,(FRAME_V0*8)(sp) /* in case we need to restart */
stq s0,(FRAME_S0*8)(sp)
stq s1,(FRAME_S1*8)(sp)
stq s2,(FRAME_S2*8)(sp)
stq s3,(FRAME_S3*8)(sp)
stq s4,(FRAME_S4*8)(sp)
stq s5,(FRAME_S5*8)(sp)
stq s6,(FRAME_S6*8)(sp)
stq a3,(FRAME_A3*8)(sp)
stq a4,(FRAME_A4*8)(sp)
stq a5,(FRAME_A5*8)(sp)
stq ra,(FRAME_RA*8)(sp)
stq a0,(FRAME_A0*8)(sp)
stq a1,(FRAME_A1*8)(sp)
stq a2,(FRAME_A2*8)(sp)
ldiq t1,FRAME_FLAGS_SYSCALL
stq t1,(FRAME_FLAGS*8)(sp)
/* syscall number, passed in v0, is first arg, frame pointer second */
mov v0,a0
mov sp,a1 ; .loc 1 __LINE__
br pv,1f
1: LDGP(pv)
CALL(syscall)
/* Handle any AST's. */
2: ldiq a0, ALPHA_PSL_IPL_HIGH /* disable all interrupts */
call_pal PAL_OSF1_swpipl
ldq s0, PC_CURTHREAD(pcpup) /* checking for pending asts */
ldl s1, TD_FLAGS(s0)
ldiq s2, TDF_ASTPENDING | TDF_NEEDRESCHED
and s1, s2
beq s1, 3f
ldiq a0, ALPHA_PSL_IPL_0 /* reenable interrupts */
call_pal PAL_OSF1_swpipl
mov sp, a0 /* only arg is frame */
CALL(ast)
jmp zero, 2b
/* see if we need a full exception_return */
3: ldq t1, (FRAME_FLAGS*8)(sp)
and t1, FRAME_FLAGS_SYSCALL
beq t1, exception_return
/* set the hae register if this process has specified a value */
ldq t1, TD_MD_FLAGS(s0)
and t1, MDTD_HAEUSED
beq t1, 3f
ldq a0, TD_MD_HAE(s0)
ldq pv, chipset + CHIPSET_WRITE_HAE
CALL((pv))
3:
#ifdef SMP
/* leave the kernel */
stl zero, TD_MD_KERNNEST(s0)
#endif
/* restore the registers, and return */
ldq v0,(FRAME_V0*8)(sp)
ldq s0,(FRAME_S0*8)(sp)
ldq s1,(FRAME_S1*8)(sp)
ldq s2,(FRAME_S2*8)(sp)
ldq s3,(FRAME_S3*8)(sp)
ldq s4,(FRAME_S4*8)(sp)
ldq s5,(FRAME_S5*8)(sp)
ldq s6,(FRAME_S6*8)(sp)
ldq a3,(FRAME_A3*8)(sp)
ldq a4,(FRAME_A4*8)(sp)
ldq a5,(FRAME_A5*8)(sp)
ldq ra,(FRAME_RA*8)(sp)
ldq a0,(FRAME_A0*8)(sp)
ldq a1,(FRAME_A1*8)(sp)
ldq a2,(FRAME_A2*8)(sp)
lda sp,(FRAME_SW_SIZE*8)(sp)
call_pal PAL_OSF1_retsys
END(XentSys)
/**************************************************************************/
/*
* XentUna:
* System unaligned access entry point.
*/
LEAF(XentUna, 3) /* XXX should be NESTED */
.set noat
lda sp,-(FRAME_SW_SIZE*8)(sp)
stq at_reg,(FRAME_AT*8)(sp)
.set at
stq ra,(FRAME_RA*8)(sp)
bsr ra, exception_save_regs /* jmp/CALL trashes pv/t12 */
/* a0, a1, & a2 already set up */
ldiq a3, ALPHA_KENTRY_UNA
mov sp, a4 ; .loc 1 __LINE__
br pv, 1f
1: LDGP(pv)
CALL(trap)
jmp zero, exception_return
END(XentUna)
/**************************************************************************/
/*
* console 'restart' routine to be placed in HWRPB.
*/
LEAF(XentRestart, 1) /* XXX should be NESTED */
.set noat
lda sp,-(FRAME_SIZE*8)(sp)
stq at_reg,(FRAME_AT*8)(sp)
.set at
stq v0,(FRAME_V0*8)(sp)
stq a3,(FRAME_A3*8)(sp)
stq a4,(FRAME_A4*8)(sp)
stq a5,(FRAME_A5*8)(sp)
stq s0,(FRAME_S0*8)(sp)
stq s1,(FRAME_S1*8)(sp)
stq s2,(FRAME_S2*8)(sp)
stq s3,(FRAME_S3*8)(sp)
stq s4,(FRAME_S4*8)(sp)
stq s5,(FRAME_S5*8)(sp)
stq s6,(FRAME_S6*8)(sp)
stq t0,(FRAME_T0*8)(sp)
stq t1,(FRAME_T1*8)(sp)
stq t2,(FRAME_T2*8)(sp)
stq t3,(FRAME_T3*8)(sp)
stq t4,(FRAME_T4*8)(sp)
stq t5,(FRAME_T5*8)(sp)
stq t6,(FRAME_T6*8)(sp)
stq t7,(FRAME_T7*8)(sp)
stq t8,(FRAME_T8*8)(sp)
stq t9,(FRAME_T9*8)(sp)
stq t10,(FRAME_T10*8)(sp)
stq t11,(FRAME_T11*8)(sp)
stq t12,(FRAME_T12*8)(sp)
stq ra,(FRAME_RA*8)(sp)
br pv,1f
1: LDGP(pv)
ldq a0,(FRAME_RA*8)(sp) /* a0 = ra */
ldq a1,(FRAME_T11*8)(sp) /* a1 = ai */
ldq a2,(FRAME_T12*8)(sp) /* a2 = pv */
CALL(console_restart)
call_pal PAL_halt
END(XentRestart)
/*
* exception_return: return from trap, exception, or syscall
*/
LEAF(exception_return, 1) /* XXX should be NESTED */
br pv, Ler1
Ler1: LDGP(pv)
ldq s0, PC_CURTHREAD(pcpup) /* save curthread in s0 */
#ifdef SMP
ldl s1, TD_MD_KERNNEST(s0)
subl s1, 1, s1 /* decrement nesting level */
#endif
ldq t1, (FRAME_PS * 8)(sp) /* get the saved PS */
and t1, ALPHA_PSL_USERMODE, t0 /* are we returning to user? */
beq t0, Lkernelret /* no: kernel return */
/* Handle any AST's or resched's. */
1: ldiq a0, ALPHA_PSL_IPL_HIGH /* disable all interrupts */
call_pal PAL_OSF1_swpipl
ldl s2, TD_FLAGS(s0) /* atomically with returning */
ldiq s3, TDF_ASTPENDING | TDF_NEEDRESCHED
and s2, s3
beq s2, 2f
ldiq a0, ALPHA_PSL_IPL_0 /* reenable interrupts */
call_pal PAL_OSF1_swpipl
mov sp, a0 /* only arg is frame */
CALL(ast)
jmp zero, 1b
2:
#ifdef SMP
br Lrestoreregs
#endif
Lkernelret:
#ifdef SMP
beq s1, Lrestoreregs
stq pcpup, (FRAME_T7*8)(sp) /* fixup pcpup */
#endif
Lrestoreregs:
/* set the hae register if this process has specified a value */
ldq t1, TD_MD_FLAGS(s0)
and t1, MDTD_HAEUSED
beq t1, Lnohae
ldq a0, TD_MD_HAE(t0)
ldq pv, chipset + CHIPSET_WRITE_HAE
CALL((pv))
Lnohae:
#ifdef SMP
/* leave the kernel */
stl s1, TD_MD_KERNNEST(s0)
#endif
/* restore the registers, and return */
bsr ra, exception_restore_regs /* jmp/CALL trashes pv/t12 */
ldq ra,(FRAME_RA*8)(sp)
.set noat
ldq at_reg,(FRAME_AT*8)(sp)
lda sp,(FRAME_SW_SIZE*8)(sp)
call_pal PAL_OSF1_rti
.set at
END(exception_return)
LEAF(exception_save_regs, 0)
stq v0,(FRAME_V0*8)(sp)
stq a3,(FRAME_A3*8)(sp)
stq a4,(FRAME_A4*8)(sp)
stq a5,(FRAME_A5*8)(sp)
stq s0,(FRAME_S0*8)(sp)
stq s1,(FRAME_S1*8)(sp)
stq s2,(FRAME_S2*8)(sp)
stq s3,(FRAME_S3*8)(sp)
stq s4,(FRAME_S4*8)(sp)
stq s5,(FRAME_S5*8)(sp)
stq s6,(FRAME_S6*8)(sp)
stq t0,(FRAME_T0*8)(sp)
stq t1,(FRAME_T1*8)(sp)
stq t2,(FRAME_T2*8)(sp)
stq t3,(FRAME_T3*8)(sp)
stq t4,(FRAME_T4*8)(sp)
stq t5,(FRAME_T5*8)(sp)
stq t6,(FRAME_T6*8)(sp)
stq t7,(FRAME_T7*8)(sp)
stq t8,(FRAME_T8*8)(sp)
stq t9,(FRAME_T9*8)(sp)
stq t10,(FRAME_T10*8)(sp)
stq t11,(FRAME_T11*8)(sp)
stq t12,(FRAME_T12*8)(sp)
.set noat
lda at_reg,(FRAME_SIZE*8)(sp)
stq at_reg,(FRAME_SP*8)(sp)
.set at
stq zero,(FRAME_FLAGS*8)(sp)
RET
END(exception_save_regs)
LEAF(exception_restore_regs, 0)
ldq v0,(FRAME_V0*8)(sp)
ldq a3,(FRAME_A3*8)(sp)
ldq a4,(FRAME_A4*8)(sp)
ldq a5,(FRAME_A5*8)(sp)
ldq s0,(FRAME_S0*8)(sp)
ldq s1,(FRAME_S1*8)(sp)
ldq s2,(FRAME_S2*8)(sp)
ldq s3,(FRAME_S3*8)(sp)
ldq s4,(FRAME_S4*8)(sp)
ldq s5,(FRAME_S5*8)(sp)
ldq s6,(FRAME_S6*8)(sp)
ldq t0,(FRAME_T0*8)(sp)
ldq t1,(FRAME_T1*8)(sp)
ldq t2,(FRAME_T2*8)(sp)
ldq t3,(FRAME_T3*8)(sp)
ldq t4,(FRAME_T4*8)(sp)
ldq t5,(FRAME_T5*8)(sp)
ldq t6,(FRAME_T6*8)(sp)
ldq t7,(FRAME_T7*8)(sp)
ldq t8,(FRAME_T8*8)(sp)
ldq t9,(FRAME_T9*8)(sp)
ldq t10,(FRAME_T10*8)(sp)
ldq t11,(FRAME_T11*8)(sp)
ldq t12,(FRAME_T12*8)(sp)
RET
END(exception_restore_regs)

415
sys/alpha/alpha/fp_emulate.c
View File

@ -1,415 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/sysent.h>
#include <sys/proc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <vm/vm_extern.h>
#include <vm/vm_object.h>
#include <vm/vm_pager.h>
#include <machine/fpu.h>
#include <machine/inst.h>
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <machine/reg.h>
#include <alpha/alpha/ieee_float.h>
#define GETREG(regs, i) (*(fp_register_t*) &regs->fpr_regs[i])
#define PUTREG(regs, i, v) (*(fp_register_t*) &regs->fpr_regs[i] = v)
typedef fp_register_t fp_opcode_handler(union alpha_instruction ins,
int src, int rnd,
u_int64_t fp_control,
u_int64_t *status,
struct fpreg *fpregs);
static fp_register_t fp_add(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_add(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
src, rnd, control, status);
}
static fp_register_t fp_sub(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_sub(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
src, rnd, control, status);
}
static fp_register_t fp_mul(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_mul(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
src, rnd, control, status);
}
static fp_register_t fp_div(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_div(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
src, rnd, control, status);
}
static fp_register_t fp_cmpun(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_cmpun(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
status);
}
static fp_register_t fp_cmpeq(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_cmpeq(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
status);
}
static fp_register_t fp_cmplt(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_cmplt(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
status);
}
static fp_register_t fp_cmple(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
return ieee_cmple(GETREG(fpregs, ins.f_format.fa),
GETREG(fpregs, ins.f_format.fb),
status);
}
static fp_register_t fp_cvts(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
switch (src) {
case T_FORMAT:
return ieee_convert_T_S(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
case Q_FORMAT:
return ieee_convert_Q_S(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
default:
*status |= FPCR_INV;
return GETREG(fpregs, ins.f_format.fc);
}
}
static fp_register_t fp_cvtt(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
switch (src) {
case S_FORMAT:
return ieee_convert_S_T(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
break;
case Q_FORMAT:
return ieee_convert_Q_T(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
break;
default:
*status |= FPCR_INV;
return GETREG(fpregs, ins.f_format.fc);
}
}
static fp_register_t fp_cvtq(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
switch (src) {
case S_FORMAT:
return ieee_convert_S_Q(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
break;
case T_FORMAT:
return ieee_convert_T_Q(GETREG(fpregs, ins.f_format.fb),
rnd, control, status);
break;
default:
*status |= FPCR_INV;
return GETREG(fpregs, ins.f_format.fc);
}
}
static fp_register_t fp_reserved(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
*status |= FPCR_INV;
return GETREG(fpregs, ins.f_format.fc);
}
static fp_register_t fp_cvtql(union alpha_instruction ins,
int src, int rnd,
u_int64_t control, u_int64_t *status,
struct fpreg *fpregs)
{
fp_register_t fb = GETREG(fpregs, ins.f_format.fb);
fp_register_t ret;
*status |= FPCR_INV;
ret.q = ((fb.q & 0xc0000000) << 32 | (fb.q & 0x3fffffff) << 29);
return ret;
}
static int fp_emulate(union alpha_instruction ins, struct thread *td)
{
u_int64_t control = td->td_pcb->pcb_fp_control;
struct fpreg *fpregs = &td->td_pcb->pcb_fp;
static fp_opcode_handler *ops[16] = {
fp_add, /* 0 */
fp_sub, /* 1 */
fp_mul, /* 2 */
fp_div, /* 3 */
fp_cmpun, /* 4 */
fp_cmpeq, /* 5 */
fp_cmplt, /* 6 */
fp_cmple, /* 7 */
fp_reserved, /* 8 */
fp_reserved, /* 9 */
fp_reserved, /* 10 */
fp_reserved, /* 11 */
fp_cvts, /* 12 */
fp_reserved, /* 13 */
fp_cvtt, /* 14 */
fp_cvtq, /* 15 */
};
int src, rnd;
fp_register_t result;
u_int64_t status;
/*
* Only attempt to emulate ieee instructions & integer overflow
*/
if ((ins.common.opcode != op_flti) &&
(ins.f_format.function != fltl_cvtqlsv)){
printf("fp_emulate: unhandled opcode = 0x%x, fun = 0x%x\n",ins.common.opcode,ins.f_format.function);
return 0;
}
/*
* Dump the float registers into the pcb so we can get at
* them. We are potentially going to modify the fp state, so
* cancel fpcurproc too.
*/
alpha_fpstate_save(td, 1);
/*
* Decode and execute the instruction.
*/
src = (ins.f_format.function >> 4) & 3;
rnd = (ins.f_format.function >> 6) & 3;
if (rnd == 3)
rnd = (fpregs->fpr_cr >> FPCR_DYN_SHIFT) & 3;
status = 0;
if (ins.common.opcode == op_fltl
&& ins.f_format.function == fltl_cvtqlsv)
result = fp_cvtql(ins, src, rnd, control, &status,
fpregs);
else
result = ops[ins.f_format.function & 0xf](ins, src, rnd,
control, &status,
fpregs);
/*
* Handle exceptions.
*/
if (status) {
u_int64_t fpcr;
/* Record the exception in the software control word. */
control |= (status >> IEEE_STATUS_TO_FPCR_SHIFT);
td->td_pcb->pcb_fp_control = control;
/* Regenerate the control register */
fpcr = fpregs->fpr_cr & (FPCR_DYN_MASK | FPCR_STATUS_MASK);
fpcr |= ((control & IEEE_STATUS_MASK)
<< IEEE_STATUS_TO_FPCR_SHIFT);
if (!(control & IEEE_TRAP_ENABLE_INV))
fpcr |= FPCR_INVD;
if (!(control & IEEE_TRAP_ENABLE_DZE))
fpcr |= FPCR_DZED;
if (!(control & IEEE_TRAP_ENABLE_OVF))
fpcr |= FPCR_OVFD;
if (!(control & IEEE_TRAP_ENABLE_UNF))
fpcr |= FPCR_UNFD;
if (!(control & IEEE_TRAP_ENABLE_INE))
fpcr |= FPCR_INED;
if (control & IEEE_STATUS_MASK)
fpcr |= FPCR_SUM;
fpregs->fpr_cr = fpcr;
/* Check the trap enable */
if ((control >> IEEE_STATUS_TO_EXCSUM_SHIFT)
& (control & IEEE_TRAP_ENABLE_MASK))
return 0;
}
PUTREG(fpregs, ins.f_format.fc, result);
return 1;
}
/*
* Attempt to complete a floating point instruction which trapped by
* emulating it in software. Return non-zero if the completion was
* successful, otherwise zero.
*/
int fp_software_completion(u_int64_t regmask, struct thread *td)
{
struct trapframe *frame = td->td_frame;
u_int64_t pc = frame->tf_regs[FRAME_PC];
int error;
/*
* First we must search back through the trap shadow to find which
* instruction was responsible for generating the trap.
*/
pc -= 4;
while (regmask) {
union alpha_instruction ins;
/*
* Read the instruction and figure out the destination
* register and opcode.
*/
error = copyin((caddr_t) pc, &ins, sizeof(ins));
if (error)
return 0;
switch (ins.common.opcode) {
case op_call_pal:
case op_jsr:
case op_br ... op_bgt:
/*
* Condition 6: the trap shadow may not
* include any branch instructions. Also,
* the trap shadow is bounded by EXCB, TRAPB
* and CALL_PAL.
*/
return 0;
case op_misc:
switch (ins.memory_format.function) {
case misc_trapb:
case misc_excb:
return 0;
}
break;
case op_inta:
case op_intl:
case op_ints:
/*
* The first 32 bits of the register mask
* represents integer registers which were
* modified in the trap shadow.
*/
regmask &= ~(1LL << ins.o_format.rc);
break;
case op_fltv:
case op_flti:
case op_fltl:
/*
* The second 32 bits of the register mask
* represents float registers which were
* modified in the trap shadow.
*/
regmask &= ~(1LL << (ins.f_format.fc + 32));
break;
}
if (regmask == 0) {
/*
* We have traced back through all the
* instructions in the trap shadow, so this
* must be the one which generated the trap.
*/
if (fp_emulate(ins, td)) {
/*
* Restore pc to the first instruction
* in the trap shadow.
*/
frame->tf_regs[FRAME_PC] = pc + 4;
return 1;
} else
return 0;
}
pc -= 4;
}
return 0;
}

101
sys/alpha/alpha/gdb_machdep.c
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@ -1,101 +0,0 @@
/*-
* Copyright (c) 2004 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kdb.h>
#include <sys/kernel.h>
#include <sys/signal.h>
#include <machine/gdb_machdep.h>
#include <machine/pcb.h>
#include <machine/reg.h>
#include <gdb/gdb.h>
void *
gdb_cpu_getreg(int regnum, size_t *regsz)
{
*regsz = gdb_cpu_regsz(regnum);
switch (regnum) {
case 9: return (&kdb_thrctx->pcb_context[0]);
case 10: return (&kdb_thrctx->pcb_context[1]);
case 11: return (&kdb_thrctx->pcb_context[2]);
case 12: return (&kdb_thrctx->pcb_context[3]);
case 13: return (&kdb_thrctx->pcb_context[4]);
case 14: return (&kdb_thrctx->pcb_context[5]);
case 15: return (&kdb_thrctx->pcb_context[6]);
case 30: return (&kdb_thrctx->pcb_hw.apcb_ksp);
case 64: return (&kdb_thrctx->pcb_context[7]);
}
return (NULL);
}
void
gdb_cpu_setreg(int regnum, void *val)
{
switch (regnum) {
}
}
int
gdb_cpu_signal(int entry, int code)
{
switch (entry) {
case ALPHA_KENTRY_INT:
case ALPHA_KENTRY_ARITH:
return (SIGILL); /* Can this happen? */
case ALPHA_KENTRY_MM:
switch (code) {
case ALPHA_MMCSR_INVALTRANS:
return (SIGSEGV);
case ALPHA_MMCSR_ACCESS:
case ALPHA_MMCSR_FOR:
case ALPHA_MMCSR_FOE:
case ALPHA_MMCSR_FOW:
return (SIGBUS);
}
case ALPHA_KENTRY_IF:
switch (code) {
case ALPHA_IF_CODE_BUGCHK:
case ALPHA_IF_CODE_BPT:
return (SIGTRAP);
case ALPHA_IF_CODE_GENTRAP:
case ALPHA_IF_CODE_FEN:
case ALPHA_IF_CODE_OPDEC:
return (SIGILL);
}
case ALPHA_KENTRY_UNA:
return (SIGSEGV);
case ALPHA_KENTRY_SYS:
return (SIGILL);
}
return (SIGILL);
}

178
sys/alpha/alpha/genassym.c
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@ -1,178 +0,0 @@
/*-
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)genassym.c 5.11 (Berkeley) 5/10/91
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/assym.h>
#include <sys/proc.h>
#include <sys/bio.h>
#include <sys/buf.h>
#include <sys/errno.h>
#include <sys/proc.h>
#include <sys/mount.h>
#include <sys/mutex.h>
#include <sys/socket.h>
#include <sys/resource.h>
#include <sys/resourcevar.h>
#include <sys/ktr.h>
#include <machine/frame.h>
#include <machine/chipset.h>
#include <machine/pcb.h>
#include <sys/vmmeter.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <net/if.h>
#include <netinet/in.h>
#include <nfs/nfsproto.h>
#include <nfs/rpcv2.h>
#include <nfsclient/nfs.h>
#include <nfsclient/nfsdiskless.h>
ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
ASSYM(PC_FPCURTHREAD, offsetof(struct pcpu, pc_fpcurthread));
ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
ASSYM(PC_CPUID, offsetof(struct pcpu, pc_cpuid));
ASSYM(PC_IDLEPCBPHYS, offsetof(struct pcpu, pc_idlepcbphys));
ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock));
ASSYM(MTX_RECURSE, offsetof(struct mtx, mtx_recurse));
ASSYM(MTX_UNOWNED, MTX_UNOWNED);
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
ASSYM(TDF_ASTPENDING, TDF_ASTPENDING);
ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);
ASSYM(TD_MD_FLAGS, offsetof(struct thread, td_md.md_flags));
ASSYM(TD_MD_PCBPADDR, offsetof(struct thread, td_md.md_pcbpaddr));
ASSYM(TD_MD_HAE, offsetof(struct thread, td_md.md_hae));
#ifdef SMP
ASSYM(TD_MD_KERNNEST, offsetof(struct thread, td_md.md_kernnest));
#endif
ASSYM(MDTD_HAEUSED, MDTD_HAEUSED);
ASSYM(CHIPSET_WRITE_HAE, offsetof(struct alpha_chipset, write_hae));
ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS);
ASSYM(PTLEV1I, PTLEV1I);
ASSYM(PTESIZE, PTESIZE);
ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
ASSYM(PCB_HWPCB_KSP, offsetof(struct pcb, pcb_hw.apcb_ksp));
ASSYM(PCB_CONTEXT, offsetof(struct pcb, pcb_context));
ASSYM(PCB_HW, offsetof(struct pcb, pcb_hw));
ASSYM(FPREG_FPR_REGS, offsetof(struct fpreg, fpr_regs));
ASSYM(FPREG_FPR_CR, offsetof(struct fpreg, fpr_cr));
ASSYM(EFAULT, EFAULT);
ASSYM(ENAMETOOLONG, ENAMETOOLONG);
/* Register offsets, for stack frames. */
ASSYM(FRAME_V0, FRAME_V0);
ASSYM(FRAME_T0, FRAME_T0);
ASSYM(FRAME_T1, FRAME_T1);
ASSYM(FRAME_T2, FRAME_T2);
ASSYM(FRAME_T3, FRAME_T3);
ASSYM(FRAME_T4, FRAME_T4);
ASSYM(FRAME_T5, FRAME_T5);
ASSYM(FRAME_T6, FRAME_T6);
ASSYM(FRAME_T7, FRAME_T7);
ASSYM(FRAME_S0, FRAME_S0);
ASSYM(FRAME_S1, FRAME_S1);
ASSYM(FRAME_S2, FRAME_S2);
ASSYM(FRAME_S3, FRAME_S3);
ASSYM(FRAME_S4, FRAME_S4);
ASSYM(FRAME_S5, FRAME_S5);
ASSYM(FRAME_S6, FRAME_S6);
ASSYM(FRAME_A3, FRAME_A3);
ASSYM(FRAME_A4, FRAME_A4);
ASSYM(FRAME_A5, FRAME_A5);
ASSYM(FRAME_T8, FRAME_T8);
ASSYM(FRAME_T9, FRAME_T9);
ASSYM(FRAME_T10, FRAME_T10);
ASSYM(FRAME_T11, FRAME_T11);
ASSYM(FRAME_RA, FRAME_RA);
ASSYM(FRAME_T12, FRAME_T12);
ASSYM(FRAME_AT, FRAME_AT);
ASSYM(FRAME_SP, FRAME_SP);
ASSYM(FRAME_FLAGS, FRAME_FLAGS);
ASSYM(FRAME_FLAGS_SYSCALL, FRAME_FLAGS_SYSCALL);
ASSYM(FRAME_SW_SIZE, FRAME_SW_SIZE);
ASSYM(FRAME_PS, FRAME_PS);
ASSYM(FRAME_PC, FRAME_PC);
ASSYM(FRAME_GP, FRAME_GP);
ASSYM(FRAME_A0, FRAME_A0);
ASSYM(FRAME_A1, FRAME_A1);
ASSYM(FRAME_A2, FRAME_A2);
ASSYM(FRAME_SIZE, FRAME_SIZE);
/* bits of the PS register */
ASSYM(ALPHA_PSL_USERMODE, ALPHA_PSL_USERMODE);
ASSYM(ALPHA_PSL_IPL_MASK, ALPHA_PSL_IPL_MASK);
ASSYM(ALPHA_PSL_IPL_0, ALPHA_PSL_IPL_0);
ASSYM(ALPHA_PSL_IPL_SOFT, ALPHA_PSL_IPL_SOFT);
ASSYM(ALPHA_PSL_IPL_HIGH, ALPHA_PSL_IPL_HIGH);
/* pte bits */
ASSYM(ALPHA_L1SHIFT, ALPHA_L1SHIFT);
ASSYM(ALPHA_L2SHIFT, ALPHA_L2SHIFT);
ASSYM(ALPHA_L3SHIFT, ALPHA_L3SHIFT);
ASSYM(ALPHA_K1SEG_BASE, ALPHA_K1SEG_BASE);
ASSYM(ALPHA_PTE_VALID, ALPHA_PTE_VALID);
ASSYM(ALPHA_PTE_ASM, ALPHA_PTE_ASM);
ASSYM(ALPHA_PTE_KR, ALPHA_PTE_KR);
ASSYM(ALPHA_PTE_KW, ALPHA_PTE_KW);
/* Kernel entries */
ASSYM(ALPHA_KENTRY_ARITH, ALPHA_KENTRY_ARITH);
ASSYM(ALPHA_KENTRY_MM, ALPHA_KENTRY_MM);
ASSYM(ALPHA_KENTRY_IF, ALPHA_KENTRY_IF);
ASSYM(ALPHA_KENTRY_UNA, ALPHA_KENTRY_UNA);
ASSYM(VPTBASE, VPTBASE);
ASSYM(KERNBASE, KERNBASE);

1525
sys/alpha/alpha/ieee_float.c
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File diff suppressed because it is too large Load Diff

102
sys/alpha/alpha/ieee_float.h
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@ -1,102 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#define S_FORMAT 0 /* IEEE single */
#define T_FORMAT 2 /* IEEE double */
#define Q_FORMAT 3 /* 64 bit fixed */
#define ROUND_CHOP 0 /* truncate fraction */
#define ROUND_MINUS_INF 1 /* round to -INF */
#define ROUND_NORMAL 2 /* round to nearest */
#define ROUND_PLUS_INF 3 /* round to +INF */
typedef union fp_register {
struct {
u_int64_t fraction: 52;
u_int64_t exponent: 11;
u_int64_t sign: 1;
} t;
u_int64_t q;
} fp_register_t;
fp_register_t
ieee_add(fp_register_t fa, fp_register_t fb,
int src, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_sub(fp_register_t fa, fp_register_t fb,
int src, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_mul(fp_register_t fa, fp_register_t fb,
int src, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_div(fp_register_t fa, fp_register_t fb,
int src, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_cmpun(fp_register_t fa, fp_register_t fb, u_int64_t *status);
fp_register_t
ieee_cmpeq(fp_register_t fa, fp_register_t fb, u_int64_t *status);
fp_register_t
ieee_cmplt(fp_register_t fa, fp_register_t fb, u_int64_t *status);
fp_register_t
ieee_cmple(fp_register_t fa, fp_register_t fb, u_int64_t *status);
fp_register_t
ieee_convert_S_T(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_convert_T_S(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_convert_Q_T(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_convert_Q_S(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_convert_T_Q(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);
fp_register_t
ieee_convert_S_Q(fp_register_t f, int rnd,
u_int64_t control, u_int64_t *status);

240
sys/alpha/alpha/in_cksum.c
View File

@ -1,240 +0,0 @@
/* $NetBSD: in_cksum.c,v 1.7 1997/09/02 13:18:15 thorpej Exp $ */
/*-
* Copyright (c) 1988, 1992, 1993
* The Regents of the University of California. All rights reserved.
* Copyright (c) 1996
* Matt Thomas <matt@3am-software.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)in_cksum.c 8.1 (Berkeley) 6/10/93
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/systm.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/ip.h>
#include <machine/in_cksum.h>
/*
* Checksum routine for Internet Protocol family headers
* (Portable Alpha version).
*
* This routine is very heavily used in the network
* code and should be modified for each CPU to be as fast as possible.
*/
#define ADDCARRY(x) (x > 65535 ? x -= 65535 : x)
#define REDUCE32 \
{ \
q_util.q = sum; \
sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
}
#define REDUCE16 \
{ \
q_util.q = sum; \
l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
sum = l_util.s[0] + l_util.s[1]; \
ADDCARRY(sum); \
}
static const u_int32_t in_masks[] = {
/*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/
0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF, /* offset 0 */
0x00000000, 0x0000FF00, 0x00FFFF00, 0xFFFFFF00, /* offset 1 */
0x00000000, 0x00FF0000, 0xFFFF0000, 0xFFFF0000, /* offset 2 */
0x00000000, 0xFF000000, 0xFF000000, 0xFF000000, /* offset 3 */
};
union l_util {
u_int16_t s[2];
u_int32_t l;
};
union q_util {
u_int16_t s[4];
u_int32_t l[2];
u_int64_t q;
};
static u_int64_t
in_cksumdata(const u_int32_t *lw, int len)
{
u_int64_t sum = 0;
u_int64_t prefilled;
int offset;
union q_util q_util;
if ((3 & (long) lw) == 0 && len == 20) {
sum = (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3] + lw[4];
REDUCE32;
return sum;
}
if ((offset = 3 & (long) lw) != 0) {
const u_int32_t *masks = in_masks + (offset << 2);
lw = (u_int32_t *) (((long) lw) - offset);
sum = *lw++ & masks[len >= 3 ? 3 : len];
len -= 4 - offset;
if (len <= 0) {
REDUCE32;
return sum;
}
}
#if 0
/*
* Force to cache line boundary.
*/
offset = 32 - (0x1f & (long) lw);
if (offset < 32 && len > offset) {
len -= offset;
if (4 & offset) {
sum += (u_int64_t) lw[0];
lw += 1;
}
if (8 & offset) {
sum += (u_int64_t) lw[0] + lw[1];
lw += 2;
}
if (16 & offset) {
sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3];
lw += 4;
}
}
#endif
/*
* access prefilling to start load of next cache line.
* then add current cache line
* save result of prefilling for loop iteration.
*/
prefilled = lw[0];
while ((len -= 32) >= 4) {
u_int64_t prefilling = lw[8];
sum += prefilled + lw[1] + lw[2] + lw[3]
+ lw[4] + lw[5] + lw[6] + lw[7];
lw += 8;
prefilled = prefilling;
}
if (len >= 0) {
sum += prefilled + lw[1] + lw[2] + lw[3]
+ lw[4] + lw[5] + lw[6] + lw[7];
lw += 8;
} else {
len += 32;
}
while ((len -= 16) >= 0) {
sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3];
lw += 4;
}
len += 16;
while ((len -= 4) >= 0) {
sum += (u_int64_t) *lw++;
}
len += 4;
if (len > 0)
sum += (u_int64_t) (in_masks[len] & *lw);
REDUCE32;
return sum;
}
u_short
in_addword(u_short a, u_short b)
{
u_int64_t sum = a + b;
ADDCARRY(sum);
return (sum);
}
u_short
in_pseudo(u_int32_t a, u_int32_t b, u_int32_t c)
{
u_int64_t sum;
union q_util q_util;
union l_util l_util;
sum = (u_int64_t) a + b + c;
REDUCE16;
return (sum);
}
u_short
in_cksum_skip(struct mbuf *m, int len, int skip)
{
u_int64_t sum = 0;
int mlen = 0;
int clen = 0;
caddr_t addr;
union q_util q_util;
union l_util l_util;
len -= skip;
for (; skip && m; m = m->m_next) {
if (m->m_len > skip) {
mlen = m->m_len - skip;
addr = mtod(m, caddr_t) + skip;
goto skip_start;
} else {
skip -= m->m_len;
}
}
for (; m && len; m = m->m_next) {
if (m->m_len == 0)
continue;
mlen = m->m_len;
addr = mtod(m, caddr_t);
skip_start:
if (len < mlen)
mlen = len;
if ((clen ^ (long) addr) & 1)
sum += in_cksumdata((const u_int32_t *)addr, mlen) << 8;
else
sum += in_cksumdata((const u_int32_t *)addr, mlen);
clen += mlen;
len -= mlen;
}
REDUCE16;
return (~sum & 0xffff);
}
u_int in_cksum_hdr(const struct ip *ip)
{
u_int64_t sum = in_cksumdata((const u_int32_t *)ip, sizeof(struct ip));
union q_util q_util;
union l_util l_util;
REDUCE16;
return (~sum & 0xffff);
}

509
sys/alpha/alpha/interrupt.c
View File

@ -1,509 +0,0 @@
/* $NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $ */
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Authors: Keith Bostic, Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center.
* Redistribute and modify at will, leaving only this additional copyright
* notice.
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
/* __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $");*/
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/kdb.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/sched.h>
#include <sys/smp.h>
#include <sys/unistd.h>
#include <sys/vmmeter.h>
#include <machine/bwx.h>
#include <machine/cpuconf.h>
#include <machine/frame.h>
#include <machine/intr.h>
#include <machine/md_var.h>
#include <machine/reg.h>
#include <machine/rpb.h>
#include <machine/smp.h>
#ifdef EVCNT_COUNTERS
struct evcnt clock_intr_evcnt; /* event counter for clock intrs. */
#else
#include <machine/intrcnt.h>
#endif
volatile int mc_expected, mc_received;
static void
dummy_perf(unsigned long vector, struct trapframe *framep)
{
printf("performance interrupt!\n");
}
void (*perf_irq)(unsigned long, struct trapframe *) = dummy_perf;
static u_int schedclk2;
static void alpha_clock_interrupt(struct trapframe *framep);
void
interrupt(a0, a1, a2, framep)
unsigned long a0, a1, a2;
struct trapframe *framep;
{
struct thread *td;
#ifdef SMP
register_t s;
#endif
/*
* Find our per-cpu globals.
*/
#ifdef SMP
s = intr_disable();
#endif
pcpup = (struct pcpu *) alpha_pal_rdval();
td = curthread;
#ifdef SMP
td->td_md.md_kernnest++;
intr_restore(s);
#endif
atomic_add_int(&td->td_intr_nesting_level, 1);
#if KSTACK_GUARD_PAGES == 0
#ifndef SMP
{
if ((caddr_t) framep < (caddr_t) td->td_pcb + 1024) {
panic("possible stack overflow\n");
}
}
#endif
#endif
framep->tf_regs[FRAME_TRAPARG_A0] = a0;
framep->tf_regs[FRAME_TRAPARG_A1] = a1;
framep->tf_regs[FRAME_TRAPARG_A2] = a2;
switch (a0) {
#ifdef SMP
case ALPHA_INTR_XPROC: /* interprocessor interrupt */
CTR0(KTR_INTR|KTR_SMP, "interprocessor interrupt");
smp_handle_ipi(framep); /* note: lock not taken */
break;
#endif
case ALPHA_INTR_CLOCK: /* clock interrupt */
CTR0(KTR_INTR, "clock interrupt");
alpha_clock_interrupt(framep);
break;
case ALPHA_INTR_ERROR: /* Machine Check or Correctable Error */
a0 = alpha_pal_rdmces();
if (platform.mcheck_handler)
(*platform.mcheck_handler)(a0, framep, a1, a2);
else
machine_check(a0, framep, a1, a2);
break;
case ALPHA_INTR_DEVICE: /* I/O device interrupt */
PCPU_LAZY_INC(cnt.v_intr);
if (platform.iointr)
(*platform.iointr)(framep, a1);
break;
case ALPHA_INTR_PERF: /* interprocessor interrupt */
perf_irq(a1, framep);
break;
case ALPHA_INTR_PASSIVE:
#if 0
printf("passive release interrupt vec 0x%lx (ignoring)\n", a1);
#endif
break;
default:
panic("unexpected interrupt: type 0x%lx vec 0x%lx a2 0x%lx\n",
a0, a1, a2);
/* NOTREACHED */
}
atomic_subtract_int(&td->td_intr_nesting_level, 1);
}
void
set_iointr(niointr)
void (*niointr)(void *, unsigned long);
{
if (platform.iointr)
panic("set iointr twice");
platform.iointr = niointr;
}
void
machine_check(mces, framep, vector, param)
unsigned long mces;
struct trapframe *framep;
unsigned long vector, param;
{
const char *type;
/* Make sure it's an error we know about. */
if ((mces & (ALPHA_MCES_MIP|ALPHA_MCES_SCE|ALPHA_MCES_PCE)) == 0) {
type = "fatal machine check or error (unknown type)";
goto fatal;
}
/* Machine checks. */
if (mces & ALPHA_MCES_MIP) {
/* If we weren't expecting it, then we punt. */
if (!mc_expected) {
type = "unexpected machine check";
goto fatal;
}
mc_expected = 0;
mc_received = 1;
}
/* System correctable errors. */
if (mces & ALPHA_MCES_SCE)
printf("Warning: received system correctable error.\n");
/* Processor correctable errors. */
if (mces & ALPHA_MCES_PCE)
printf("Warning: received processor correctable error.\n");
/* Clear pending machine checks and correctable errors */
alpha_pal_wrmces(mces);
return;
fatal:
/* Clear pending machine checks and correctable errors */
alpha_pal_wrmces(mces);
printf("\n");
printf("%s:\n", type);
printf("\n");
printf(" mces = 0x%lx\n", mces);
printf(" vector = 0x%lx\n", vector);
printf(" param = 0x%lx\n", param);
printf(" pc = 0x%lx\n", framep->tf_regs[FRAME_PC]);
printf(" ra = 0x%lx\n", framep->tf_regs[FRAME_RA]);
printf(" curproc = %p\n", curproc);
if (curproc != NULL)
printf(" pid = %d, comm = %s\n", curproc->p_pid,
curproc->p_comm);
printf("\n");
#ifdef KDB
kdb_trap(ALPHA_KENTRY_MM, mces, framep);
#endif
panic("machine check");
}
int
badaddr(addr, size)
void *addr;
size_t size;
{
return(badaddr_read(addr, size, NULL));
}
int
badaddr_read(addr, size, rptr)
void *addr;
size_t size;
void *rptr;
{
long rcpt;
/* Get rid of any stale machine checks that have been waiting. */
alpha_pal_draina();
/* Tell the trap code to expect a machine check. */
mc_received = 0;
mc_expected = 1;
/* Read from the test address, and make sure the read happens. */
alpha_mb();
switch (size) {
case sizeof (u_int8_t):
if (alpha_implver() >= ALPHA_IMPLVER_EV5
&& alpha_amask(ALPHA_AMASK_BWX) == 0)
rcpt = ldbu((vm_offset_t)addr);
else
rcpt = *(volatile u_int8_t *)addr;
break;
case sizeof (u_int16_t):
if (alpha_implver() >= ALPHA_IMPLVER_EV5
&& alpha_amask(ALPHA_AMASK_BWX) == 0)
rcpt = ldwu((vm_offset_t)addr);
else
rcpt = *(volatile u_int16_t *)addr;
break;
case sizeof (u_int32_t):
rcpt = *(volatile u_int32_t *)addr;
break;
case sizeof (u_int64_t):
rcpt = *(volatile u_int64_t *)addr;
break;
default:
panic("badaddr: invalid size (%ld)\n", size);
}
alpha_mb();
alpha_mb(); /* magic for ev5 2100A & maybe more */
/* Make sure we took the machine check, if we caused one. */
alpha_pal_draina();
/* disallow further machine checks */
mc_expected = 0;
if (rptr && mc_received == 0) {
switch (size) {
case sizeof (u_int8_t):
*(volatile u_int8_t *)rptr = rcpt;
break;
case sizeof (u_int16_t):
*(volatile u_int16_t *)rptr = rcpt;
break;
case sizeof (u_int32_t):
*(volatile u_int32_t *)rptr = rcpt;
break;
case sizeof (u_int64_t):
*(volatile u_int64_t *)rptr = rcpt;
break;
}
}
/* Return non-zero (i.e. true) if it's a bad address. */
return (mc_received);
}
#define HASHVEC(vector) ((vector) % 31)
LIST_HEAD(alpha_intr_list, alpha_intr);
struct alpha_intr {
LIST_ENTRY(alpha_intr) list; /* chain handlers in this hash bucket */
uintptr_t vector; /* vector to match */
struct intr_event *ie; /* interrupt event structure */
volatile long *cntp; /* interrupt counter */
void (*disable)(uintptr_t);
};
static struct mtx alpha_intr_hash_lock;
static struct alpha_intr_list alpha_intr_hash[31];
static void ithds_init(void *dummy);
static void
ithds_init(void *dummy)
{
mtx_init(&alpha_intr_hash_lock, "intr table", NULL, MTX_SPIN);
}
SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
int
alpha_setup_intr(const char *name, uintptr_t vector, driver_intr_t handler, void *arg,
enum intr_type flags, void **cookiep, volatile long *cntp,
void (*disable)(uintptr_t), void (*enable)(uintptr_t))
{
int h = HASHVEC(vector);
struct alpha_intr *i;
int errcode;
/*
* XXX - Can we have more than one device on a vector? If so, we have
* a race condition here that needs to be worked around similar to
* the fashion done in the i386 inthand_add() function.
*/
/* First, check for an existing hash table entry for this vector. */
mtx_lock_spin(&alpha_intr_hash_lock);
for (i = LIST_FIRST(&alpha_intr_hash[h]); i && i->vector != vector;
i = LIST_NEXT(i, list))
; /* nothing */
mtx_unlock_spin(&alpha_intr_hash_lock);
if (i == NULL) {
/* None was found, so create an entry. */
i = malloc(sizeof(struct alpha_intr), M_DEVBUF, M_NOWAIT);
if (i == NULL)
return ENOMEM;
i->vector = vector;
i->cntp = cntp;
i->disable = disable;
errcode = intr_event_create(&i->ie, (void *)vector, 0,
(void (*)(void *))enable, "intr:");
if (errcode) {
free(i, M_DEVBUF);
return errcode;
}
mtx_lock_spin(&alpha_intr_hash_lock);
LIST_INSERT_HEAD(&alpha_intr_hash[h], i, list);
mtx_unlock_spin(&alpha_intr_hash_lock);
}
/* Second, add this handler. */
return (intr_event_add_handler(i->ie, name, handler, arg,
intr_priority(flags), flags, cookiep));
}
int
alpha_teardown_intr(void *cookie)
{
return (intr_event_remove_handler(cookie));
}
/*
* XXX: Alpha doesn't count stray interrupts like some of the other archs.
*/
void
alpha_dispatch_intr(void *frame, unsigned long vector)
{
int h = HASHVEC(vector);
struct alpha_intr *i;
struct intr_event *ie;
struct intr_handler *ih;
int error, thread;
/*
* Walk the hash bucket for this vector looking for this vector's
* interrupt structure.
*/
for (i = LIST_FIRST(&alpha_intr_hash[h]); i && i->vector != vector;
i = LIST_NEXT(i, list))
; /* nothing */
/* No interrupt structure for this vector. */
if (i == NULL)
return;
ie = i->ie;
KASSERT(ie != NULL, ("interrupt structure without an event"));
/*
* As an optimization, if an event has no handlers, don't
* schedule it to run.
*/
if (TAILQ_EMPTY(&ie->ie_handlers))
return;
atomic_add_long(i->cntp, 1);
/*
* It seems that we need to return from an interrupt back to PAL
* on the same CPU that received the interrupt, so pin the interrupted
* thread to the current CPU until we return from the interrupt.
*/
sched_pin();
/* Execute all fast interrupt handlers directly. */
thread = 0;
critical_enter();
TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
if (!(ih->ih_flags & IH_FAST)) {
thread = 1;
continue;
}
CTR4(KTR_INTR, "%s: exec %p(%p) for %s", __func__,
ih->ih_handler, ih->ih_argument, ih->ih_name);
ih->ih_handler(ih->ih_argument);
}
critical_exit();
/*
* If the ithread needs to run, disable the source and schedule the
* thread.
*/
if (thread) {
if (i->disable) {
CTR1(KTR_INTR,
"alpha_dispatch_intr: disabling vector 0x%x",
i->vector);
i->disable(i->vector);
}
error = intr_event_schedule_thread(ie);
KASSERT(error == 0, ("got an impossible stray interrupt"));
}
sched_unpin();
}
static void
alpha_clock_interrupt(struct trapframe *framep)
{
PCPU_LAZY_INC(cnt.v_intr);
#ifdef EVCNT_COUNTERS
clock_intr_evcnt.ev_count++;
#else
intrcnt[INTRCNT_CLOCK]++;
#endif
if (platform.clockintr) {
critical_enter();
#ifdef SMP
/*
* Only one processor drives the actual timer.
*/
if (PCPU_GET(cpuid) == 0) {
#endif
(*platform.clockintr)(TRAPF_USERMODE(framep),
TRAPF_PC(framep));
/* Bump stathz divider. */
schedclk2++;
#ifdef SMP
} else
hardclock_cpu(TRAPF_USERMODE(framep));
#endif
if (profprocs != 0)
profclock(TRAPF_USERMODE(framep), TRAPF_PC(framep));
/* divide hz (1024) by 8 to get stathz (128) */
if ((schedclk2 & 0x7) == 0)
statclock(TRAPF_USERMODE(framep));
critical_exit();
}
}

372
sys/alpha/alpha/locore.s
View File

@ -1,372 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include "opt_compat.h"
#include <machine/asm.h>
#include <sys/syscall.h>
#include <assym.s>
#ifndef EVCNT_COUNTERS
#define _LOCORE
#include <machine/intrcnt.h>
#endif
/*
* PTmap is recursive pagemap at top of virtual address space.
* Within PTmap, the lev1 and lev0 page tables can be found.
*/
.globl PTmap,PTlev2,PTlev1,PTlev1pte
.equ PTmap,VPTBASE
.equ PTlev2,PTmap + (PTLEV1I << ALPHA_L2SHIFT)
.equ PTlev1,PTlev2 + (PTLEV1I << ALPHA_L3SHIFT)
.equ PTlev1pte,PTlev1 + (PTLEV1I * PTESIZE)
.globl kernbase
.equ kernbase,KERNBASE
/*
* Perform actions necessary to switch to a new context. The
* hwpcb should be in a0.
*/
#define SWITCH_CONTEXT \
/* Make a note of the context we're running on. */ \
stq a0, PC_CURPCB(pcpup); \
\
/* Swap in the new context. */ \
call_pal PAL_OSF1_swpctx
.text
NESTED(locorestart, 1, 0, ra, 0, 0)
br pv,1f
1: LDGP(pv)
/* Load KGP with current GP. */
or a0,zero,s0 /* save pfn */
or gp,zero,a0
call_pal PAL_OSF1_wrkgp /* clobbers a0, t0, t8-t11 */
or s0,zero,a0 /* restore pfn */
/*
* Call alpha_init() to do pre-main initialization.
* alpha_init() gets the arguments we were called with,
* which are already in a0, a1, a2, a3, and a4.
*/
CALL(alpha_init)
/* Set up the virtual page table pointer. */
ldiq a0, VPTBASE
call_pal PAL_OSF1_wrvptptr /* clobbers a0, t0, t8-t11 */
/*
* Initialise pcpup.
*/
call_pal PAL_OSF1_rdval /* clobbers t0, t8-t11 */
mov v0, pcpup
/*
* Switch to proc0's PCB.
*/
lda t0,thread0 /* get phys addr of pcb */
ldq a0,TD_MD_PCBPADDR(t0)
SWITCH_CONTEXT
/*
* We've switched to a new page table base, so invalidate the TLB
* and I-stream. This happens automatically everywhere but here.
*/
ldiq a0, -2 /* TBIA */
call_pal PAL_OSF1_tbi
call_pal PAL_imb
CALL(mi_startup) /* go to mi_startup()! */
/* NOTREACHED */
END(locorestart)
#ifdef SMP
/*
* Secondary processors start executing here. They will have their
* unique value set to point at the per-cpu structure and will
* be executing on their private idle stack.
*/
NESTED(smp_init_secondary_glue, 1, 0, ra, 0, 0)
br pv, 1f
1: LDGP(pv)
call_pal PAL_rdunique /* initialise pcpup */
mov v0, pcpup
ldq a0, PC_IDLEPCBPHYS(pcpup) /* switch to idle ctx */
call_pal PAL_OSF1_swpctx
/* Load KGP with current GP. */
or gp,zero,a0
call_pal PAL_OSF1_wrkgp /* clobbers a0, t0, t8-t11 */
CALL(smp_init_secondary) /* never returns */
/* NOTREACHED */
call_pal PAL_halt
END(smp_init_secondary_glue)
#endif
/**************************************************************************/
/*
* Signal "trampoline" code. Invoked from RTE setup by sendsig().
*
* On entry, stack & registers look like:
*
* a0 signal number
* a1 pointer to siginfo_t
* a2 pointer to signal context frame (scp)
* a3 address of handler
* sp+0 saved hardware state
* .
* .
* scp+0 beginning of signal context frame
*/
NESTED(sigcode,0,0,ra,0,0)
lda sp, -16(sp) /* save the sigcontext pointer */
stq a2, 0(sp)
jsr ra, (t12) /* call the signal handler (t12==pv) */
ldq a0, 0(sp) /* get the sigcontext pointer */
lda sp, 16(sp)
ldiq v0, SYS_sigreturn
call_pal PAL_OSF1_callsys /* and call sigreturn() with it. */
mov v0, a0 /* if that failed, get error code */
ldiq v0, SYS_exit
call_pal PAL_OSF1_callsys /* and call exit() with it. */
END(sigcode)
#ifdef COMPAT_43
NESTED(osigcode,0,0,ra,0,0)
lda sp, -16(sp) /* save the sigcontext pointer */
stq a2, 0(sp)
jsr ra, (t12) /* call the signal handler (t12==pv) */
ldq a0, 0(sp) /* get the sigcontext pointer */
lda sp, 16(sp)
ldiq v0, 103 /* Old 3.x SYS_sigreturn */
call_pal PAL_OSF1_callsys /* and call sigreturn() with it. */
mov v0, a0 /* if that failed, get error code */
ldiq v0, SYS_exit
call_pal PAL_OSF1_callsys /* and call exit() with it. */
END(osigcode)
#endif
#ifdef COMPAT_FREEBSD4
NESTED(freebsd4_sigcode,0,0,ra,0,0)
lda sp, -16(sp) /* save the sigcontext pointer */
stq a2, 0(sp)
jsr ra, (t12) /* call the signal handler (t12==pv) */
ldq a0, 0(sp) /* get the sigcontext pointer */
lda sp, 16(sp)
ldiq v0, 344 /* Old 4.x SYS_sigreturn */
call_pal PAL_OSF1_callsys /* and call sigreturn() with it. */
mov v0, a0 /* if that failed, get error code */
ldiq v0, SYS_exit
call_pal PAL_OSF1_callsys /* and call exit() with it. */
END(freebsd4_sigcode)
#endif
EXPORT(esigcode) /* end of all sigcode */
.data
EXPORT(szsigcode)
.long esigcode-sigcode
#ifdef COMPAT_43
EXPORT(szosigcode)
.long esigcode-osigcode
#endif
#ifdef COMPAT_FREEBSD4
EXPORT(szfreebsd4_sigcode)
.long esigcode-freebsd4_sigcode
#endif
.text
/**************************************************************************/
/*
* savefpstate: Save a process's floating point state.
*
* Arguments:
* a0 'struct fpstate *' to save into
*/
LEAF(savefpstate, 1)
LDGP(pv)
/* save all of the FP registers */
lda t1, FPREG_FPR_REGS(a0) /* get address of FP reg. save area */
stt $f0, (0 * 8)(t1) /* save first register, using hw name */
stt $f1, (1 * 8)(t1) /* etc. */
stt $f2, (2 * 8)(t1)
stt $f3, (3 * 8)(t1)
stt $f4, (4 * 8)(t1)
stt $f5, (5 * 8)(t1)
stt $f6, (6 * 8)(t1)
stt $f7, (7 * 8)(t1)
stt $f8, (8 * 8)(t1)
stt $f9, (9 * 8)(t1)
stt $f10, (10 * 8)(t1)
stt $f11, (11 * 8)(t1)
stt $f12, (12 * 8)(t1)
stt $f13, (13 * 8)(t1)
stt $f14, (14 * 8)(t1)
stt $f15, (15 * 8)(t1)
stt $f16, (16 * 8)(t1)
stt $f17, (17 * 8)(t1)
stt $f18, (18 * 8)(t1)
stt $f19, (19 * 8)(t1)
stt $f20, (20 * 8)(t1)
stt $f21, (21 * 8)(t1)
stt $f22, (22 * 8)(t1)
stt $f23, (23 * 8)(t1)
stt $f24, (24 * 8)(t1)
stt $f25, (25 * 8)(t1)
stt $f26, (26 * 8)(t1)
stt $f27, (27 * 8)(t1)
stt $f28, (28 * 8)(t1)
stt $f29, (29 * 8)(t1)
stt $f30, (30 * 8)(t1)
/*
* Then save the FPCR; note that the necessary 'trapb's are taken
* care of on kernel entry and exit.
*/
mf_fpcr ft0
stt ft0, FPREG_FPR_CR(a0) /* store to FPCR save area */
RET
END(savefpstate)
/**************************************************************************/
/*
* restorefpstate: Restore a process's floating point state.
*
* Arguments:
* a0 'struct fpstate *' to restore from
*/
LEAF(restorefpstate, 1)
LDGP(pv)
/*
* Restore the FPCR; note that the necessary 'trapb's are taken care of
* on kernel entry and exit.
*/
ldt ft0, FPREG_FPR_CR(a0) /* load from FPCR save area */
mt_fpcr ft0
/* Restore all of the FP registers. */
lda t1, FPREG_FPR_REGS(a0) /* get address of FP reg. save area */
ldt $f0, (0 * 8)(t1) /* restore first reg., using hw name */
ldt $f1, (1 * 8)(t1) /* etc. */
ldt $f2, (2 * 8)(t1)
ldt $f3, (3 * 8)(t1)
ldt $f4, (4 * 8)(t1)
ldt $f5, (5 * 8)(t1)
ldt $f6, (6 * 8)(t1)
ldt $f7, (7 * 8)(t1)
ldt $f8, (8 * 8)(t1)
ldt $f9, (9 * 8)(t1)
ldt $f10, (10 * 8)(t1)
ldt $f11, (11 * 8)(t1)
ldt $f12, (12 * 8)(t1)
ldt $f13, (13 * 8)(t1)
ldt $f14, (14 * 8)(t1)
ldt $f15, (15 * 8)(t1)
ldt $f16, (16 * 8)(t1)
ldt $f17, (17 * 8)(t1)
ldt $f18, (18 * 8)(t1)
ldt $f19, (19 * 8)(t1)
ldt $f20, (20 * 8)(t1)
ldt $f21, (21 * 8)(t1)
ldt $f22, (22 * 8)(t1)
ldt $f23, (23 * 8)(t1)
ldt $f24, (24 * 8)(t1)
ldt $f25, (25 * 8)(t1)
ldt $f26, (26 * 8)(t1)
ldt $f27, (27 * 8)(t1)
ldt $f28, (28 * 8)(t1)
ldt $f29, (29 * 8)(t1)
ldt $f30, (30 * 8)(t1)
RET
END(restorefpstate)
/* XXX: make systat/vmstat happy */
.data
EXPORT(intrnames)
.asciz "clock"
intr_n = 0
.rept INTRCNT_COUNT
.ascii "intr "
.byte intr_n / 10 + '0, intr_n % 10 + '0
.asciz " " # space for platform-specific rewrite
intr_n = intr_n + 1
.endr
EXPORT(eintrnames)
.align 3
EXPORT(intrcnt)
.fill INTRCNT_COUNT + 1, 8, 0
EXPORT(eintrcnt)
.text

2432
sys/alpha/alpha/machdep.c
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File diff suppressed because it is too large Load Diff

170
sys/alpha/alpha/mem.c
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@ -1,170 +0,0 @@
/*-
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department, and code derived from software contributed to
* Berkeley by William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah $Hdr: mem.c 1.13 89/10/08$
* from: @(#)mem.c 7.2 (Berkeley) 5/9/91
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Memory special file
*/
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/fcntl.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/memrange.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/msgbuf.h>
#include <sys/systm.h>
#include <sys/signalvar.h>
#include <sys/uio.h>
#include <machine/md_var.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <machine/memdev.h>
struct mem_range_softc mem_range_softc;
/* ARGSUSED */
int
memrw(struct cdev *dev, struct uio *uio, int flags)
{
vm_offset_t o, v;
int c = 0;
struct iovec *iov;
int error = 0, rw;
vm_offset_t addr, eaddr;
GIANT_REQUIRED;
while (uio->uio_resid > 0 && !error) {
iov = uio->uio_iov;
if (iov->iov_len == 0) {
uio->uio_iov++;
uio->uio_iovcnt--;
if (uio->uio_iovcnt < 0)
panic("memrw");
continue;
}
if (minor(dev) == CDEV_MINOR_MEM) {
v = uio->uio_offset;
kmemphys:
/* Allow reads only in RAM. */
rw = (uio->uio_rw == UIO_READ) ? VM_PROT_READ : VM_PROT_WRITE;
if ((alpha_pa_access(v) & rw) != rw) {
error = EFAULT;
c = 0;
break;
}
o = uio->uio_offset & PAGE_MASK;
c = min(uio->uio_resid, (int)(PAGE_SIZE - o));
error =
uiomove((caddr_t)ALPHA_PHYS_TO_K0SEG(v), c, uio);
continue;
}
else if (minor(dev) == CDEV_MINOR_KMEM) {
v = uio->uio_offset;
if (v >= ALPHA_K0SEG_BASE && v <= ALPHA_K0SEG_END) {
v = ALPHA_K0SEG_TO_PHYS(v);
goto kmemphys;
}
c = min(iov->iov_len, MAXPHYS);
/*
* Make sure that all of the pages are currently
* resident so that we don't create any zero-fill
* pages.
*/
addr = trunc_page(v);
eaddr = round_page(v + c);
for (; addr < eaddr; addr += PAGE_SIZE)
if (pmap_extract(kernel_pmap, addr) == 0) {
return EFAULT;
}
if (!kernacc((caddr_t)v, c,
uio->uio_rw == UIO_READ ?
VM_PROT_READ : VM_PROT_WRITE)) {
return (EFAULT);
}
error = uiomove((caddr_t)v, c, uio);
continue;
}
/* else panic! */
}
return (error);
}
/*
* allow user processes to MMAP some memory sections
* instead of going through read/write
*/
int
memmmap(struct cdev *dev, vm_offset_t offset, vm_paddr_t *paddr, int prot)
{
/*
* /dev/mem is the only one that makes sense through this
* interface. For /dev/kmem any physaddr we return here
* could be transient and hence incorrect or invalid at
* a later time.
*/
if (minor(dev) != CDEV_MINOR_MEM)
return (-1);
/*
* Allow access only in RAM.
*/
if ((prot & alpha_pa_access(atop((vm_offset_t)offset))) != prot)
return (-1);
*paddr = ALPHA_PHYS_TO_K0SEG(offset);
return (0);
}
void
dev_mem_md_init(void)
{
}

599
sys/alpha/alpha/mp_machdep.c
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@ -1,599 +0,0 @@
/*-
* Copyright (c) 2000 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_kstack_pages.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ktr.h>
#include <sys/proc.h>
#include <sys/cons.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/kernel.h>
#include <sys/pcpu.h>
#include <sys/smp.h>
#include <sys/sysctl.h>
#include <sys/bus.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <machine/atomic.h>
#include <machine/clock.h>
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <machine/pmap.h>
#include <machine/prom.h>
#include <machine/rpb.h>
#include <machine/smp.h>
/* Set to 1 once we're ready to let the APs out of the pen. */
static volatile int aps_ready = 0;
static struct mtx ap_boot_mtx;
u_int64_t boot_cpu_id;
struct pcb stoppcbs[MAXCPU];
static void release_aps(void *dummy);
static int smp_cpu_enabled(struct pcs *pcsp);
extern void smp_init_secondary_glue(void);
static int smp_send_secondary_command(const char *command, int pal_id);
static int smp_start_secondary(int pal_id, int cpuid);
/*
* Communicate with a console running on a secondary processor.
* Return 1 on failure.
*/
static int
smp_send_secondary_command(const char *command, int pal_id)
{
u_int64_t mask = 1L << pal_id;
struct pcs *cpu = LOCATE_PCS(hwrpb, pal_id);
int i, len;
/*
* Sanity check.
*/
len = strlen(command);
if (len > sizeof(cpu->pcs_buffer.rxbuf)) {
printf("smp_send_secondary_command: command '%s' too long\n",
command);
return 0;
}
/*
* Wait for the rx bit to clear.
*/
for (i = 0; i < 100000; i++) {
if (!(hwrpb->rpb_rxrdy & mask))
break;
DELAY(10);
}
if (hwrpb->rpb_rxrdy & mask)
return 0;
/*
* Write the command into the processor's buffer.
*/
bcopy(command, cpu->pcs_buffer.rxbuf, len);
cpu->pcs_buffer.rxlen = len;
/*
* Set the bit in the rxrdy mask and let the secondary try to
* handle the command.
*/
atomic_set_64(&hwrpb->rpb_rxrdy, mask);
/*
* Wait for the rx bit to clear.
*/
for (i = 0; i < 100000; i++) {
if (!(hwrpb->rpb_rxrdy & mask))
break;
DELAY(10);
}
if (hwrpb->rpb_rxrdy & mask)
return 0;
return 1;
}
void
smp_init_secondary(void)
{
struct pcs *cpu;
/* spin until all the AP's are ready */
while (!aps_ready)
/*spin*/ ;
/*
* Record the pcpu pointer in the per-cpu system value.
*/
alpha_pal_wrval((u_int64_t) pcpup);
/* Clear userland thread pointer. */
alpha_pal_wrunique(0);
/* Initialize curthread. */
KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
PCPU_SET(curthread, PCPU_GET(idlethread));
/*
* Point interrupt/exception vectors to our own.
*/
alpha_pal_wrent(XentInt, ALPHA_KENTRY_INT);
alpha_pal_wrent(XentArith, ALPHA_KENTRY_ARITH);
alpha_pal_wrent(XentMM, ALPHA_KENTRY_MM);
alpha_pal_wrent(XentIF, ALPHA_KENTRY_IF);
alpha_pal_wrent(XentUna, ALPHA_KENTRY_UNA);
alpha_pal_wrent(XentSys, ALPHA_KENTRY_SYS);
/* lower the ipl and take any pending machine check */
mc_expected = 1;
alpha_mb(); alpha_mb();
alpha_pal_wrmces(7);
(void)alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH);
mc_expected = 0;
/*
* Set flags in our per-CPU slot in the HWRPB.
*/
cpu = LOCATE_PCS(hwrpb, PCPU_GET(pal_id));
cpu->pcs_flags &= ~PCS_BIP;
cpu->pcs_flags |= PCS_RC;
alpha_mb();
/*
* XXX: doesn't idleproc already have a pcb from when it was
* kthread_create'd?
*
* cache idleproc's physical address.
*/
curthread->td_md.md_pcbpaddr = (struct pcb *)PCPU_GET(idlepcbphys);
/*
* and make idleproc's trapframe pointer point to its
* stack pointer for sanity.
*/
curthread->td_frame =
(struct trapframe *)PCPU_PTR(idlepcb)->apcb_ksp;
mtx_lock_spin(&ap_boot_mtx);
smp_cpus++;
CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
/* Build our map of 'other' CPUs. */
PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
if (smp_cpus == mp_ncpus) {
smp_started = 1;
smp_active = 1;
}
mtx_unlock_spin(&ap_boot_mtx);
while (smp_started == 0)
; /* nothing */
/* ok, now grab sched_lock and enter the scheduler */
mtx_lock_spin(&sched_lock);
/*
* Correct spinlock nesting. The idle thread context that we are
* borrowing was created so that it would start out with a single
* spin lock (sched_lock) held in fork_trampoline(). Since we've
* explicitly acquired locks in this function, the nesting count
* is now 2 rather than 1. Since we are nested, calling
* spinlock_exit() will simply adjust the counts without allowing
* spin lock using code to interrupt us.
*/
spinlock_exit();
KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count"));
PCPU_SET(switchtime, cpu_ticks());
PCPU_SET(switchticks, ticks);
cpu_throw(NULL, choosethread()); /* doesn't return */
panic("scheduler returned us to %s", __func__);
}
static int
smp_start_secondary(int pal_id, int cpuid)
{
struct pcs *cpu = LOCATE_PCS(hwrpb, pal_id);
struct pcs *bootcpu = LOCATE_PCS(hwrpb, boot_cpu_id);
struct alpha_pcb *pcb = (struct alpha_pcb *) cpu->pcs_hwpcb;
struct pcpu *pcpu;
int i;
size_t sz;
if ((cpu->pcs_flags & PCS_PV) == 0) {
printf("smp_start_secondary: cpu %d PALcode invalid\n", pal_id);
return 0;
}
if (bootverbose)
printf("smp_start_secondary: starting cpu %d\n", pal_id);
sz = KSTACK_PAGES * PAGE_SIZE;
pcpu = malloc(sz, M_TEMP, M_NOWAIT);
if (!pcpu) {
printf("smp_start_secondary: can't allocate memory\n");
return 0;
}
pcpu_init(pcpu, cpuid, sz);
pcpu->pc_pal_id = pal_id;
/*
* Copy the idle pcb and setup the address to start executing.
* Use the pcb unique value to point the secondary at its pcpu
* structure.
*/
*pcb = pcpu->pc_idlepcb;
pcb->apcb_unique = (u_int64_t)pcpu;
hwrpb->rpb_restart = (u_int64_t) smp_init_secondary_glue;
hwrpb->rpb_restart_val = (u_int64_t) smp_init_secondary_glue;
hwrpb->rpb_checksum = hwrpb_checksum();
/*
* Tell the cpu to start with the same PALcode as us.
*/
bcopy(&bootcpu->pcs_pal_rev, &cpu->pcs_pal_rev,
sizeof cpu->pcs_pal_rev);
/*
* Set flags in cpu structure and push out write buffers to
* make sure the secondary sees it.
*/
cpu->pcs_flags |= PCS_CV|PCS_RC;
cpu->pcs_flags &= ~PCS_BIP;
alpha_mb();
/*
* Fire it up and hope for the best.
*/
if (!smp_send_secondary_command("START\r\n", pal_id)) {
printf("smp_start_secondary: can't send START command\n");
pcpu_destroy(pcpu);
free(pcpu, M_TEMP);
return 0;
}
/*
* Wait for the secondary to set the BIP flag in its structure.
*/
for (i = 0; i < 100000; i++) {
if (cpu->pcs_flags & PCS_BIP)
break;
DELAY(10);
}
if (!(cpu->pcs_flags & PCS_BIP)) {
printf("smp_start_secondary: secondary did not respond\n");
pcpu_destroy(pcpu);
free(pcpu, M_TEMP);
return 0;
}
/*
* It worked (I think).
*/
if (bootverbose)
printf("smp_start_secondary: cpu %d started\n", pal_id);
return 1;
}
/* Other stuff */
static int
smp_cpu_enabled(struct pcs *pcsp)
{
/* Is this CPU present? */
if ((pcsp->pcs_flags & PCS_PP) == 0)
return (0);
/* Is this CPU available? */
if ((pcsp->pcs_flags & PCS_PA) == 0)
/*
* The TurboLaser PCS_PA bit doesn't seem to be set
* correctly.
*/
if (hwrpb->rpb_type != ST_DEC_21000)
return (0);
/* Is this CPU's PALcode valid? */
if ((pcsp->pcs_flags & PCS_PV) == 0)
return (0);
return (1);
}
void
cpu_mp_setmaxid(void)
{
u_int64_t i;
mp_maxid = 0;
for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) {
if (i == PCPU_GET(pal_id))
continue;
if (!smp_cpu_enabled(LOCATE_PCS(hwrpb, i)))
continue;
mp_maxid++;
}
if (mp_maxid > MAXCPU)
mp_maxid = MAXCPU;
}
int
cpu_mp_probe(void)
{
int i, cpus;
/* XXX: Need to check for valid platforms here. */
boot_cpu_id = PCPU_GET(pal_id);
KASSERT(boot_cpu_id == hwrpb->rpb_primary_cpu_id,
("cpu_mp_probe() called on non-primary CPU"));
all_cpus = PCPU_GET(cpumask);
mp_ncpus = 1;
/* Make sure we have at least one secondary CPU. */
cpus = 0;
for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) {
if (i == PCPU_GET(pal_id))
continue;
if (!smp_cpu_enabled(LOCATE_PCS(hwrpb, i)))
continue;
cpus++;
}
return (cpus);
}
void
cpu_mp_start(void)
{
int i, cpuid;
mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
cpuid = 1;
for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) {
struct pcs *pcsp;
if (i == boot_cpu_id)
continue;
pcsp = LOCATE_PCS(hwrpb, i);
if ((pcsp->pcs_flags & PCS_PP) == 0)
continue;
if ((pcsp->pcs_flags & PCS_PA) == 0) {
if (hwrpb->rpb_type == ST_DEC_21000) {
printf("Ignoring PA bit for CPU %d.\n", i);
} else {
if (bootverbose)
printf("CPU %d not available.\n", i);
continue;
}
}
if ((pcsp->pcs_flags & PCS_PV) == 0) {
if (bootverbose)
printf("CPU %d does not have valid PALcode.\n",
i);
continue;
}
if (i > MAXCPU) {
if (bootverbose) {
printf("CPU %d not supported.", i);
printf(" Only %d CPUs supported.\n", MAXCPU);
}
continue;
}
if (resource_disabled("cpu", i)) {
printf("CPU %d disabled by loader.\n", i);
continue;
}
if (smp_start_secondary(i, cpuid)) {
all_cpus |= (1 << cpuid);
mp_ncpus++;
cpuid++;
}
}
PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
}
void
cpu_mp_announce(void)
{
struct pcpu *pc;
int i;
/* List CPUs */
printf(" cpu0 (BSP): PAL ID: %2lu\n", boot_cpu_id);
for (i = 1; i < MAXCPU; i++) {
if (CPU_ABSENT(i))
continue;
pc = pcpu_find(i);
MPASS(pc != NULL);
printf(" cpu%d (AP): PAL ID: %2lu\n", i, pc->pc_pal_id);
}
}
/*
* send an IPI to a set of cpus.
*/
void
ipi_selected(u_int32_t cpus, u_int64_t ipi)
{
struct pcpu *pcpu;
CTR2(KTR_SMP, "ipi_selected: cpus: %x ipi: %lx", cpus, ipi);
alpha_mb();
while (cpus) {
int cpuid = ffs(cpus) - 1;
cpus &= ~(1 << cpuid);
pcpu = pcpu_find(cpuid);
if (pcpu) {
atomic_set_64(&pcpu->pc_pending_ipis, ipi);
alpha_mb();
CTR1(KTR_SMP, "calling alpha_pal_wripir(%d)",
pcpu->pc_pal_id);
alpha_pal_wripir(pcpu->pc_pal_id);
}
}
}
/*
* send an IPI INTerrupt containing 'vector' to all CPUs, including myself
*/
void
ipi_all(u_int64_t ipi)
{
ipi_selected(all_cpus, ipi);
}
/*
* send an IPI to all CPUs EXCEPT myself
*/
void
ipi_all_but_self(u_int64_t ipi)
{
ipi_selected(PCPU_GET(other_cpus), ipi);
}
/*
* send an IPI to myself
*/
void
ipi_self(u_int64_t ipi)
{
ipi_selected(PCPU_GET(cpumask), ipi);
}
/*
* Handle an IPI sent to this processor.
*/
void
smp_handle_ipi(struct trapframe *frame)
{
u_int64_t ipis = atomic_readandclear_64(PCPU_PTR(pending_ipis));
u_int64_t ipi;
int cpumask;
cpumask = PCPU_GET(cpumask);
CTR1(KTR_SMP, "smp_handle_ipi(), ipis=%lx", ipis);
while (ipis) {
/*
* Find the lowest set bit.
*/
ipi = ipis & ~(ipis - 1);
ipis &= ~ipi;
switch (ipi) {
case IPI_INVLTLB:
CTR0(KTR_SMP, "IPI_NVLTLB");
ALPHA_TBIA();
break;
case IPI_RENDEZVOUS:
CTR0(KTR_SMP, "IPI_RENDEZVOUS");
smp_rendezvous_action();
break;
case IPI_AST:
CTR0(KTR_SMP, "IPI_AST");
break;
case IPI_STOP:
CTR0(KTR_SMP, "IPI_STOP");
savectx(&stoppcbs[PCPU_GET(cpuid)]);
atomic_set_acq_int(&stopped_cpus, cpumask);
while ((started_cpus & cpumask) == 0)
cpu_spinwait();
atomic_clear_rel_int(&started_cpus, cpumask);
atomic_clear_rel_int(&stopped_cpus, cpumask);
break;
}
}
/*
* Dump console messages to the console. XXX - we need to handle
* requests to provide PALcode to secondaries and to start up new
* secondaries that are added to the system on the fly.
*/
if (PCPU_GET(pal_id) == boot_cpu_id) {
u_int pal_id;
u_int64_t txrdy;
#ifdef DIAGNOSTIC
struct pcs *cpu;
char buf[81];
#endif
alpha_mb();
while (hwrpb->rpb_txrdy != 0) {
pal_id = ffs(hwrpb->rpb_txrdy) - 1;
#ifdef DIAGNOSTIC
cpu = LOCATE_PCS(hwrpb, pal_id);
bcopy(&cpu->pcs_buffer.txbuf, buf,
cpu->pcs_buffer.txlen);
buf[cpu->pcs_buffer.txlen] = '\0';
printf("SMP From CPU%d: %s\n", pal_id, buf);
#endif
do {
txrdy = hwrpb->rpb_txrdy;
} while (atomic_cmpset_64(&hwrpb->rpb_txrdy, txrdy,
txrdy & ~(1 << pal_id)) == 0);
}
}
}
static void
release_aps(void *dummy __unused)
{
if (bootverbose && mp_ncpus > 1)
printf("%s: releasing secondary CPUs\n", __func__);
atomic_store_rel_int(&aps_ready, 1);
while (mp_ncpus > 1 && smp_started == 0)
; /* nothing */
}
SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);

370
sys/alpha/alpha/pal.s
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@ -1,370 +0,0 @@
/*-
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* The various OSF PALcode routines.
*
* The following code is originally derived from pages: (I) 6-5 - (I) 6-7
* and (III) 2-1 - (III) 2-25 of "Alpha Architecture Reference Manual" by
* Richard L. Sites.
*
* Updates taken from pages: (II-B) 2-1 - (II-B) 2-33 of "Alpha AXP
* Architecture Reference Manual, Second Edition" by Richard L. Sites
* and Richard T. Witek.
*/
#include <machine/asm.h>
__KERNEL_RCSID(1, "$NetBSD: pal.s,v 1.12 1998/02/27 03:44:53 thorpej Exp $");
__FBSDID("$FreeBSD$");
.text
.loc 1 __LINE__
/*
* alpha_rpcc: read process cycle counter (XXX INSTRUCTION, NOT PALcode OP)
*/
.text
LEAF(alpha_rpcc,1)
rpcc v0
RET
END(alpha_rpcc)
/*
* alpha_mb: memory barrier (XXX INSTRUCTION, NOT PALcode OP)
*/
.text
LEAF(alpha_mb,0)
mb
RET
END(alpha_mb)
/*
* alpha_wmb: write memory barrier (XXX INSTRUCTION, NOT PALcode OP)
*/
.text
LEAF(alpha_wmb,0)
/* wmb XXX */
mb /* XXX */
RET
END(alpha_wmb)
/*
* alpha_amask: read architecture features (XXX INSTRUCTION, NOT PALcode OP)
*
* Arguments:
* a0 bitmask of features to test
*
* Returns:
* v0 bitmask - bit is _cleared_ if feature is supported
*/
.text
LEAF(alpha_amask,1)
amask a0, v0
RET
END(alpha_amask)
/*
* alpha_implver: read implementation version (XXX INSTRUCTION, NOT PALcode OP)
*
* Returns:
* v0 implementation version - see <machine/alpha_cpu.h>
*/
.text
LEAF(alpha_implver,0)
#if 0
implver 0x1, v0
#else
.long 0x47e03d80 /* XXX gas(1) does the Wrong Thing */
#endif
RET
END(alpha_implver)
/*
* alpha_pal_imb: I-Stream memory barrier. [UNPRIVILEGED]
* (Makes instruction stream coherent with data stream.)
*/
.text
LEAF(alpha_pal_imb,0)
call_pal PAL_imb
RET
END(alpha_pal_imb)
/*
* alpha_pal_cflush: Cache flush [PRIVILEGED]
*
* Flush the entire physical page specified by the PFN specified in
* a0 from any data caches associated with the current processor.
*
* Arguments:
* a0 page frame number of page to flush
*/
.text
LEAF(alpha_pal_cflush,1)
call_pal PAL_cflush
RET
END(alpha_pal_cflush)
/*
* alpha_pal_draina: Drain aborts. [PRIVILEGED]
*/
.text
LEAF(alpha_pal_draina,0)
call_pal PAL_draina
RET
END(alpha_pal_draina)
/*
* alpha_pal_halt: Halt the processor. [PRIVILEGED]
*/
.text
LEAF(alpha_pal_halt,0)
call_pal PAL_halt
br zero,alpha_pal_halt /* Just in case */
RET
END(alpha_pal_halt)
/*
* alpha_pal_rdmces: Read MCES processor register. [PRIVILEGED]
*
* Return:
* v0 current MCES value
*/
.text
LEAF(alpha_pal_rdmces,1)
call_pal PAL_OSF1_rdmces
RET
END(alpha_pal_rdmces)
/*
* alpha_pal_rdps: Read processor status. [PRIVILEGED]
*
* Return:
* v0 current PS value
*/
.text
LEAF(alpha_pal_rdps,0)
call_pal PAL_OSF1_rdps
RET
END(alpha_pal_rdps)
/*
* alpha_pal_rdusp: Read user stack pointer. [PRIVILEGED]
*
* Return:
* v0 current user stack pointer
*/
.text
LEAF(alpha_pal_rdusp,0)
call_pal PAL_OSF1_rdusp
RET
END(alpha_pal_rdusp)
/*
* alpha_pal_rdval: Read system value. [PRIVILEGED]
*
* Returns the sysvalue in v0, allowing access to a 64-bit
* per-processor value for use by the operating system.
*
* Return:
* v0 sysvalue
*/
.text
LEAF(alpha_pal_rdval,0)
call_pal PAL_OSF1_rdval
RET
END(alpha_pal_rdval)
/*
* alpha_pal_swpipl: Swap Interrupt priority level. [PRIVILEGED]
* _alpha_pal_swpipl: Same, from profiling code. [PRIVILEGED]
*
* Arguments:
* a0 new IPL
*
* Return:
* v0 old IPL
*/
.text
LEAF(alpha_pal_swpipl,1)
call_pal PAL_OSF1_swpipl
RET
END(alpha_pal_swpipl)
LEAF_NOPROFILE(_alpha_pal_swpipl,1)
call_pal PAL_OSF1_swpipl
RET
END(_alpha_pal_swpipl)
/*
* alpha_pal_tbi: Translation buffer invalidate. [PRIVILEGED]
*
* Arguments:
* a0 operation selector
* a1 address to operate on (if necessary)
*/
.text
LEAF(alpha_pal_tbi,2)
call_pal PAL_OSF1_tbi
RET
END(alpha_pal_tbi)
/*
* alpha_pal_whami: Who am I? [PRIVILEGED]
*
* Return:
* v0 processor number
*/
.text
LEAF(alpha_pal_whami,0)
call_pal PAL_OSF1_whami
RET
END(alpha_pal_whami)
/*
* alpha_pal_wrent: Write system entry address. [PRIVILEGED]
*
* Arguments:
* a0 new vector
* a1 vector selector
*/
.text
LEAF(alpha_pal_wrent,2)
call_pal PAL_OSF1_wrent
RET
END(alpha_pal_wrent)
/*
* alpha_pal_wrfen: Write floating-point enable. [PRIVILEGED]
*
* Arguments:
* a0 new enable value (val & 0x1 -> enable).
*/
.text
LEAF(alpha_pal_wrfen,1)
call_pal PAL_OSF1_wrfen
RET
END(alpha_pal_wrfen)
/*
* alpha_pal_wripir: Write interprocessor interrupt request. [PRIVILEGED]
*
* Generate an interprocessor interrupt on the processor specified by
* processor number in a0.
*
* Arguments:
* a0 processor to interrupt
*/
.text
LEAF(alpha_pal_wripir,1)
call_pal PAL_ipir
RET
END(alpha_pal_wripir)
/*
* alpha_pal_wrusp: Write user stack pointer. [PRIVILEGED]
*
* Arguments:
* a0 new user stack pointer
*/
.text
LEAF(alpha_pal_wrusp,1)
call_pal PAL_OSF1_wrusp
RET
END(alpha_pal_wrusp)
/*
* alpha_pal_wrvptptr: Write virtual page table pointer. [PRIVILEGED]
*
* Arguments:
* a0 new virtual page table pointer
*/
.text
LEAF(alpha_pal_wrvptptr,1)
call_pal PAL_OSF1_wrvptptr
RET
END(alpha_pal_wrvptptr)
/*
* alpha_pal_wrmces: Write MCES processor register. [PRIVILEGED]
*
* Arguments:
* a0 value to write to MCES
*/
.text
LEAF(alpha_pal_wrmces,1)
call_pal PAL_OSF1_wrmces
RET
END(alpha_pal_wrmces)
/*
* alpha_pal_wrval: Write system value. [PRIVILEGED]
*
* Write the value passed in a0 to this processor's sysvalue.
*
* Arguments:
* a0 value to write to sysvalue
*/
LEAF(alpha_pal_wrval,1)
call_pal PAL_OSF1_wrval
RET
END(alpha_pal_wrval)
/*
* alpha_pal_swpctx: Swap context. [PRIVILEGED]
*
* Switch to a new process context.
*
* Arguments:
* a0 physical address of hardware PCB describing context
*
* Returns:
* v0 physical address of hardware PCB describing previous context
*/
LEAF(alpha_pal_swpctx,1)
call_pal PAL_OSF1_swpctx
RET
END(alpha_pal_swpctx)
/*
* alpha_pal_wrperfmon: Write perf monitor [PRIVILEGED]
*
* Enables / disables performance monitoring hardware
*
* Arguments:
* a0 function type
*
* a1 function parameter
*
* Returns:
* v0 0 (failure) or 1 (success)
*/
LEAF(alpha_pal_wrperfmon,2)
call_pal PAL_OSF1_wrperfmon
RET
END(alpha_pal_wrperfmon)

2727
sys/alpha/alpha/pmap.c
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File diff suppressed because it is too large Load Diff

326
sys/alpha/alpha/prom.c
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@ -1,326 +0,0 @@
/*-
* Copyright (c) 1992, 1994, 1995, 1996 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
/* __KERNEL_RCSID(0, "$NetBSD: prom.c,v 1.22 1998/02/27 04:03:00 thorpej Exp $"); */
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <sys/proc.h>
#include <sys/cons.h>
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <machine/prom.h>
#include <machine/rpb.h>
#include <machine/vmparam.h>
struct rpb *hwrpb;
extern struct prom_vec prom_dispatch_v;
int prom_mapped = 1; /* Is PROM still mapped? */
pt_entry_t rom_pte, saved_pte[1]; /* XXX */
static pt_entry_t *rom_lev1map(void);
extern pt_entry_t* Lev1map;
static void prom_cache_sync(void);
static pt_entry_t *
rom_lev1map()
{
struct alpha_pcb *apcb;
struct pcb *cpcb;
/*
* We may be called before the first context switch
* after alpha_init(), in which case we just need
* to use the kernel Lev1map.
*/
if (PCPU_GET(curpcb) == 0)
return (Lev1map);
/*
* Find the level 1 map that we're currently running on.
*/
cpcb = PCPU_GET(curpcb);
apcb = (struct alpha_pcb *)ALPHA_PHYS_TO_K0SEG((vm_offset_t)cpcb);
return ((pt_entry_t *)ALPHA_PHYS_TO_K0SEG(alpha_ptob(apcb->apcb_ptbr)));
}
void
init_prom_interface(rpb)
struct rpb *rpb;
{
struct crb *c;
c = (struct crb *)((char *)rpb + rpb->rpb_crb_off);
prom_dispatch_v.routine_arg = c->crb_v_dispatch;
prom_dispatch_v.routine = c->crb_v_dispatch->entry_va;
}
static int alpha_console;
void
init_bootstrap_console()
{
char buf[4];
init_prom_interface(hwrpb);
prom_getenv(PROM_E_TTY_DEV, buf, 4);
alpha_console = buf[0] - '0';
promcnattach(alpha_console);
}
static register_t enter_prom(void);
static void leave_prom(critical_t);
/*
* promcnputc:
*
* Remap char before passing off to prom.
*
* Prom only takes 32 bit addresses. Copy char somewhere prom can
* find it. This routine will stop working after pmap_rid_of_console
* is called in alpha_init. This is due to the hard coded address
* of the console area.
*/
void
promcnputc(struct consdev *cp, int c)
{
prom_return_t ret;
unsigned char *to = (unsigned char *)0x20000000;
register_t s;
s = enter_prom(); /* critical_enter() and map prom */
*to = c;
do {
ret.bits = prom_putstr(alpha_console, to, 1);
} while ((ret.u.retval & 1) == 0);
leave_prom(s); /* unmap prom and critical_exit(s) */
}
/*
* promcngetc:
*
* Wait for the prom to get a real char and pass it back.
*/
int
promcngetc(struct consdev *cp)
{
prom_return_t ret;
register_t s;
for (;;) {
s = enter_prom();
ret.bits = prom_getc(alpha_console);
leave_prom(s);
if (ret.u.status == 0 || ret.u.status == 1)
return (ret.u.retval);
}
}
/*
* promcncheckc
*
* If a char is ready, return it, otherwise return -1.
*/
int
promcncheckc(struct consdev *cp)
{
prom_return_t ret;
register_t s;
s = enter_prom();
ret.bits = prom_getc(alpha_console);
leave_prom(s);
if (ret.u.status == 0 || ret.u.status == 1)
return (ret.u.retval);
else
return (-1);
}
static register_t
enter_prom()
{
pt_entry_t *lev1map;
register_t s;
s = intr_disable();
if (!prom_mapped) {
if (!pmap_uses_prom_console())
panic("enter_prom");
lev1map = rom_lev1map(); /* XXX */
saved_pte[0] = lev1map[0]; /* XXX */
lev1map[0] = rom_pte; /* XXX */
prom_cache_sync(); /* XXX */
}
return s;
}
static void
leave_prom(s)
register_t s;
{
pt_entry_t *lev1map;
if (!prom_mapped) {
if (!pmap_uses_prom_console())
panic("leave_prom");
lev1map = rom_lev1map(); /* XXX */
lev1map[0] = saved_pte[0]; /* XXX */
prom_cache_sync(); /* XXX */
}
intr_restore(s);
}
static void
prom_cache_sync(void)
{
ALPHA_TBIA();
alpha_pal_imb();
}
int
prom_getenv(id, buf, len)
int id, len;
char *buf;
{
unsigned char *to = (unsigned char *)0x20000000;
prom_return_t ret;
register_t s;
s = enter_prom();
ret.bits = prom_getenv_disp(id, to, len);
bcopy(to, buf, len);
leave_prom(s);
if (ret.u.status & 0x4)
ret.u.retval = 0;
buf[ret.u.retval] = '\0';
return (ret.bits);
}
void
prom_halt(halt)
int halt;
{
struct pcs *p;
/*
* Turn off interrupts, for sanity.
*/
intr_disable();
/*
* Set "boot request" part of the CPU state depending on what
* we want to happen when we halt.
*/
p = LOCATE_PCS(hwrpb, PCPU_GET(cpuid));
p->pcs_flags &= ~(PCS_RC | PCS_HALT_REQ);
if (halt)
p->pcs_flags |= PCS_HALT_STAY_HALTED;
else
p->pcs_flags |= PCS_HALT_WARM_BOOT;
/*
* Halt the machine.
*/
for (;;)
alpha_pal_halt();
}
u_int64_t
hwrpb_checksum()
{
u_int64_t *p, sum;
int i;
for (i = 0, p = (u_int64_t *)hwrpb, sum = 0;
i < (offsetof(struct rpb, rpb_checksum) / sizeof (u_int64_t));
i++, p++)
sum += *p;
return (sum);
}
void
hwrpb_restart_setup()
{
struct pcs *p;
/* Clear bootstrap-in-progress flag since we're done bootstrapping */
p = (struct pcs *)((char *)hwrpb + hwrpb->rpb_pcs_off);
p->pcs_flags &= ~PCS_BIP;
bcopy(&thread0.td_pcb->pcb_hw, p->pcs_hwpcb,
sizeof thread0.td_pcb->pcb_hw);
hwrpb->rpb_vptb = VPTBASE;
/* when 'c'ontinuing from console halt, do a dump */
hwrpb->rpb_rest_term = (u_int64_t)&XentRestart;
hwrpb->rpb_rest_term_val = 0x1;
#if 0
/* don't know what this is really used by, so don't mess with it. */
hwrpb->rpb_restart = (u_int64_t)&XentRestart;
hwrpb->rpb_restart_val = 0x2;
#endif
hwrpb->rpb_checksum = hwrpb_checksum();
p->pcs_flags |= (PCS_RC | PCS_CV);
}
u_int64_t
console_restart(ra, ai, pv)
u_int64_t ra, ai, pv;
{
struct pcs *p;
/* Clear restart-capable flag, since we can no longer restart. */
p = (struct pcs *)((char *)hwrpb + hwrpb->rpb_pcs_off);
p->pcs_flags &= ~PCS_RC;
panic("user requested console halt");
return (1);
}

116
sys/alpha/alpha/prom_disp.s
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@ -1,116 +0,0 @@
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#ifndef _LOCORE
#include <machine/asm.h>
#else
__KERNEL_RCSID(2, "$NetBSD: prom_disp.s,v 1.8 1997/11/03 04:22:03 ross Exp $");
__FBSDID("$FreeBSD$");
#endif
.globl prom_dispatch_v
.comm prom_dispatch_v,16
.text
.align 4
.text
.loc 1 __LINE__
/*
* Dispatcher routine. Implements prom's calling machinery, saves our
* callee-saved registers as required by C.
*/
#define D_RA (7*8)
#define D_S0 (8*8)
#define D_S1 (9*8)
#define D_S2 (10*8)
#define D_S3 (11*8)
#define D_S4 (12*8)
#define D_S5 (13*8)
#define D_S6 (14*8)
#define DISPATCH_FRAME_SIZE (15*8)
#define DISPATCH_REGS IM_RA|IM_S0|IM_S1|IM_S2|IM_S3|IM_S4|IM_S5|IM_S6
NESTED(prom_dispatch, 5, DISPATCH_FRAME_SIZE, ra, DISPATCH_REGS, 0)
ldgp gp, 0(pv)
lda sp, -DISPATCH_FRAME_SIZE(sp)
stq ra, D_RA(sp)
stq s0, D_S0(sp)
stq s1, D_S1(sp)
stq s2, D_S2(sp)
stq s3, D_S3(sp)
stq s4, D_S4(sp)
stq s5, D_S5(sp)
stq s6, D_S6(sp)
/* Lord have mercy because.. I would not. */
#define STUPID_PROM_IS_32_BITS
#ifdef STUPID_PROM_IS_32_BITS
ldah s0, 0x2000(zero) /* hack for hack */
lda s0, (0x2000-8)(s0)
stq sp, 0(s0)
or s0, zero, sp
#endif /* STUPID_PROM_IS_32_BITS */
lda pv, prom_dispatch_v
ldq v0, 0(pv) /* routine */
ldq pv, 8(pv) /* routine_arg */
jsr ra, (v0)
#ifdef STUPID_PROM_IS_32_BITS
ldah s0, 0x2000(zero) /* hack for hack */
lda s0, (0x2000-8)(s0)
ldq sp, 0(s0)
#endif /* STUPID_PROM_IS_32_BITS */
ldq ra, D_RA(sp)
ldq s0, D_S0(sp)
ldq s1, D_S1(sp)
ldq s2, D_S2(sp)
ldq s3, D_S3(sp)
ldq s4, D_S4(sp)
ldq s5, D_S5(sp)
ldq s6, D_S6(sp)
lda sp, DISPATCH_FRAME_SIZE(sp)
RET
END(prom_dispatch)
#undef D_RA
#undef D_S0
#undef D_S1
#undef D_S2
#undef D_S3
#undef D_S4
#undef D_S5
#undef D_S6
#undef DISPATCH_FRAME_SIZE
#undef DISPATCH_REGS

248
sys/alpha/alpha/promcons.c
View File

@ -1,248 +0,0 @@
/* $NetBSD: promcons.c,v 1.13 1998/03/21 22:52:59 mycroft Exp $ */
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/cons.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <vm/vm_object.h>
#include <vm/vm_extern.h>
#include <vm/vm_pageout.h>
#include <vm/vm_pager.h>
#include <machine/prom.h>
#define _PMAP_MAY_USE_PROM_CONSOLE /* XXX for now */
#ifdef _PMAP_MAY_USE_PROM_CONSOLE
#define PROM_POLL_HZ 50
static d_open_t promopen;
static d_close_t promclose;
static struct cdevsw prom_cdevsw = {
.d_version = D_VERSION,
.d_open = promopen,
.d_close = promclose,
.d_name = "prom",
.d_flags = D_TTY | D_NEEDGIANT,
};
static int polltime;
static struct callout_handle promtimeouthandle
= CALLOUT_HANDLE_INITIALIZER(&promtimeouthandle);
void promstart(struct tty *);
void promtimeout(void *);
int promparam(struct tty *, struct termios *);
void promstop(struct tty *, int);
extern int promcons_dly_mkdev;
void promcons_delayed_makedev(void);
int
promopen(dev, flag, mode, td)
struct cdev *dev;
int flag, mode;
struct thread *td;
{
struct tty *tp;
int unit = minor(dev);
int s;
int error = 0, setuptimeout = 0;
if (pmap_uses_prom_console() == 0 || unit != 0)
return ENXIO;
tp = dev->si_tty = ttyalloc();
s = spltty();
tp->t_oproc = promstart;
tp->t_param = promparam;
tp->t_stop = promstop;
tp->t_dev = dev;
if ((tp->t_state & TS_ISOPEN) == 0) {
tp->t_state |= TS_CARR_ON;
ttyconsolemode(tp, 0);
setuptimeout = 1;
} else if ((tp->t_state & TS_XCLUDE) && suser(td)) {
splx(s);
return EBUSY;
}
splx(s);
error = ttyld_open(tp, dev);
if (error == 0 && setuptimeout) {
polltime = hz / PROM_POLL_HZ;
if (polltime < 1)
polltime = 1;
promtimeouthandle = timeout(promtimeout, tp, polltime);
}
return error;
}
int
promclose(dev, flag, mode, td)
struct cdev *dev;
int flag, mode;
struct thread *td;
{
int unit = minor(dev);
struct tty *tp = dev->si_tty;
if (unit != 0)
return ENXIO;
untimeout(promtimeout, tp, promtimeouthandle);
ttyld_close(tp, flag);
tty_close(tp);
return 0;
}
int
promparam(tp, t)
struct tty *tp;
struct termios *t;
{
return 0;
}
void
promstart(tp)
struct tty *tp;
{
int s;
s = spltty();
if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
ttwwakeup(tp);
splx(s);
return;
}
tp->t_state |= TS_BUSY;
while (tp->t_outq.c_cc != 0)
promcnputc(NULL, getc(&tp->t_outq));
tp->t_state &= ~TS_BUSY;
ttwwakeup(tp);
splx(s);
}
/*
* Stop output on a line.
*/
void
promstop(tp, flag)
struct tty *tp;
int flag;
{
int s;
s = spltty();
if (tp->t_state & TS_BUSY)
if ((tp->t_state & TS_TTSTOP) == 0)
tp->t_state |= TS_FLUSH;
splx(s);
}
void
promtimeout(v)
void *v;
{
struct tty *tp = v;
int c;
while ((c = promcncheckc(NULL)) != -1) {
if (tp->t_state & TS_ISOPEN)
ttyld_rint(tp, c);
}
promtimeouthandle = timeout(promtimeout, tp, polltime);
}
CONS_DRIVER(prom, NULL, NULL, NULL, promcngetc, promcncheckc, promcnputc, NULL);
static int promcn_attached = 0;
void
promcnattach(int alpha_console)
{
prom_consdev.cn_pri = CN_NORMAL;
sprintf(prom_consdev.cn_name, "promcons");
if (promcons_dly_mkdev)
promcons_dly_mkdev++;
else {
make_dev(&prom_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "promcons");
}
cnadd(&prom_consdev);
promcn_attached = 1;
}
void
promcons_delayed_makedev(void)
{
if (promcn_attached) {
make_dev(&prom_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "promcons");
}
}
void
promcndetach(void)
{
if (promcn_attached) {
cnremove(&prom_consdev);
promcn_attached = 0;
}
}
/*
* promcnputc, promcngetc and promchcheckc in prom.c for layering reasons
*/
#endif /* _PMAP_MAY_USE_PROM_CONSOLE */

195
sys/alpha/alpha/sgmap.c
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@ -1,195 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <machine/bus.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/lock.h>
#include <machine/sgmap.h>
#include <vm/vm.h>
#include <vm/pmap.h>
MALLOC_DEFINE(M_SGMAP, "sgmap", "Scatter Gather mapping");
struct sgmap {
struct rman rm; /* manage range of bus addresses */
sgmap_map_callback *map; /* map one page in the sgmap */
void *arg; /* argument to map function */
bus_addr_t sba;
bus_addr_t eba;
};
void *overflow_page = 0;
vm_offset_t overflow_page_pa;
vm_offset_t
sgmap_overflow_page(void)
{
/*
* Allocate the overflow page if necessary.
*/
if (!overflow_page) {
overflow_page = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT);
if (!overflow_page)
panic("sgmap_alloc_region: can't allocate overflow page");
overflow_page_pa = pmap_kextract((vm_offset_t) overflow_page);
}
return overflow_page_pa;
}
/*
* Create an sgmap to manage a range of bus addresses which map
* physical memory using a scatter-gather map.
*/
struct sgmap *
sgmap_map_create(bus_addr_t sba, bus_addr_t eba,
sgmap_map_callback *map, void *arg)
{
struct sgmap *sgmap;
sgmap = malloc(sizeof *sgmap, M_SGMAP, M_NOWAIT);
if (!sgmap)
return 0;
sgmap->rm.rm_start = sba;
sgmap->rm.rm_end = eba;
sgmap->rm.rm_type = RMAN_ARRAY;
sgmap->rm.rm_descr = "Scatter Gather Bus Addresses";
rman_init(&sgmap->rm);
rman_manage_region(&sgmap->rm, sba, eba);
sgmap->map = map;
sgmap->arg = arg;
sgmap->sba = sba;
sgmap->eba = eba;
return sgmap;
}
/*
* Destroy an sgmap created with sgmap_map_create().
*/
void
sgmap_map_destroy(struct sgmap *sgmap)
{
rman_fini(&sgmap->rm);
free(sgmap, M_SGMAP);
}
/*
* Map a range of virtual addresses using the sgmap and return the bus
* address of the mapped region. An opaque handle for the mapped
* region is also returned in *mhp. This handle should be passed to
* sgmap_free_region() when the mapping is no longer required.
*/
bus_addr_t
sgmap_alloc_region(struct sgmap *sgmap,
bus_size_t size,
bus_size_t boundary,
void **mhp)
{
struct resource *res;
bus_addr_t ba, nba;
/*
* This ensures allocations are on page boundaries. The extra
* page is used as a guard page since dma prefetching can
* generate accesses to addresses outside the transfer range.
*/
size = round_page(size);
/*
* Attempt to allocate within each boundary delimited region.
*/
res = 0;
for (ba = sgmap->sba; ba < sgmap->eba; ba = nba) {
nba = (ba + boundary) & ~(boundary - 1);
res = rman_reserve_resource(&sgmap->rm,
ba, nba - 1, size + PAGE_SIZE,
RF_ACTIVE, 0);
if (res)
break;
}
if (res == 0)
return 0;
*mhp = (void *) res;
return rman_get_start(res);
}
void
sgmap_load_region(struct sgmap *sgmap,
bus_addr_t sba,
vm_offset_t va,
bus_size_t size)
{
bus_addr_t ba, eba;
/*
* Call the chipset to map each page in the mapped range to
* the correct physical page.
*/
for (ba = sba, eba = sba + size; ba < eba;
ba += PAGE_SIZE, va += PAGE_SIZE) {
vm_offset_t pa = pmap_kextract(va);
sgmap->map(sgmap->arg, ba, pa);
}
sgmap->map(sgmap->arg, ba, overflow_page_pa);
}
void
sgmap_unload_region(struct sgmap *sgmap,
bus_addr_t sba,
bus_size_t size)
{
bus_addr_t ba, eba;
/*
* Call the chipset to unmap each page.
*/
for (ba = sba, eba = sba + size; ba < eba; ba += PAGE_SIZE) {
sgmap->map(sgmap->arg, ba, 0);
}
sgmap->map(sgmap->arg, ba, 0);
}
/*
* Free a region allocated using sgmap_alloc_region().
*/
void
sgmap_free_region(struct sgmap *sgmap, void *mh)
{
struct resource *res = mh;
rman_release_resource(res);
}

691
sys/alpha/alpha/support.s
View File

@ -1,691 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <machine/asm.h>
#include <assym.s>
.text
/**************************************************************************/
/*
* intptr_t
* casuptr(intptr_t *p, intptr_t old, intptr_t new)
*/
LEAF(casuptr, 3)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
1:
ldq_l v0, 0(a0) /* try to load the old value */
cmpeq v0, a1, t0 /* compare */
beq t0, 2f /* exit if not equal */
mov a2, t0 /* setup value to write */
stq_c t0, 0(a0) /* write if address still locked */
beq t0, 1b /* if it failed, spin */
2:
stq zero, PCB_ONFAULT(t2) /* clean up */
RET
END(casuptr)
/*
* fu{byte,word} : fetch a byte (word) from user memory
*/
LEAF(suword, 1)
XLEAF(suword64, 1)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
stq a1, 0(a0) /* try the store */
stq zero, PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
END(suword)
LEAF(suword32, 2)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
stl a1, 0(a0) /* try the store */
stq zero, PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
END(suword32)
LEAF(subyte, 1)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
zap a1, 0xfe, a1 /* mask off the byte to store */
insbl a1, a0, a1 /* shift it to the right place */
ldq_u t0, 0(a0) /* read the qword to store it in */
mskbl t0, a0, t0 /* make a place for our byte */
or a1, t0, a1 /* move it in */
stq_u a1, 0(a0) /* and put the byte back */
stq zero, PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
END(subyte)
LEAF(fuword, 1)
XLEAF(fuword64, 1)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
ldq v0, 0(a0) /* try the fetch */
stq zero, PCB_ONFAULT(t2) /* clean up */
RET
END(fuword)
LEAF(fuword32, 1)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
ldl v0, 0(a0) /* get the word containing our byte */
stq zero, PCB_ONFAULT(t2) /* clean up */
RET
END(fuword32)
LEAF(fubyte, 1)
LDGP(pv)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
lda t0, fusufault /* trap faults */
ldq t2, PC_CURTHREAD(pcpup)
ldq t2, TD_PCB(t2)
stq t0, PCB_ONFAULT(t2)
ldq_u v0, 0(a0) /* get the word containing our byte */
extbl v0, a0, v0 /* extract the byte */
stq zero, PCB_ONFAULT(t2) /* clean up */
RET
END(fubyte)
LEAF(fusufault, 0)
ldq t0, PC_CURTHREAD(pcpup)
ldq t0, TD_PCB(t0)
stq zero, PCB_ONFAULT(t0)
ldiq v0, -1
RET
END(fusufault)
LEAF(fswintrberr, 0)
XLEAF(fuswintr, 2) /* XXX 16 bit short for profiling */
XLEAF(suswintr, 2) /* XXX 16 bit short for profiling */
LDGP(pv)
ldiq v0, -1
RET
END(fswintrberr)
/**************************************************************************/
/*
* Copy a null-terminated string within the kernel's address space.
* If lenp is not NULL, store the number of chars copied in *lenp
*
* int copystr(char *from, char *to, size_t len, size_t *lenp);
*/
LEAF(copystr, 4)
LDGP(pv)
mov a2, t0 /* t0 = i = len */
beq a2, Lcopystr2 /* if (len == 0), bail out */
Lcopystr1:
ldq_u t1, 0(a0) /* t1 = *from */
extbl t1, a0, t1
ldq_u t3, 0(a1) /* set up t2 with quad around *to */
insbl t1, a1, t2
mskbl t3, a1, t3
or t3, t2, t3 /* add *from to quad around *to */
stq_u t3, 0(a1) /* write out that quad */
subl a2, 1, a2 /* len-- */
beq t1, Lcopystr2 /* if (*from == 0), bail out */
addq a1, 1, a1 /* to++ */
addq a0, 1, a0 /* from++ */
bne a2, Lcopystr1 /* if (len != 0) copy more */
Lcopystr2:
beq a3, Lcopystr3 /* if (lenp != NULL) */
subl t0, a2, t0 /* *lenp = (i - len) */
stq t0, 0(a3)
Lcopystr3:
beq t1, Lcopystr4 /* *from == '\0'; leave quietly */
ldiq v0, ENAMETOOLONG /* *from != '\0'; error. */
RET
Lcopystr4:
mov zero, v0 /* return 0. */
RET
END(copystr)
NESTED(copyinstr, 4, 16, ra, 0, 0)
LDGP(pv)
lda sp, -16(sp) /* set up stack frame */
stq ra, (16-8)(sp) /* save ra */
ldiq t0, VM_MAXUSER_ADDRESS /* make sure that src addr */
cmpult a0, t0, t1 /* is in user space. */
beq t1, copyerr /* if it's not, error out. */
lda v0, copyerr /* set up fault handler. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup)
ldq at_reg, TD_PCB(at_reg)
stq v0, PCB_ONFAULT(at_reg)
.set at
CALL(copystr) /* do the copy. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup) /* kill the fault handler. */
ldq at_reg, TD_PCB(at_reg)
stq zero, PCB_ONFAULT(at_reg)
.set at
ldq ra, (16-8)(sp) /* restore ra. */
lda sp, 16(sp) /* kill stack frame. */
RET /* v0 left over from copystr */
END(copyinstr)
NESTED(copyoutstr, 4, 16, ra, 0, 0)
LDGP(pv)
lda sp, -16(sp) /* set up stack frame */
stq ra, (16-8)(sp) /* save ra */
ldiq t0, VM_MAXUSER_ADDRESS /* make sure that dest addr */
cmpult a1, t0, t1 /* is in user space. */
beq t1, copyerr /* if it's not, error out. */
lda v0, copyerr /* set up fault handler. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup)
ldq at_reg, TD_PCB(at_reg)
stq v0, PCB_ONFAULT(at_reg)
.set at
CALL(copystr) /* do the copy. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup) /* kill the fault handler. */
ldq at_reg, TD_PCB(at_reg)
stq zero, PCB_ONFAULT(at_reg)
.set at
ldq ra, (16-8)(sp) /* restore ra. */
lda sp, 16(sp) /* kill stack frame. */
RET /* v0 left over from copystr */
END(copyoutstr)
/*
* Alternative memory mover
*/
LEAF(memcpy,3)
mov a0,t0
mov a1,a0
mov t0,a1
br bcopy
END(memcpy)
/*
* Copy a bytes within the kernel's address space.
* Handles overlapping regions.
*
* void bcopy(char *from, char *to, size_t len);
*/
LEAF(bcopy,3)
/* Check for negative length */
ble a2,bcopy_done
/* Check for overlap */
subq a1,a0,t5
cmpult t5,a2,t5
bne t5,bcopy_overlap
/* a3 = end address */
addq a0,a2,a3
/* Get the first word */
ldq_u t2,0(a0)
/* Do they have the same alignment? */
xor a0,a1,t0
and t0,7,t0
and a1,7,t1
bne t0,bcopy_different_alignment
/* src & dst have same alignment */
beq t1,bcopy_all_aligned
ldq_u t3,0(a1)
addq a2,t1,a2
mskqh t2,a0,t2
mskql t3,a0,t3
or t2,t3,t2
/* Dst is 8-byte aligned */
bcopy_all_aligned:
/* If less than 8 bytes,skip loop */
subq a2,1,t0
and a2,7,a2
bic t0,7,t0
beq t0,bcopy_samealign_lp_end
bcopy_samealign_lp:
stq_u t2,0(a1)
addq a1,8,a1
ldq_u t2,8(a0)
subq t0,8,t0
addq a0,8,a0
bne t0,bcopy_samealign_lp
bcopy_samealign_lp_end:
/* If we're done, exit */
bne a2,bcopy_small_left
stq_u t2,0(a1)
RET
bcopy_small_left:
mskql t2,a2,t4
ldq_u t3,0(a1)
mskqh t3,a2,t3
or t4,t3,t4
stq_u t4,0(a1)
RET
bcopy_different_alignment:
/*
* this is the fun part
*/
addq a0,a2,a3
cmpule a2,8,t0
bne t0,bcopy_da_finish
beq t1,bcopy_da_noentry
/* Do the initial partial word */
subq zero,a1,t0
and t0,7,t0
ldq_u t3,7(a0)
extql t2,a0,t2
extqh t3,a0,t3
or t2,t3,t5
insql t5,a1,t5
ldq_u t6,0(a1)
mskql t6,a1,t6
or t5,t6,t5
stq_u t5,0(a1)
addq a0,t0,a0
addq a1,t0,a1
subq a2,t0,a2
ldq_u t2,0(a0)
bcopy_da_noentry:
subq a2,1,t0
bic t0,7,t0
and a2,7,a2
beq t0,bcopy_da_finish2
bcopy_da_lp:
ldq_u t3,7(a0)
addq a0,8,a0
extql t2,a0,t4
extqh t3,a0,t5
subq t0,8,t0
or t4,t5,t5
stq t5,0(a1)
addq a1,8,a1
beq t0,bcopy_da_finish1
ldq_u t2,7(a0)
addq a0,8,a0
extql t3,a0,t4
extqh t2,a0,t5
subq t0,8,t0
or t4,t5,t5
stq t5,0(a1)
addq a1,8,a1
bne t0,bcopy_da_lp
bcopy_da_finish2:
/* Do the last new word */
mov t2,t3
bcopy_da_finish1:
/* Do the last partial word */
ldq_u t2,-1(a3)
extql t3,a0,t3
extqh t2,a0,t2
or t2,t3,t2
br zero,bcopy_samealign_lp_end
bcopy_da_finish:
/* Do the last word in the next source word */
ldq_u t3,-1(a3)
extql t2,a0,t2
extqh t3,a0,t3
or t2,t3,t2
insqh t2,a1,t3
insql t2,a1,t2
lda t4,-1(zero)
mskql t4,a2,t5
cmovne t5,t5,t4
insqh t4,a1,t5
insql t4,a1,t4
addq a1,a2,a4
ldq_u t6,0(a1)
ldq_u t8,-1(a4)
bic t6,t4,t6
bic t8,t5,t8
and t2,t4,t2
and t3,t5,t3
or t2,t6,t2
or t3,t8,t3
stq_u t3,-1(a4)
stq_u t2,0(a1)
RET
bcopy_overlap:
/*
* Basically equivalent to previous case, only backwards.
* Not quite as highly optimized
*/
addq a0,a2,a3
addq a1,a2,a4
/* less than 8 bytes - don't worry about overlap */
cmpule a2,8,t0
bne t0,bcopy_ov_short
/* Possibly do a partial first word */
and a4,7,t4
beq t4,bcopy_ov_nostart2
subq a3,t4,a3
subq a4,t4,a4
ldq_u t1,0(a3)
subq a2,t4,a2
ldq_u t2,7(a3)
ldq t3,0(a4)
extql t1,a3,t1
extqh t2,a3,t2
or t1,t2,t1
mskqh t3,t4,t3
mskql t1,t4,t1
or t1,t3,t1
stq t1,0(a4)
bcopy_ov_nostart2:
bic a2,7,t4
and a2,7,a2
beq t4,bcopy_ov_lp_end
bcopy_ov_lp:
/* This could be more pipelined, but it doesn't seem worth it */
ldq_u t0,-8(a3)
subq a4,8,a4
ldq_u t1,-1(a3)
subq a3,8,a3
extql t0,a3,t0
extqh t1,a3,t1
subq t4,8,t4
or t0,t1,t0
stq t0,0(a4)
bne t4,bcopy_ov_lp
bcopy_ov_lp_end:
beq a2,bcopy_done
ldq_u t0,0(a0)
ldq_u t1,7(a0)
ldq_u t2,0(a1)
extql t0,a0,t0
extqh t1,a0,t1
or t0,t1,t0
insql t0,a1,t0
mskql t2,a1,t2
or t2,t0,t2
stq_u t2,0(a1)
bcopy_done:
RET
bcopy_ov_short:
ldq_u t2,0(a0)
br zero,bcopy_da_finish
END(bcopy)
NESTED(copyin, 3, 16, ra, 0, 0)
LDGP(pv)
lda sp, -16(sp) /* set up stack frame */
stq ra, (16-8)(sp) /* save ra */
ldiq t0, VM_MAXUSER_ADDRESS /* make sure that src addr */
cmpult a0, t0, t1 /* is in user space. */
beq t1, copyerr /* if it's not, error out. */
lda v0, copyerr /* set up fault handler. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup)
ldq at_reg, TD_PCB(at_reg)
stq v0, PCB_ONFAULT(at_reg)
.set at
CALL(bcopy) /* do the copy. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup) /* kill the fault handler. */
ldq at_reg, TD_PCB(at_reg)
stq zero, PCB_ONFAULT(at_reg)
.set at
ldq ra, (16-8)(sp) /* restore ra. */
lda sp, 16(sp) /* kill stack frame. */
mov zero, v0 /* return 0. */
RET
END(copyin)
NESTED(copyout, 3, 16, ra, 0, 0)
LDGP(pv)
lda sp, -16(sp) /* set up stack frame */
stq ra, (16-8)(sp) /* save ra */
ldiq t0, VM_MAXUSER_ADDRESS /* make sure that dest addr */
cmpult a1, t0, t1 /* is in user space. */
beq t1, copyerr /* if it's not, error out. */
lda v0, copyerr /* set up fault handler. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup)
ldq at_reg, TD_PCB(at_reg)
stq v0, PCB_ONFAULT(at_reg)
.set at
CALL(bcopy) /* do the copy. */
.set noat
ldq at_reg, PC_CURTHREAD(pcpup) /* kill the fault handler. */
ldq at_reg, TD_PCB(at_reg)
stq zero, PCB_ONFAULT(at_reg)
.set at
ldq ra, (16-8)(sp) /* restore ra. */
lda sp, 16(sp) /* kill stack frame. */
mov zero, v0 /* return 0. */
RET
END(copyout)
LEAF(copyerr, 0)
ldq t0, PC_CURTHREAD(pcpup)
ldq t0, TD_PCB(t0)
stq zero, PCB_ONFAULT(t0) /* reset fault handler. */
ldq ra, (16-8)(sp) /* restore ra. */
lda sp, 16(sp) /* kill stack frame. */
ldiq v0, EFAULT /* return EFAULT. */
RET
END(copyerr)
/**************************************************************************/
/*
* Kernel setjmp and longjmp. Rather minimalist.
*
* longjmp(label_t *a)
* will generate a "return (1)" from the last call to
* setjmp(label_t *a)
* by restoring registers from the stack,
*/
.set noreorder
LEAF(setjmp, 1)
LDGP(pv)
stq ra, (0 * 8)(a0) /* return address */
stq s0, (1 * 8)(a0) /* callee-saved registers */
stq s1, (2 * 8)(a0)
stq s2, (3 * 8)(a0)
stq s3, (4 * 8)(a0)
stq s4, (5 * 8)(a0)
stq s5, (6 * 8)(a0)
stq s6, (7 * 8)(a0)
stq sp, (8 * 8)(a0)
ldiq t0, 0xbeeffedadeadbabe /* set magic number */
stq t0, (9 * 8)(a0)
mov zero, v0 /* return zero */
RET
END(setjmp)
LEAF(longjmp, 1)
LDGP(pv)
ldiq t0, 0xbeeffedadeadbabe /* check magic number */
ldq t1, (9 * 8)(a0)
cmpeq t0, t1, t0
beq t0, longjmp_botch /* if bad, punt */
ldq ra, (0 * 8)(a0) /* return address */
ldq s0, (1 * 8)(a0) /* callee-saved registers */
ldq s1, (2 * 8)(a0)
ldq s2, (3 * 8)(a0)
ldq s3, (4 * 8)(a0)
ldq s4, (5 * 8)(a0)
ldq s5, (6 * 8)(a0)
ldq s6, (7 * 8)(a0)
ldq sp, (8 * 8)(a0)
ldiq v0, 1
RET
longjmp_botch:
lda a0, longjmp_botchmsg
mov ra, a1
CALL(panic)
call_pal PAL_bugchk
.data
longjmp_botchmsg:
.asciz "longjmp botch from %p"
.text
END(longjmp)

217
sys/alpha/alpha/swtch.s
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@ -1,217 +0,0 @@
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*
* $NetBSD: locore.s,v 1.47 1998/03/22 07:26:32 thorpej Exp $
* $FreeBSD$
*/
#define _LOCORE
#include <machine/asm.h>
#include <machine/mutex.h>
#include "assym.s"
/**************************************************************************/
/*
* Perform actions necessary to switch to a new context. The
* hwpcb should be in a0.
*/
#define SWITCH_CONTEXT \
/* Make a note of the context we're running on. */ \
stq a0, PC_CURPCB(pcpup); \
\
/* Swap in the new context. */ \
call_pal PAL_OSF1_swpctx
/*
* savectx: save process context, i.e. callee-saved registers
*
* Note that savectx() only works for threads other than curthread,
* since cpu_switch will copy over the info saved here. (It _can_
* sanely be used for curthread iff cpu_switch won't be called again, e.g.
* from if called from boot().)
*
* Arguments:
* a0 'struct pcb *' of the process that needs its context saved
*
* Return:
* v0 0. (note that for child processes, it seems
* like savectx() returns 1, because the return address
* in the PCB is set to the return address from savectx().)
*/
LEAF(savectx, 1)
br pv, Lsavectx1
Lsavectx1: LDGP(pv)
stq sp, PCB_HWPCB_KSP(a0) /* store sp */
stq s0, PCB_CONTEXT+(0 * 8)(a0) /* store s0 - s6 */
stq s1, PCB_CONTEXT+(1 * 8)(a0)
stq s2, PCB_CONTEXT+(2 * 8)(a0)
stq s3, PCB_CONTEXT+(3 * 8)(a0)
stq s4, PCB_CONTEXT+(4 * 8)(a0)
stq s5, PCB_CONTEXT+(5 * 8)(a0)
stq s6, PCB_CONTEXT+(6 * 8)(a0)
stq ra, PCB_CONTEXT+(7 * 8)(a0) /* store ra */
call_pal PAL_OSF1_rdps /* NOTE: doesn't kill a0 */
stq v0, PCB_CONTEXT+(8 * 8)(a0) /* store ps, for ipl */
mov zero, v0
RET
END(savectx)
/**************************************************************************/
IMPORT(Lev1map, 8)
/*
* cpu_throw()
* Switch to a new thread discarding our current state.
*
* Arguments:
* a0 'struct thread *' of the old thread
* a1 'struct thread *' of the new thread
*/
LEAF(cpu_throw, 0)
LDGP(pv)
CALL(Lcs1)
END(cpu_throw)
/*
* cpu_switch()
* Switch to a new thread saving the current state in the old thread.
*
* Arguments:
* a0 'struct thread *' of the old thread
* a1 'struct thread *' of the new thread
*/
LEAF(cpu_switch, 1)
LDGP(pv)
/* do an inline savectx(), to save old context */
ldq a2, TD_PCB(a0)
/* NOTE: ksp is stored by the swpctx */
stq s0, PCB_CONTEXT+(0 * 8)(a2) /* store s0 - s6 */
stq s1, PCB_CONTEXT+(1 * 8)(a2)
stq s2, PCB_CONTEXT+(2 * 8)(a2)
stq s3, PCB_CONTEXT+(3 * 8)(a2)
stq s4, PCB_CONTEXT+(4 * 8)(a2)
stq s5, PCB_CONTEXT+(5 * 8)(a2)
stq s6, PCB_CONTEXT+(6 * 8)(a2)
stq ra, PCB_CONTEXT+(7 * 8)(a2) /* store ra */
call_pal PAL_OSF1_rdps /* NOTE: doesn't kill a0 */
stq v0, PCB_CONTEXT+(8 * 8)(a2) /* store ps, for ipl */
mov a0, s0 /* s0 = old curthread */
mov a2, s1 /* s1 = old pcb */
/*
* Deactivate the old address space before activating the
* new one. We need to do this before activating the
* new thread's address space in the event that new
* thread is using the same vmspace as the old. If we
* do this after we activate, then we might end up
* incorrectly marking the pmap inactive!
*
* We don't deactivate if we came here from switch_exit
* (old pmap no longer exists; vmspace has been freed).
* oldproc will be NULL in this case. We have actually
* taken care of calling pmap_deactivate() in cpu_exit(),
* before the vmspace went away.
*/
beq a0, sw1
CALL(pmap_deactivate) /* pmap_deactivate(oldthread) */
sw1:
br pv, Lcs1
Lcs1: LDGP(pv)
mov a1, s2 /* s2 = new thread */
ldq s3, TD_MD_PCBPADDR(s2) /* s3 = new pcbpaddr */
#ifdef SMP
/*
* Save fp state if we have some.
*/
mov s0, a0 /* curthread */
ldiq a1, 1 /* clear fpcurthread */
CALL(alpha_fpstate_save)
#endif
/*
* Activate the new thread's address space and perform
* the actual context swap.
*/
mov s2, a0 /* pmap_activate(newthread) */
CALL(pmap_activate) /* XXXKSE */
mov s3, a0 /* swap the context */
SWITCH_CONTEXT
/*
* Now that the switch is done, update curthread and other
* globals.
*/
stq s2, PC_CURTHREAD(pcpup) /* curthread = p */
/*
* Now running on the new pcb.
* Restore registers and return.
*/
ldq t0, TD_PCB(s2)
/* NOTE: ksp is restored by the swpctx */
ldq s0, PCB_CONTEXT+(0 * 8)(t0) /* restore s0 - s6 */
ldq s1, PCB_CONTEXT+(1 * 8)(t0)
ldq s2, PCB_CONTEXT+(2 * 8)(t0)
ldq s3, PCB_CONTEXT+(3 * 8)(t0)
ldq s4, PCB_CONTEXT+(4 * 8)(t0)
ldq s5, PCB_CONTEXT+(5 * 8)(t0)
ldq s6, PCB_CONTEXT+(6 * 8)(t0)
ldq ra, PCB_CONTEXT+(7 * 8)(t0) /* restore ra */
ldiq v0, 1 /* possible ret to savectx() */
RET
END(cpu_switch)
/*
* fork_trampoline()
*
* Arrange for a function to be invoked neatly, after a cpu_switch().
*
* Invokes fork_exit() passing in three arguments: a callout function,
* an argument to the callout, and a trapframe pointer. For child processes
* returning from fork(2), the argument is a pointer to the child process.
*
* The callout function is in s0, the address to return to after executing
* fork_exit() is in s1, and the argument is in s2.
*/
LEAF(fork_trampoline, 0)
mov s1, ra
mov s0, a0
mov s2, a1
mov sp, a2
jmp zero, fork_exit
END(fork_trampoline)

216
sys/alpha/alpha/sys_machdep.c
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@ -1,216 +0,0 @@
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)sys_machdep.c 5.5 (Berkeley) 1/19/91
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_mac.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/lock.h>
#include <sys/mac.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/sysent.h>
#include <sys/sysproto.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <vm/vm_extern.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
#include <machine/sysarch.h>
#include <vm/vm_kern.h> /* for kernel_map */
#include <machine/fpu.h>
#ifndef _SYS_SYSPROTO_H_
struct sysarch_args {
int op;
char *parms;
};
#endif
static int alpha_sethae(struct thread *td, char *args);
static int alpha_get_fpmask(struct thread *td, char *args);
static int alpha_set_fpmask(struct thread *td, char *args);
static int alpha_set_uac(struct thread *td, char *args);
static int alpha_get_uac(struct thread *td, char *args);
int
sysarch(td, uap)
struct thread *td;
register struct sysarch_args *uap;
{
int error;
switch(uap->op) {
case ALPHA_SETHAE:
error = alpha_sethae(td, uap->parms);
break;
case ALPHA_GET_FPMASK:
error = alpha_get_fpmask(td, uap->parms);
break;
case ALPHA_SET_FPMASK:
error = alpha_set_fpmask(td, uap->parms);
break;
case ALPHA_SET_UAC:
error = alpha_set_uac(td, uap->parms);
break;
case ALPHA_GET_UAC:
error = alpha_get_uac(td, uap->parms);
break;
default:
error = EINVAL;
break;
}
return (error);
}
struct alpha_sethae_args {
u_int64_t hae;
};
static int
alpha_sethae(struct thread *td, char *args)
{
int error;
struct alpha_sethae_args ua;
error = copyin(args, &ua, sizeof(struct alpha_sethae_args));
if (error)
return (error);
#ifdef MAC
error = mac_check_sysarch_ioperm(td->td_ucred);
if (error)
return (error);
#endif
error = securelevel_gt(td->td_ucred, 0);
if (error)
return (error);
error = suser(td);
if (error)
return (error);
td->td_md.md_flags |= MDTD_HAEUSED;
td->td_md.md_hae = ua.hae;
return (0);
}
struct alpha_fpmask_args {
u_int64_t mask;
};
static int
alpha_get_fpmask(struct thread *td, char *args)
{
int error;
struct alpha_fpmask_args ua;
ua.mask = td->td_pcb->pcb_fp_control;
error = copyout(&ua, args, sizeof(struct alpha_fpmask_args));
return (error);
}
static int
alpha_set_fpmask(struct thread *td, char *args)
{
int error;
u_int64_t oldmask, *fp_control;
struct alpha_fpmask_args ua;
error = copyin(args, &ua, sizeof(struct alpha_fpmask_args));
if (error)
return (error);
fp_control = &td->td_pcb->pcb_fp_control;
oldmask = *fp_control;
*fp_control = ua.mask & IEEE_TRAP_ENABLE_MASK;
ua.mask = oldmask;
error = copyout(&ua, args, sizeof(struct alpha_fpmask_args));
return (error);
}
static int
alpha_set_uac(struct thread *td, char *args)
{
int error;
unsigned long uac;
struct proc *p, *pp;
error = copyin(args, &uac, sizeof(uac));
if (error)
return (error);
p = td->td_proc;
PROC_LOCK(p);
pp = p->p_pptr;
if (pp != NULL) {
PROC_LOCK(pp);
pp->p_md.md_uac = uac & MDP_UAC_MASK;
PROC_UNLOCK(pp);
}
PROC_UNLOCK(p);
return 0;
}
static int
alpha_get_uac(struct thread *td, char *args)
{
struct proc *p, *pp;
int error;
unsigned long uac;
p = td->td_proc;
error = ESRCH;
PROC_LOCK(p);
pp = p->p_pptr;
if (pp != NULL) {
PROC_LOCK(pp);
uac = pp->p_md.md_uac;
PROC_UNLOCK(pp);
PROC_UNLOCK(p);
error = copyout(&uac, args, sizeof(uac));
} else
PROC_UNLOCK(p);
return error;
}

1318
sys/alpha/alpha/trap.c
View File

File diff suppressed because it is too large Load Diff

121
sys/alpha/alpha/uio_machdep.c
View File

@ -1,121 +0,0 @@
/*-
* Copyright (c) 2004 Alan L. Cox <alc@cs.rice.edu>
* Copyright (c) 1982, 1986, 1991, 1993
* The Regents of the University of California. All rights reserved.
* (c) UNIX System Laboratories, Inc.
* All or some portions of this file are derived from material licensed
* to the University of California by American Telephone and Telegraph
* Co. or Unix System Laboratories, Inc. and are reproduced herein with
* the permission of UNIX System Laboratories, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)kern_subr.c 8.3 (Berkeley) 1/21/94
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/systm.h>
#include <sys/uio.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <machine/vmparam.h>
/*
* Implement uiomove(9) from physical memory using the direct map to
* avoid the creation and destruction of ephemeral mappings.
*/
int
uiomove_fromphys(vm_page_t ma[], vm_offset_t offset, int n, struct uio *uio)
{
struct thread *td = curthread;
struct iovec *iov;
void *cp;
vm_offset_t page_offset;
size_t cnt;
int error = 0;
int save = 0;
KASSERT(uio->uio_rw == UIO_READ || uio->uio_rw == UIO_WRITE,
("uiomove_fromphys: mode"));
KASSERT(uio->uio_segflg != UIO_USERSPACE || uio->uio_td == curthread,
("uiomove_fromphys proc"));
save = td->td_pflags & TDP_DEADLKTREAT;
td->td_pflags |= TDP_DEADLKTREAT;
while (n > 0 && uio->uio_resid) {
iov = uio->uio_iov;
cnt = iov->iov_len;
if (cnt == 0) {
uio->uio_iov++;
uio->uio_iovcnt--;
continue;
}
if (cnt > n)
cnt = n;
page_offset = offset & PAGE_MASK;
cnt = min(cnt, PAGE_SIZE - page_offset);
cp = (char *)
ALPHA_PHYS_TO_K0SEG(ma[offset >> PAGE_SHIFT]->phys_addr) +
page_offset;
switch (uio->uio_segflg) {
case UIO_USERSPACE:
if (ticks - PCPU_GET(switchticks) >= hogticks)
uio_yield();
if (uio->uio_rw == UIO_READ)
error = copyout(cp, iov->iov_base, cnt);
else
error = copyin(iov->iov_base, cp, cnt);
if (error)
goto out;
break;
case UIO_SYSSPACE:
if (uio->uio_rw == UIO_READ)
bcopy(cp, iov->iov_base, cnt);
else
bcopy(iov->iov_base, cp, cnt);
break;
case UIO_NOCOPY:
break;
}
iov->iov_base = (char *)iov->iov_base + cnt;
iov->iov_len -= cnt;
uio->uio_resid -= cnt;
uio->uio_offset += cnt;
offset += cnt;
n -= cnt;
}
out:
if (save == 0)
td->td_pflags &= ~TDP_DEADLKTREAT;
return (error);
}

82
sys/alpha/alpha/uma_machdep.c
View File

@ -1,82 +0,0 @@
/*-
* Copyright (c) 2004 Alan L. Cox <alc@cs.rice.edu>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/systm.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>
#include <vm/uma.h>
#include <vm/uma_int.h>
#include <machine/md_var.h>
#include <machine/vmparam.h>
void *
uma_small_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
{
static vm_pindex_t color;
vm_page_t m;
void *va;
int pflags;
*flags = UMA_SLAB_PRIV;
if ((wait & (M_NOWAIT | M_USE_RESERVE)) == M_NOWAIT)
pflags = VM_ALLOC_INTERRUPT;
else
pflags = VM_ALLOC_SYSTEM;
if (wait & M_ZERO)
pflags |= VM_ALLOC_ZERO;
for (;;) {
m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ);
if (m == NULL) {
if (wait & M_NOWAIT)
return (NULL);
else
VM_WAIT;
} else
break;
}
va = (void *)ALPHA_PHYS_TO_K0SEG(m->phys_addr);
if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
bzero(va, PAGE_SIZE);
return (va);
}
void
uma_small_free(void *mem, int size, u_int8_t flags)
{
vm_page_t m;
m = PHYS_TO_VM_PAGE(ALPHA_K0SEG_TO_PHYS((vm_offset_t)mem));
vm_page_lock_queues();
vm_page_free(m);
vm_page_unlock_queues();
}

432
sys/alpha/alpha/vm_machdep.c
View File

@ -1,432 +0,0 @@
/*-
* Copyright (c) 1982, 1986 The Regents of the University of California.
* Copyright (c) 1989, 1990 William Jolitz
* Copyright (c) 1994 John Dyson
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department, and William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)vm_machdep.c 7.3 (Berkeley) 5/13/91
* Utah $Hdr: vm_machdep.c 1.16.1.1 89/06/23$
*/
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/proc.h>
#include <sys/malloc.h>
#include <sys/bio.h>
#include <sys/buf.h>
#include <sys/cons.h>
#include <sys/mutex.h>
#include <sys/vnode.h>
#include <sys/vmmeter.h>
#include <sys/kernel.h>
#include <sys/mbuf.h>
#include <sys/sf_buf.h>
#include <sys/sysctl.h>
#include <sys/unistd.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/fpu.h>
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <machine/prom.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <sys/lock.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <vm/vm_extern.h>
/*
* Finish a fork operation, with process p2 nearly set up.
* Copy and update the pcb, set up the stack so that the child
* ready to run and return to user mode.
*/
void
cpu_fork(td1, p2, td2, flags)
register struct thread *td1;
register struct proc *p2;
register struct thread *td2;
int flags;
{
struct proc *p1;
struct trapframe *p2tf;
if ((flags & RFPROC) == 0)
return;
p1 = td1->td_proc;
td2->td_pcb = (struct pcb *)
(td2->td_kstack + td2->td_kstack_pages * PAGE_SIZE) - 1;
td2->td_md.md_flags = td1->td_md.md_flags & MDTD_FPUSED;
PROC_LOCK(p2);
p2->p_md.md_uac = p1->p_md.md_uac;
PROC_UNLOCK(p2);
/*
* Cache the physical address of the pcb, so we can
* swap to it easily.
*/
td2->td_md.md_pcbpaddr = (void*)vtophys((vm_offset_t)td2->td_pcb);
/*
* Copy floating point state from the FP chip to the PCB
* if this process has state stored there.
*/
alpha_fpstate_save(td1, 0);
/*
* Copy pcb and stack from proc p1 to p2. We do this as
* cheaply as possible, copying only the active part of the
* stack. The stack and pcb need to agree. Make sure that the
* new process has FEN disabled.
*/
bcopy(td1->td_pcb, td2->td_pcb, sizeof(struct pcb));
td2->td_pcb->pcb_hw.apcb_usp = alpha_pal_rdusp();
td2->td_pcb->pcb_hw.apcb_unique = 0;
td2->td_pcb->pcb_hw.apcb_flags &= ~ALPHA_PCB_FLAGS_FEN;
/*
* Set the floating point state.
*/
if ((td2->td_pcb->pcb_fp_control & IEEE_INHERIT) == 0) {
td2->td_pcb->pcb_fp_control = 0;
td2->td_pcb->pcb_fp.fpr_cr = (FPCR_DYN_NORMAL
| FPCR_INVD | FPCR_DZED
| FPCR_OVFD | FPCR_INED
| FPCR_UNFD);
}
/*
* Arrange for a non-local goto when the new process
* is started, to resume here, returning nonzero from setjmp.
*/
#ifdef DIAGNOSTIC
alpha_fpstate_check(td1);
#endif
/*
* Create the child's kernel stack, from scratch.
*
* Pick a stack pointer, leaving room for a trapframe;
* copy trapframe from parent so return to user mode
* will be to right address, with correct registers.
*/
td2->td_frame = (struct trapframe *)td2->td_pcb - 1;
bcopy(td1->td_frame, td2->td_frame, sizeof(struct trapframe));
/*
* Set up return-value registers as fork() libc stub expects.
*/
p2tf = td2->td_frame;
p2tf->tf_regs[FRAME_V0] = 0; /* child's pid (linux) */
p2tf->tf_regs[FRAME_A3] = 0; /* no error */
p2tf->tf_regs[FRAME_A4] = 1; /* is child (FreeBSD) */
/*
* Arrange for continuation at fork_return(), which
* will return to exception_return(). Note that the child
* process doesn't stay in the kernel for long!
*/
td2->td_pcb->pcb_hw.apcb_ksp = (u_int64_t)p2tf;
td2->td_pcb->pcb_context[0] = (u_int64_t)fork_return; /* s0: a0 */
td2->td_pcb->pcb_context[1] = (u_int64_t)exception_return;/* s1: ra */
td2->td_pcb->pcb_context[2] = (u_long)td2; /* s2: a1 */
td2->td_pcb->pcb_context[7] = (u_int64_t)fork_trampoline; /* ra: magic*/
#ifdef SMP
/*
* We start off at a nesting level of 1 within the kernel.
*/
td2->td_md.md_kernnest = 1;
#endif
/* Setup to release sched_lock in fork_exit(). */
td2->td_md.md_spinlock_count = 1;
td2->td_md.md_saved_ipl = ALPHA_PSL_IPL_0;
}
/*
* Intercept the return address from a freshly forked process that has NOT
* been scheduled yet.
*
* This is needed to make kernel threads stay in kernel mode.
*/
void
cpu_set_fork_handler(td, func, arg)
struct thread *td;
void (*func)(void *);
void *arg;
{
/*
* Note that the trap frame follows the args, so the function
* is really called like this: func(arg, frame);
*/
td->td_pcb->pcb_context[0] = (u_long) func;
td->td_pcb->pcb_context[2] = (u_long) arg;
}
void
cpu_exit(struct thread *td)
{
/*
* XXX: Should this be in thread_exit instead? If so,
* alpha_fpstate_save() should be in cpu_set_upcall()
* as well.
*/
alpha_fpstate_drop(td);
}
void
cpu_thread_exit(struct thread *td)
{
}
void
cpu_thread_clean(struct thread *td)
{
}
void
cpu_thread_setup(struct thread *td)
{
td->td_pcb =
(struct pcb *)(td->td_kstack + td->td_kstack_pages * PAGE_SIZE) - 1;
td->td_md.md_pcbpaddr = (void*)vtophys((vm_offset_t)td->td_pcb);
td->td_frame = (struct trapframe *)((caddr_t)td->td_pcb) - 1;
}
void
cpu_thread_swapin(struct thread *td)
{
/*
* The pcb may be at a different physical address now so cache the
* new address.
*/
td->td_md.md_pcbpaddr = (void *)vtophys((vm_offset_t)td->td_pcb);
}
void
cpu_thread_swapout(struct thread *td)
{
/* Make sure we aren't fpcurthread. */
alpha_fpstate_save(td, 1);
}
void
cpu_set_upcall(struct thread *td, struct thread *td0)
{
struct pcb *pcb2;
/* Point the pcb to the top of the stack. */
pcb2 = td->td_pcb;
/*
* Copy the upcall pcb. This loads kernel regs.
* Those not loaded individually below get their default
* values here.
*
* XXXKSE It might be a good idea to simply skip this as
* the values of the other registers may be unimportant.
* This would remove any requirement for knowing the KSE
* at this time (see the matching comment below for
* more analysis) (need a good safe default).
*/
bcopy(td0->td_pcb, pcb2, sizeof(*pcb2));
/*
* Create a new fresh stack for the new thread.
* Don't forget to set this stack value into whatever supplies
* the address for the fault handlers.
* The contexts are filled in at the time we actually DO the
* upcall as only then do we know which KSE we got.
*/
bcopy(td0->td_frame, td->td_frame, sizeof(struct trapframe));
/*
* Arrange for continuation at fork_return(), which
* will return to exception_return(). Note that the child
* process doesn't stay in the kernel for long!
*/
pcb2->pcb_hw.apcb_ksp = (u_int64_t)td->td_frame;
pcb2->pcb_context[0] = (u_int64_t)fork_return; /* s0: a0 */
pcb2->pcb_context[1] = (u_int64_t)exception_return; /* s1: ra */
pcb2->pcb_context[2] = (u_long)td; /* s2: a1 */
pcb2->pcb_context[7] = (u_int64_t)fork_trampoline; /* ra: magic*/
#ifdef SMP
/*
* We start off at a nesting level of 1 within the kernel.
*/
td->td_md.md_kernnest = 1;
#endif
/* Setup to release sched_lock in fork_exit(). */
td->td_md.md_spinlock_count = 1;
td->td_md.md_saved_ipl = ALPHA_PSL_IPL_0;
}
void
cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
stack_t *stack)
{
struct pcb *pcb;
struct trapframe *tf;
uint64_t sp;
pcb = td->td_pcb;
tf = td->td_frame;
sp = ((uint64_t)stack->ss_sp + stack->ss_size) & ~15;
bzero(tf->tf_regs, FRAME_SIZE * sizeof(tf->tf_regs[0]));
bzero(&pcb->pcb_fp, sizeof(pcb->pcb_fp));
pcb->pcb_fp_control = 0;
pcb->pcb_fp.fpr_cr = FPCR_DYN_NORMAL | FPCR_INVD | FPCR_DZED |
FPCR_OVFD | FPCR_INED | FPCR_UNFD;
if (td != curthread) {
pcb->pcb_hw.apcb_usp = sp;
pcb->pcb_hw.apcb_unique = 0;
} else {
alpha_pal_wrusp(sp);
alpha_pal_wrunique(0);
}
tf->tf_regs[FRAME_PS] = ALPHA_PSL_USERSET;
tf->tf_regs[FRAME_PC] = (u_long)entry;
tf->tf_regs[FRAME_A0] = (u_long)arg;
tf->tf_regs[FRAME_T12] = tf->tf_regs[FRAME_PC]; /* aka. PV */
tf->tf_regs[FRAME_FLAGS] = 0; /* full restore */
}
int
cpu_set_user_tls(struct thread *td, void *tls_base)
{
if (td != curthread)
td->td_pcb->pcb_hw.apcb_unique = (unsigned long)tls_base;
else
alpha_pal_wrunique((uintptr_t)tls_base);
return (0);
}
/*
* Reset back to firmware.
*/
void
cpu_reset()
{
prom_halt(0);
}
/*
* Allocate an sf_buf for the given vm_page. On this machine, however, there
* is no sf_buf object. Instead, an opaque pointer to the given vm_page is
* returned.
*/
struct sf_buf *
sf_buf_alloc(struct vm_page *m, int pri)
{
return ((struct sf_buf *)m);
}
/*
* Free the sf_buf. In fact, do nothing because there are no resources
* associated with the sf_buf.
*/
void
sf_buf_free(struct sf_buf *sf)
{
}
/*
* Software interrupt handler for queued VM system processing.
*/
void
swi_vm(void *dummy)
{
if (busdma_swi_pending != 0)
busdma_swi();
}
/*
* Tell whether this address is in some physical memory region.
* Currently used by the kernel coredump code in order to avoid
* dumping the ``ISA memory hole'' which could cause indefinite hangs,
* or other unpredictable behaviour.
*/
int
is_physical_memory(addr)
vm_offset_t addr;
{
/*
* stuff other tests for known memory-mapped devices (PCI?)
* here
*/
return 1;
}

1
sys/alpha/compile/.cvsignore
View File

@ -1 +0,0 @@
[A-Za-z0-9]*

1
sys/alpha/conf/.cvsignore
View File

@ -1 +0,0 @@
[A-Za-z0-9]*

9
sys/alpha/conf/DEFAULTS
View File

@ -1,9 +0,0 @@
#
# DEFAULTS -- Default kernel configuration file for FreeBSD/alpha
#
# $FreeBSD$
machine alpha
# Pseudo devices.
device mem # Memory and kernel memory devices

222
sys/alpha/conf/GENERIC
View File

@ -1,222 +0,0 @@
#
# GENERIC -- Generic kernel configuration file for FreeBSD/alpha
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# For hardware specific information check HARDWARE.TXT
#
# $FreeBSD$
cpu EV4
cpu EV5
ident GENERIC
# To statically compile in device wiring instead of /boot/device.hints
#hints "GENERIC.hints" # Default places to look for devices.
makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
# Platforms supported
options API_UP1000 # UP1000, UP1100 (Nautilus)
options DEC_EB164 # EB164, PC164, PC164LX, PC164SX
options DEC_EB64PLUS # EB64+, AlphaPC64, Aspen Alpine, etc
options DEC_2100_A50 # AlphaStation 200, 250, 255, 400
options DEC_2100_A500 # AlphaServer 2000, 2100, 2100A
options DEC_KN20AA # AlphaStation 500, 600
options DEC_ST550 # Personal Workstation 433, 500, 600
options DEC_ST6600 # XP1000, DP264, DS20, DS10, family
options DEC_1000A # AlphaServer 1000, 1000A, 800
options DEC_KN300 # AlphaServer 4100 (Rawhide),
# AlphaServer 1200 (Tincup)
#options SCHED_ULE # ULE scheduler
options SCHED_4BSD # 4BSD scheduler
options PREEMPTION # Enable kernel thread preemption
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options FFS # Berkeley Fast Filesystem
options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big directories
options MD_ROOT # MD is a potential root device
options NFSCLIENT # Network Filesystem Client
options NFSSERVER # Network Filesystem Server
options NFS_ROOT # NFS usable as /, requires NFSCLIENT
options MSDOSFS # MSDOS Filesystem
options CD9660 # ISO 9660 Filesystem
options PROCFS # Process filesystem (requires PSEUDOFS)
options PSEUDOFS # Pseudo-filesystem framework
options GEOM_GPT # GUID Partition Tables.
options COMPAT_43 # Compatible with BSD 4.3 [KEEP THIS!]
options COMPAT_43TTY # BSD 4.3 TTY compat [KEEP THIS!]
options COMPAT_FREEBSD4 # Compatible with FreeBSD4
options COMPAT_FREEBSD5 # Compatible with FreeBSD5
options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI
options KTRACE # ktrace(1) support
options SYSVSHM # SYSV-style shared memory
options SYSVMSG # SYSV-style message queues
options SYSVSEM # SYSV-style semaphores
options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
options ADAPTIVE_GIANT # Giant mutex is adaptive.
# Debugging for use in -current
options KDB # Enable kernel debugger support.
options DDB # Support DDB.
options GDB # Support remote GDB.
options INVARIANTS # Enable calls of extra sanity checking
options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS # Enable checks to detect deadlocks and cycles
options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
# To make an SMP kernel, the next line is needed
options SMP # Symmetric MultiProcessor Kernel
# Alpha's do not appear to react well to probing high EISA slots
options EISA_SLOTS=2
# Standard busses
device isa
device eisa
device pci
# Floppy drives
device fdc
# ATA and ATAPI devices
device ata
device atadisk # ATA disk drives
device atapicd # ATAPI CDROM drives
device atapifd # ATAPI floppy drives
device atapist # ATAPI tape drives
# SCSI Controllers
device ahc # AHA2940 and onboard AIC7xxx devices
options AHC_REG_PRETTY_PRINT # Print register bitfields in debug
# output. Adds ~128k to driver.
device isp # Qlogic family
device ispfw # Firmware module for Qlogic host adapters
device mpt # LSI-Logic MPT-Fusion
#device ncr # NCR/Symbios Logic
device sym # NCR/Symbios Logic (newer chipsets + those of `ncr')
# SCSI peripherals
device scbus # SCSI bus (required for SCSI)
device ch # SCSI media changers
device da # Direct Access (disks)
device sa # Sequential Access (tape etc)
device cd # CD
device pass # Passthrough device (direct SCSI access)
device ses # SCSI Environmental Services (and SAF-TE)
# RAID controllers interfaced to the SCSI subsystem
device amr # AMI MegaRAID
# RAID controllers
device mlx # Mylex DAC960 family
# atkbdc0 controls both the keyboard and the PS/2 mouse
device atkbdc # AT keyboard controller
device atkbd # AT keyboard
device psm # PS/2 mouse
device vga # VGA video card driver
# TGA support is broken
# device tga # TGA video card driver
device splash # Splash screen and screen saver support
# syscons is the default console driver, resembling an SCO console
device sc
device mcclock # MC146818 real time clock device
# Serial (COM) ports
device sio # 8250, 16[45]50 based serial ports
device uart # Generic UART driver
# Parallel port
device ppc
device ppbus # Parallel port bus (required)
device lpt # Printer
device ppi # Parallel port interface device
#device vpo # Requires scbus and da
# If you've got a "dumb" serial or parallel PCI card that is
# supported by the puc(4) glue driver, uncomment the following
# line to enable it (connects to sio, uart and/or ppc drivers):
#device puc
# PCI Ethernet NICs.
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
device txp # 3Com 3cR990 (``Typhoon'')
device vx # 3Com 3c590, 3c595 (``Vortex'')
# PCI Ethernet NICs that use the common MII bus controller code.
# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs!
device miibus # MII bus support
device dc # DEC/Intel 21143 and various workalikes
device fxp # Intel EtherExpress PRO/100B (82557, 82558)
device nge # NatSemi DP83820 gigabit ethernet
device pcn # AMD Am79C97x PCI 10/100 NICs
device rl # RealTek 8129/8139
device sf # Adaptec AIC-6915 (``Starfire'')
device sis # Silicon Integrated Systems SiS 900/SiS 7016
device ste # Sundance ST201 (D-Link DFE-550TX)
device tl # Texas Instruments ThunderLAN
device vr # VIA Rhine, Rhine II
device wb # Winbond W89C840F
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
# Pseudo devices.
device loop # Network loopback
device random # Entropy device
device ether # Ethernet support
device sl # Kernel SLIP
device ppp # Kernel PPP
device tun # Packet tunnel.
device pty # Pseudo-ttys (telnet etc)
device md # Memory "disks"
device gif # IPv6 and IPv4 tunneling
device faith # IPv6-to-IPv4 relaying (translation)
# The `bpf' device enables the Berkeley Packet Filter.
# Be aware of the administrative consequences of enabling this!
# Note that 'bpf' is required for DHCP.
device bpf # Berkeley packet filter
# USB support
device uhci # UHCI PCI->USB interface
device ohci # OHCI PCI->USB interface
device usb # USB Bus (required)
device ugen # Generic
device uhid # "Human Interface Devices"
device ukbd # Keyboard
device ulpt # Printer
device umass # Disks/Mass storage - Requires scbus and da
device ums # Mouse
# USB Ethernet, requires miibus
device aue # ADMtek USB Ethernet
device axe # ASIX Electronics USB Ethernet
device cdce # Generic USB over Ethernet
device cue # CATC USB Ethernet
device kue # Kawasaki LSI USB Ethernet
device rue # RealTek RTL8150 USB Ethernet
# FireWire support
device firewire # FireWire bus code
device sbp # SCSI over FireWire (Requires scbus and da)
device fwe # Ethernet over FireWire (non-standard!)

41
sys/alpha/conf/GENERIC.hints
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@ -1,41 +0,0 @@
# $FreeBSD$
hint.fdc.0.at="isa"
hint.fdc.0.port="0x3F0"
hint.fdc.0.irq="6"
hint.fdc.0.drq="2"
hint.fd.0.at="fdc0"
hint.fd.0.drive="0"
hint.fd.0.flags="4"
hint.ata.0.at="isa"
hint.ata.0.port="0x1F0"
hint.ata.0.irq="14"
hint.ata.1.at="isa"
hint.ata.1.port="0x170"
hint.ata.1.irq="15"
hint.atkbdc.0.at="isa"
hint.atkbdc.0.port="0x060"
hint.atkbd.0.at="atkbdc"
hint.atkbd.0.irq="1"
hint.psm.0.at="atkbdc"
hint.psm.0.irq="12"
hint.vga.0.at="isa"
hint.sc.0.at="isa"
hint.mcclock.0.at="isa"
hint.mcclock.0.port="0x70"
hint.sio.0.at="isa"
hint.sio.0.port="0x3F8"
hint.sio.0.irq="4"
hint.sio.0.flags="0x10"
hint.sio.1.at="isa"
hint.sio.1.port="0x2F8"
hint.sio.1.irq="3"
hint.sio.1.flags="0x80"
hint.ppc.0.at="isa"
hint.ppc.0.irq="7"
hint.uart.0.at="isa"
hint.uart.0.irq="4"
hint.uart.0.port="0x3F8"
hint.uart.1.at="isa"
hint.uart.1.flags="0x80"
hint.uart.1.irq="3"
hint.uart.1.port="0x2F8"

28
sys/alpha/conf/MAC
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@ -1,28 +0,0 @@
# MAC -- Generic kernel configuration file for FreeBSD/alpha MAC
#
# The Mandatory Access Control, or MAC, framework allows administrators to
# finely control system security by providing for a loadable security pol-
# icy architecture.
#
# For more information see:
#
# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/mac.html
#
# $FreeBSD$
include GENERIC
ident MAC
options MAC
#options MAC_BIBA # BIBA data integrity policy
#options MAC_BSDEXTENDED # File system firewall policy
#options MAC_IFOFF # Network interface silencing policy
#options MAC_LOMAC # Low-watermark data integrity policy
#options MAC_MLS # Multi-level confidentiality policy
#options MAC_NONE # NULL policy
#options MAC_PARTITION # Process partition policy
#options MAC_PORTACL # Network port access control policy
#options MAC_SEEOTHERUIDS # UID visibility policy
#options MAC_STUB # Stub policy
#options MAC_TEST # Testing policy for the MAC framework

3
sys/alpha/conf/Makefile
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@ -1,3 +0,0 @@
# $FreeBSD$
.include "${.CURDIR}/../../conf/makeLINT.mk"

64
sys/alpha/conf/NOTES
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@ -1,64 +0,0 @@
# $FreeBSD$
#
# This file contains machine dependent kernel configuration notes. For
# machine independent notes, look in /sys/conf/NOTES.
#####################################################################
# CPU OPTIONS
#
# You must specify at least one CPU (the one you intend to run on);
# deleting the specification for CPUs you don't need to use may make
# parts of the system run faster.
# XXX: On the Alpha, CPU types are never used. This list also does
# not include newer CPU types that are supported such as the EV6.
cpu EV4
cpu EV5
#####################################################################
# PLATFORM OPTIONS
options API_UP1000 # UP1000, UP1100 (Nautilus)
options DEC_EB164 # EB164, PC164, PC164LX, PC164SX
options DEC_EB64PLUS # EB64+, AlphaPC64, Aspen Alpine, etc
options DEC_2100_A50 # AlphaStation 200, 250, 255, 400
options DEC_2100_A500 # AlphaServer 2000, 2100, 2100A
options DEC_KN20AA # AlphaStation 500, 600
options DEC_ST550 # Personal Workstation 433, 500, 600
options DEC_ST6600 # XP1000, DP264, DS20, DS10, family
options DEC_1000A # AlphaServer 1000, 1000A, 800
options DEC_KN300 # AlphaServer 4100 (Rawhide),
# AlphaServer 1200 (Tincup)
#####################################################################
# HARDWARE BUS CONFIGURATION
device isa
device eisa
device pci
#####################################################################
# HARDWARE DEVICE CONFIGURATION
#
# Mandatory devices:
#
device mcclock # MC146818 real time clock device
#
# Optional devices:
#
device tga # TGA video card driver
#####################################################################
# ABI Emulation
# Enable OSF/1 ABI emulation
options COMPAT_OSF1

42
sys/alpha/include/_bus.h
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@ -1,42 +0,0 @@
/*-
* Copyright (c) 2005 M. Warner Losh.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef ALPHA_INCLUDE__BUS_H
#define ALPHA_INCLUDE__BUS_H
/*
* Bus address and size types
*/
typedef u_int64_t bus_addr_t;
typedef u_int64_t bus_size_t;
typedef struct alpha_busspace *bus_space_tag_t;
typedef u_int32_t bus_space_handle_t;
#endif /* ALPHA_INCLUDE__BUS_H */

220
sys/alpha/include/_inttypes.h
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@ -1,220 +0,0 @@
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $
* $FreeBSD$
*/
#ifndef _MACHINE_INTTYPES_H_
#define _MACHINE_INTTYPES_H_
/*
* Macros for format specifiers.
*/
/* fprintf(3) macros for signed integers. */
#define PRId8 "d" /* int8_t */
#define PRId16 "d" /* int16_t */
#define PRId32 "d" /* int32_t */
#define PRId64 "ld" /* int64_t */
#define PRIdLEAST8 "d" /* int_least8_t */
#define PRIdLEAST16 "d" /* int_least16_t */
#define PRIdLEAST32 "d" /* int_least32_t */
#define PRIdLEAST64 "ld" /* int_least64_t */
#define PRIdFAST8 "d" /* int_fast8_t */
#define PRIdFAST16 "d" /* int_fast16_t */
#define PRIdFAST32 "d" /* int_fast32_t */
#define PRIdFAST64 "ld" /* int_fast64_t */
#define PRIdMAX "jd" /* intmax_t */
#define PRIdPTR "ld" /* intptr_t */
#define PRIi8 "i" /* int8_t */
#define PRIi16 "i" /* int16_t */
#define PRIi32 "i" /* int32_t */
#define PRIi64 "li" /* int64_t */
#define PRIiLEAST8 "i" /* int_least8_t */
#define PRIiLEAST16 "i" /* int_least16_t */
#define PRIiLEAST32 "i" /* int_least32_t */
#define PRIiLEAST64 "li" /* int_least64_t */
#define PRIiFAST8 "i" /* int_fast8_t */
#define PRIiFAST16 "i" /* int_fast16_t */
#define PRIiFAST32 "i" /* int_fast32_t */
#define PRIiFAST64 "li" /* int_fast64_t */
#define PRIiMAX "ji" /* intmax_t */
#define PRIiPTR "li" /* intptr_t */
/* fprintf(3) macros for unsigned integers. */
#define PRIo8 "o" /* uint8_t */
#define PRIo16 "o" /* uint16_t */
#define PRIo32 "o" /* uint32_t */
#define PRIo64 "lo" /* uint64_t */
#define PRIoLEAST8 "o" /* uint_least8_t */
#define PRIoLEAST16 "o" /* uint_least16_t */
#define PRIoLEAST32 "o" /* uint_least32_t */
#define PRIoLEAST64 "lo" /* uint_least64_t */
#define PRIoFAST8 "o" /* uint_fast8_t */
#define PRIoFAST16 "o" /* uint_fast16_t */
#define PRIoFAST32 "o" /* uint_fast32_t */
#define PRIoFAST64 "lo" /* uint_fast64_t */
#define PRIoMAX "jo" /* uintmax_t */
#define PRIoPTR "lo" /* uintptr_t */
#define PRIu8 "u" /* uint8_t */
#define PRIu16 "u" /* uint16_t */
#define PRIu32 "u" /* uint32_t */
#define PRIu64 "lu" /* uint64_t */
#define PRIuLEAST8 "u" /* uint_least8_t */
#define PRIuLEAST16 "u" /* uint_least16_t */
#define PRIuLEAST32 "u" /* uint_least32_t */
#define PRIuLEAST64 "lu" /* uint_least64_t */
#define PRIuFAST8 "u" /* uint_fast8_t */
#define PRIuFAST16 "u" /* uint_fast16_t */
#define PRIuFAST32 "u" /* uint_fast32_t */
#define PRIuFAST64 "lu" /* uint_fast64_t */
#define PRIuMAX "ju" /* uintmax_t */
#define PRIuPTR "lu" /* uintptr_t */
#define PRIx8 "x" /* uint8_t */
#define PRIx16 "x" /* uint16_t */
#define PRIx32 "x" /* uint32_t */
#define PRIx64 "lx" /* uint64_t */
#define PRIxLEAST8 "x" /* uint_least8_t */
#define PRIxLEAST16 "x" /* uint_least16_t */
#define PRIxLEAST32 "x" /* uint_least32_t */
#define PRIxLEAST64 "lx" /* uint_least64_t */
#define PRIxFAST8 "x" /* uint_fast8_t */
#define PRIxFAST16 "x" /* uint_fast16_t */
#define PRIxFAST32 "x" /* uint_fast32_t */
#define PRIxFAST64 "lx" /* uint_fast64_t */
#define PRIxMAX "jx" /* uintmax_t */
#define PRIxPTR "lx" /* uintptr_t */
#define PRIX8 "X" /* uint8_t */
#define PRIX16 "X" /* uint16_t */
#define PRIX32 "X" /* uint32_t */
#define PRIX64 "lX" /* uint64_t */
#define PRIXLEAST8 "X" /* uint_least8_t */
#define PRIXLEAST16 "X" /* uint_least16_t */
#define PRIXLEAST32 "X" /* uint_least32_t */
#define PRIXLEAST64 "lX" /* uint_least64_t */
#define PRIXFAST8 "X" /* uint_fast8_t */
#define PRIXFAST16 "X" /* uint_fast16_t */
#define PRIXFAST32 "X" /* uint_fast32_t */
#define PRIXFAST64 "lX" /* uint_fast64_t */
#define PRIXMAX "jX" /* uintmax_t */
#define PRIXPTR "lX" /* uintptr_t */
/* fscanf(3) macros for signed integers. */
#define SCNd8 "hhd" /* int8_t */
#define SCNd16 "hd" /* int16_t */
#define SCNd32 "d" /* int32_t */
#define SCNd64 "ld" /* int64_t */
#define SCNdLEAST8 "hhd" /* int_least8_t */
#define SCNdLEAST16 "hd" /* int_least16_t */
#define SCNdLEAST32 "d" /* int_least32_t */
#define SCNdLEAST64 "ld" /* int_least64_t */
#define SCNdFAST8 "d" /* int_fast8_t */
#define SCNdFAST16 "d" /* int_fast16_t */
#define SCNdFAST32 "d" /* int_fast32_t */
#define SCNdFAST64 "ld" /* int_fast64_t */
#define SCNdMAX "jd" /* intmax_t */
#define SCNdPTR "ld" /* intptr_t */
#define SCNi8 "hhi" /* int8_t */
#define SCNi16 "hi" /* int16_t */
#define SCNi32 "i" /* int32_t */
#define SCNi64 "li" /* int64_t */
#define SCNiLEAST8 "hhi" /* int_least8_t */
#define SCNiLEAST16 "hi" /* int_least16_t */
#define SCNiLEAST32 "i" /* int_least32_t */
#define SCNiLEAST64 "li" /* int_least64_t */
#define SCNiFAST8 "i" /* int_fast8_t */
#define SCNiFAST16 "i" /* int_fast16_t */
#define SCNiFAST32 "i" /* int_fast32_t */
#define SCNiFAST64 "li" /* int_fast64_t */
#define SCNiMAX "ji" /* intmax_t */
#define SCNiPTR "li" /* intptr_t */
/* fscanf(3) macros for unsigned integers. */
#define SCNo8 "hho" /* uint8_t */
#define SCNo16 "ho" /* uint16_t */
#define SCNo32 "o" /* uint32_t */
#define SCNo64 "lo" /* uint64_t */
#define SCNoLEAST8 "hho" /* uint_least8_t */
#define SCNoLEAST16 "ho" /* uint_least16_t */
#define SCNoLEAST32 "o" /* uint_least32_t */
#define SCNoLEAST64 "lo" /* uint_least64_t */
#define SCNoFAST8 "o" /* uint_fast8_t */
#define SCNoFAST16 "o" /* uint_fast16_t */
#define SCNoFAST32 "o" /* uint_fast32_t */
#define SCNoFAST64 "lo" /* uint_fast64_t */
#define SCNoMAX "jo" /* uintmax_t */
#define SCNoPTR "lo" /* uintptr_t */
#define SCNu8 "hhu" /* uint8_t */
#define SCNu16 "hu" /* uint16_t */
#define SCNu32 "u" /* uint32_t */
#define SCNu64 "lu" /* uint64_t */
#define SCNuLEAST8 "hhu" /* uint_least8_t */
#define SCNuLEAST16 "hu" /* uint_least16_t */
#define SCNuLEAST32 "u" /* uint_least32_t */
#define SCNuLEAST64 "lu" /* uint_least64_t */
#define SCNuFAST8 "u" /* uint_fast8_t */
#define SCNuFAST16 "u" /* uint_fast16_t */
#define SCNuFAST32 "u" /* uint_fast32_t */
#define SCNuFAST64 "lu" /* uint_fast64_t */
#define SCNuMAX "ju" /* uintmax_t */
#define SCNuPTR "lu" /* uintptr_t */
#define SCNx8 "hhx" /* uint8_t */
#define SCNx16 "hx" /* uint16_t */
#define SCNx32 "x" /* uint32_t */
#define SCNx64 "lx" /* uint64_t */
#define SCNxLEAST8 "hhx" /* uint_least8_t */
#define SCNxLEAST16 "hx" /* uint_least16_t */
#define SCNxLEAST32 "x" /* uint_least32_t */
#define SCNxLEAST64 "lx" /* uint_least64_t */
#define SCNxFAST8 "x" /* uint_fast8_t */
#define SCNxFAST16 "x" /* uint_fast16_t */
#define SCNxFAST32 "x" /* uint_fast32_t */
#define SCNxFAST64 "lx" /* uint_fast64_t */
#define SCNxMAX "jx" /* uintmax_t */
#define SCNxPTR "lx" /* uintptr_t */
#endif /* !_MACHINE_INTTYPES_H_ */

96
sys/alpha/include/_limits.h
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@ -1,96 +0,0 @@
/*-
* Copyright (c) 1988, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
* From: NetBSD: limits.h,v 1.3 1997/04/06 08:47:31 cgd Exp
* $FreeBSD$
*/
#ifndef _MACHINE__LIMITS_H_
#define _MACHINE__LIMITS_H_
/*
* According to ANSI (section 2.2.4.2), the values below must be usable by
* #if preprocessing directives. Additionally, the expression must have the
* same type as would an expression that is an object of the corresponding
* type converted according to the integral promotions. The subtraction for
* INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an
* unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).
* These numbers are for the default configuration of gcc. They work for
* some other compilers as well, but this should not be depended on.
*/
#define __CHAR_BIT 8 /* number of bits in a char */
#define __SCHAR_MAX 0x7f /* max value for a signed char */
#define __SCHAR_MIN (-0x7f-1) /* min value for a signed char */
#define __UCHAR_MAX 0xffU /* max value for an unsigned char */
#define __CHAR_MAX 0x7f /* max value for a char */
#define __CHAR_MIN (-0x7f-1) /* min value for a char */
#define __USHRT_MAX 0xffffU /* max value for an unsigned short */
#define __SHRT_MAX 0x7fff /* max value for a short */
#define __SHRT_MIN (-0x7fff-1) /* min value for a short */
#define __UINT_MAX 0xffffffffU /* max value for an unsigned int */
#define __INT_MAX 0x7fffffff /* max value for an int */
#define __INT_MIN (-0x7fffffff-1) /* min value for an int */
#define __ULONG_MAX 0xffffffffffffffffUL /* max for an unsigned long */
#define __LONG_MAX 0x7fffffffffffffffL /* max for a long */
#define __LONG_MIN (-0x7fffffffffffffffL-1) /* min for a long */
/* Long longs and longs are the same size on the alpha. */
/* max for an unsigned long long */
#define __ULLONG_MAX 0xffffffffffffffffULL
#define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */
#define __LLONG_MIN (-0x7fffffffffffffffLL-1) /* min for a long long */
#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */
#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */
#define __OFF_MAX __LONG_MAX /* max value for a off_t */
#define __OFF_MIN __LONG_MIN /* min value for a off_t */
/* Quads and longs are the same on the alpha. Ensure they stay in sync. */
#define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */
#define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */
#define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */
#define __LONG_BIT 64
#define __WORD_BIT 32
/*
* Minimum signal stack size. The current signal frame
* for Alpha is 808 bytes large.
*/
#define __MINSIGSTKSZ (1024 * 4)
#endif /* !_MACHINE__LIMITS_H_ */

171
sys/alpha/include/_stdint.h
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@ -1,171 +0,0 @@
/*-
* Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## L)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## UL)
#define INTMAX_C(c) (c ## L)
#define UINTMAX_C(c) (c ## UL)
#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
/*
* ISO/IEC 9899:1999
* 7.18.2.1 Limits of exact-width integer types
*/
/* Minimum values of exact-width signed integer types. */
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffUL
/*
* ISO/IEC 9899:1999
* 7.18.2.2 Limits of minimum-width integer types
*/
/* Minimum values of minimum-width signed integer types. */
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
/* Maximum values of minimum-width signed integer types. */
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
/* Maximum values of minimum-width unsigned integer types. */
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.3 Limits of fastest minimum-width integer types
*/
/* Minimum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MIN INT32_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
/* Maximum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MAX INT32_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
/* Maximum values of fastest minimum-width unsigned integer types. */
#define UINT_FAST8_MAX UINT32_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.4 Limits of integer types capable of holding object pointers
*/
#define INTPTR_MIN INT64_MIN
#define INTPTR_MAX INT64_MAX
#define UINTPTR_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.5 Limits of greatest-width integer types
*/
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.3 Limits of other integer types
*/
/* Limits of ptrdiff_t. */
#define PTRDIFF_MIN INT64_MIN
#define PTRDIFF_MAX INT64_MAX
/* Limits of sig_atomic_t. */
#define SIG_ATOMIC_MIN INT32_MIN
#define SIG_ATOMIC_MAX INT32_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT64_MAX
#ifndef WCHAR_MIN /* Also possibly defined in <wchar.h> */
/* Limits of wchar_t. */
#define WCHAR_MIN INT32_MIN
#define WCHAR_MAX INT32_MAX
#endif
/* Limits of wint_t. */
#define WINT_MIN INT32_MIN
#define WINT_MAX INT32_MAX
#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
#endif /* !_MACHINE__STDINT_H_ */

119
sys/alpha/include/_types.h
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@ -1,119 +0,0 @@
/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
* $FreeBSD$
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#ifndef _SYS_CDEFS_H_
#error this file needs sys/cdefs.h as a prerequisite
#endif
/*
* Basic types upon which most other types are built.
*/
typedef __signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
typedef long __int64_t;
typedef unsigned long __uint64_t;
/*
* Standard type definitions.
*/
typedef __int32_t __clock_t; /* clock()... */
typedef unsigned int __cpumask_t;
typedef __int64_t __critical_t;
typedef double __double_t;
typedef float __float_t;
typedef __int64_t __intfptr_t;
typedef __int64_t __intmax_t;
typedef __int64_t __intptr_t;
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __int8_t __int_least8_t;
typedef __int16_t __int_least16_t;
typedef __int32_t __int_least32_t;
typedef __int64_t __int_least64_t;
typedef __int64_t __ptrdiff_t; /* ptr1 - ptr2 */
typedef __int64_t __register_t;
typedef __int64_t __segsz_t; /* segment size (in pages) */
typedef __uint64_t __size_t; /* sizeof() */
typedef __int64_t __ssize_t; /* byte count or error */
typedef __int32_t __time_t; /* time()... */
typedef __uint64_t __uintfptr_t;
typedef __uint64_t __uintmax_t;
typedef __uint64_t __uintptr_t;
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint8_t __uint_least8_t;
typedef __uint16_t __uint_least16_t;
typedef __uint32_t __uint_least32_t;
typedef __uint64_t __uint_least64_t;
typedef __uint64_t __u_register_t;
typedef __uint64_t __vm_offset_t;
typedef __int64_t __vm_ooffset_t;
typedef __uint64_t __vm_paddr_t;
typedef __uint64_t __vm_pindex_t;
typedef __uint64_t __vm_size_t;
/*
* Unusual type definitions.
*/
#ifdef __GNUCLIKE_BUILTIN_VAALIST
typedef __builtin_va_list __va_list; /* internally known to gcc */
#else
typedef struct {
char *__base;
int __offset;
int __pad;
} __va_list;
#endif /* __GNUCLIKE_BUILTIN_VAALIST */
#if defined(__GNUC_VA_LIST_COMPATIBILITY) && !defined(__GNUC_VA_LIST) \
&& !defined(__NO_GNUC_VA_LIST)
#define __GNUC_VA_LIST
typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/
#endif
#endif /* !_MACHINE__TYPES_H_ */

582
sys/alpha/include/alpha_cpu.h
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@ -1,582 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: alpha_cpu.h,v 1.15 1997/09/20 19:02:34 mjacob Exp */
/*-
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#ifndef __ALPHA_ALPHA_CPU_H__
#define __ALPHA_ALPHA_CPU_H__
/*
* Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
*
* Definitions for:
*
* Process Control Block
* Interrupt/Exception/Syscall Stack Frame
* Processor Status Register
* Machine Check Error Summary Register
* Machine Check Logout Area
* Virtual Memory Management
* Kernel Entry Vectors
* MMCSR Fault Type Codes
* Translation Buffer Invalidation
*
* and miscellaneous PALcode operations.
*/
/*
* Process Control Block definitions [OSF/1 PALcode Specific]
*/
struct alpha_pcb {
unsigned long apcb_ksp; /* kernel stack ptr */
unsigned long apcb_usp; /* user stack ptr */
unsigned long apcb_ptbr; /* page table base reg */
unsigned int apcb_cpc; /* charged process cycles */
unsigned int apcb_asn; /* address space number */
unsigned long apcb_unique; /* process unique value */
unsigned long apcb_flags; /* flags; see below */
unsigned long apcb_decrsv0; /* DEC reserved */
unsigned long apcb_decrsv1; /* DEC reserved */
};
#define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
#define ALPHA_PCB_FLAGS_PME 0x4000000000000000
/*
* Interrupt/Exception/Syscall "Hardware" (really PALcode)
* Stack Frame definitions
*
* These are quadword offsets from the sp on kernel entry, i.e.
* to get to the value in question you access (sp + (offset * 8)).
*
* On syscall entry, A0-A2 aren't written to memory but space
* _is_ reserved for them.
*/
#define ALPHA_HWFRAME_PS 0 /* processor status register */
#define ALPHA_HWFRAME_PC 1 /* program counter */
#define ALPHA_HWFRAME_GP 2 /* global pointer */
#define ALPHA_HWFRAME_A0 3 /* a0 */
#define ALPHA_HWFRAME_A1 4 /* a1 */
#define ALPHA_HWFRAME_A2 5 /* a2 */
#define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */
/*
* Processor Status Register [OSF/1 PALcode Specific]
*
* Includes user/kernel mode bit, interrupt priority levels, etc.
*/
#define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
#define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
#define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
#define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
#define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
#define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
#define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
#define ALPHA_PSL_IPL_MCES 0x0007 /* all interrupts disabled */
#define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
/* Convenience constants: what must be set/clear in user mode */
#define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
#define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
/*
* Interrupt Type Code Definitions [OSF/1 PALcode Specific]
*/
#define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */
#define ALPHA_INTR_CLOCK 1 /* clock interrupt */
#define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */
#define ALPHA_INTR_DEVICE 3 /* device interrupt */
#define ALPHA_INTR_PERF 4 /* performance counter */
#define ALPHA_INTR_PASSIVE 5 /* passive release */
/*
* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
*
* The following bits are values as read. On write, _PCE, _SCE, and
* _MIP are "write 1 to clear."
*/
#define ALPHA_MCES_IMP \
0xffffffff00000000 /* impl. dependent */
#define ALPHA_MCES_RSVD \
0x00000000ffffffe0 /* reserved */
#define ALPHA_MCES_DSC \
0x0000000000000010 /* disable system correctable error reporting */
#define ALPHA_MCES_DPC \
0x0000000000000008 /* disable processor correctable error reporting */
#define ALPHA_MCES_PCE \
0x0000000000000004 /* processor correctable error in progress */
#define ALPHA_MCES_SCE \
0x0000000000000002 /* system correctable error in progress */
#define ALPHA_MCES_MIP \
0x0000000000000001 /* machine check in progress */
/*
* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
*/
struct alpha_logout_area {
unsigned int la_frame_size; /* frame size */
unsigned int la_flags; /* flags; see below */
unsigned int la_cpu_offset; /* offset to cpu area */
unsigned int la_system_offset; /* offset to system area */
};
#define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */
#define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */
#define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */
#define ALPHA_LOGOUT_NOT_BUILT \
(struct alpha_logout_area *)0xffffffffffffffff)
#define ALPHA_LOGOUT_PAL_AREA(lap) \
(unsigned long *)((unsigned char *)(lap) + 16)
#define ALPHA_LOGOUT_PAL_SIZE(lap) \
((lap)->la_cpu_offset - 16)
#define ALPHA_LOGOUT_CPU_AREA(lap) \
(unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
#define ALPHA_LOGOUT_CPU_SIZE(lap) \
((lap)->la_system_offset - (lap)->la_cpu_offset)
#define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
(unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
#define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
((lap)->la_frame_size - (lap)->la_system_offset)
/*
* Virtual Memory Management definitions [OSF/1 PALcode Specific]
*
* Includes user and kernel space addresses and information,
* page table entry definitions, etc.
*
* NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
*/
#define ALPHA_PGSHIFT 13 /* bits that index within page */
#define ALPHA_PTSHIFT 10 /* bits that index within page tables */
#define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
#define ALPHA_L3SHIFT ALPHA_PGSHIFT
#define ALPHA_L2SHIFT (ALPHA_L3SHIFT+ALPHA_PTSHIFT)
#define ALPHA_L1SHIFT (ALPHA_L2SHIFT+ALPHA_PTSHIFT)
#define ALPHA_USEG_BASE 0 /* virtual */
#define ALPHA_USEG_END 0x000003ffffffffffLL
#define ALPHA_K0SEG_BASE 0xfffffc0000000000LL /* direct-mapped */
#define ALPHA_K0SEG_END 0xfffffdffffffffffLL
#define ALPHA_K1SEG_BASE 0xfffffe0000000000LL /* virtual */
#define ALPHA_K1SEG_END 0xffffffffffffffffLL
#define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
#define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
#define ALPHA_PTE_VALID 0x0001
#define ALPHA_PTE_FAULT_ON_READ 0x0002
#define ALPHA_PTE_FAULT_ON_WRITE 0x0004
#define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008
#define ALPHA_PTE_ASM 0x0010 /* addr. space match */
#define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */
#define ALPHA_PTE_PROT 0xff00
#define ALPHA_PTE_KR 0x0100
#define ALPHA_PTE_UR 0x0200
#define ALPHA_PTE_KW 0x1000
#define ALPHA_PTE_UW 0x2000
#define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
#define ALPHA_PTE_SOFTWARE 0xffff0000
#define ALPHA_PTE_PFN 0xffffffff00000000
#define ALPHA_PTE_TO_PFN(pte) ((u_long)(pte) >> 32)
#define ALPHA_PTE_FROM_PFN(pfn) ((u_long)(pfn) << 32)
typedef unsigned long alpha_pt_entry_t;
/*
* Kernel Entry Vectors. [OSF/1 PALcode Specific]
*/
#define ALPHA_KENTRY_INT 0
#define ALPHA_KENTRY_ARITH 1
#define ALPHA_KENTRY_MM 2
#define ALPHA_KENTRY_IF 3
#define ALPHA_KENTRY_UNA 4
#define ALPHA_KENTRY_SYS 5
/*
* MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
*/
#define ALPHA_MMCSR_INVALTRANS 0
#define ALPHA_MMCSR_ACCESS 1
#define ALPHA_MMCSR_FOR 2
#define ALPHA_MMCSR_FOE 3
#define ALPHA_MMCSR_FOW 4
/*
* Instruction Fault Type Codes. [OSF/1 PALcode Specific]
*/
#define ALPHA_IF_CODE_BPT 0
#define ALPHA_IF_CODE_BUGCHK 1
#define ALPHA_IF_CODE_GENTRAP 2
#define ALPHA_IF_CODE_FEN 3
#define ALPHA_IF_CODE_OPDEC 4
/*
* Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
*/
#define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */
#define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */
#define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */
#define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */
#define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */
/*
* Bits used in the amask instruction [EV56 and later]
*/
#define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */
#define ALPHA_AMASK_FIX 0x0002 /* sqrt and f <-> i conversion extension */
#define ALPHA_AMASK_CIX 0x0004 /* count extension */
#define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */
#define ALPHA_AMASK_PRECISE 0x0200 /* Precise arithmetic traps */
/*
* Chip family IDs returned by implver instruction
*/
#define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */
#define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */
#define ALPHA_IMPLVER_EV6 2 /* EV6 */
/*
* Inlines for Alpha instructions normally inaccessible from C.
*/
static __inline u_int64_t
alpha_amask(u_int64_t mask)
{
u_int64_t result;
__asm__ __volatile__ (
"amask %1,%0"
: "=r" (result)
: "r" (mask));
return result;
}
static __inline unsigned long
alpha_implver(void)
{
u_int64_t result;
__asm__ __volatile__ (
"implver %0"
: "=r" (result));
return result;
}
static __inline unsigned long
alpha_rpcc(void)
{
u_int64_t result;
__asm__ __volatile__ (
"rpcc %0"
: "=r" (result));
return result;
}
static __inline void
alpha_mb(void)
{
__asm__ __volatile__ ("mb");
}
static __inline void
alpha_wmb(void)
{
/*
* XXX dfr: NetBSD originally had mb instead of wmb for
* alpha_wmb(). I'm not sure why so I'm leaving it alone. I
* think it should be safe to use wmb though.
*/
__asm__ __volatile__ ("mb");
}
/*
* Inlines for OSF/1 PALcode operations.
*/
static __inline void
alpha_pal_halt(void)
{
__asm__ __volatile__ ("call_pal 0x0 #PAL_halt");
}
static __inline void
alpha_pal_cflush(u_int64_t pfn)
{
register u_int64_t a0 __asm__("$16") = pfn;
__asm__ __volatile__ (
"call_pal 0x1 #PAL_cflush"
:
: "r" (a0));
}
static __inline void
alpha_pal_draina(void)
{
__asm__ __volatile__ ("call_pal 0x2 #PAL_draina" : : : "memory");
}
static __inline void
alpha_pal_wripir(u_int64_t ipir)
{
register u_int64_t a0 __asm__("$16") = ipir;
__asm__ __volatile__ (
"call_pal 0xd #PAL_ipir"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_rdmces(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x10 #PAL_OSF1_rdmces"
: "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline void
alpha_pal_wrmces(u_int64_t mces)
{
register u_int64_t a0 __asm__("$16") = mces;
__asm__ __volatile__ (
"call_pal 0x11 #PAL_wrmces"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline void
alpha_pal_wrfen(u_int64_t fen)
{
register u_int64_t a0 __asm__("$16") = fen;
__asm__ __volatile__ (
"call_pal 0x2b #PAL_wrfen"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline void
alpha_pal_wrvptptr(u_int64_t vptptr)
{
register u_int64_t a0 __asm__("$16") = vptptr;
__asm__ __volatile__ (
"call_pal 0x2d #PAL_wrvptptr"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_swpctx(u_int64_t pcb)
{
register u_int64_t a0 __asm__("$16") = pcb;
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x30 #PAL_OSF1_swpctx"
: "=r" (v0), "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25", "memory");
return v0;
}
static __inline void
alpha_pal_wrval(u_int64_t sysvalue)
{
register u_int64_t a0 __asm__("$16") = sysvalue;
__asm__ __volatile__ (
"call_pal 0x31 #PAL_wrval"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_rdval(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x32 #PAL_OSF1_rdval"
: "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline void
alpha_pal_wrunique(u_int64_t tp)
{
register u_int64_t a0 __asm__("$16") = tp;
__asm__ __volatile__("call_pal 0x9f # PAL_wrunique"
: "+r" (a0) : : "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_rdunique(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__("call_pal 0x9e # PAL_rdunique"
: "=r" (v0) : : "$1", "$22", "$23", "$24", "$25");
return (v0);
}
static __inline void
alpha_pal_tbi(u_int64_t op, u_int64_t va)
{
register u_int64_t a0 __asm__("$16") = op;
register u_int64_t a1 __asm__("$17") = va;
__asm__ __volatile__ (
"call_pal 0x33 #PAL_OSF1_tbi"
: "+r" (a0), "+r" (a1)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline void
alpha_pal_wrent(void *ent, u_int64_t which)
{
register u_int64_t a0 __asm__("$16") = (u_int64_t) ent;
register u_int64_t a1 __asm__("$17") = which;
__asm__ __volatile__ (
"call_pal 0x34 #PAL_OSF1_wrent"
: "+r" (a0), "+r" (a1)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_swpipl(u_int64_t newipl)
{
register u_int64_t a0 __asm__("$16") = newipl;
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x35 #PAL_OSF1_swpipl"
: "=r" (v0), "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline u_int64_t
alpha_pal_rdps(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x36 #PAL_OSF1_rdps"
: "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline void
alpha_pal_wrusp(u_int64_t usp)
{
register u_int64_t a0 __asm__("$16") = usp;
__asm__ __volatile__ (
"call_pal 0x38 #PAL_wrusp"
: "+r" (a0)
:
: "$1", "$22", "$23", "$24", "$25");
}
static __inline u_int64_t
alpha_pal_wrperfmon(u_int64_t arg0, u_int64_t arg1)
{
register u_int64_t v0 __asm__("$0");
register u_int64_t a0 __asm__("$16") = arg0;
register u_int64_t a1 __asm__("$17") = arg1;
__asm__ __volatile__ (
"call_pal 0x39 #PAL_OSF1_wrperfmon"
: "+r" (a0), "+r" (a1), "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline u_int64_t
alpha_pal_rdusp(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x3a #PAL_OSF1_rdusp"
: "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline u_int64_t
alpha_pal_whami(void)
{
register u_int64_t v0 __asm__("$0");
__asm__ __volatile__ (
"call_pal 0x3c #PAL_OSF1_whami"
: "=r" (v0)
:
: "$1", "$22", "$23", "$24", "$25");
return v0;
}
static __inline void
alpha_pal_imb(void)
{
__asm__ __volatile__ ("call_pal 0x86 #PAL_imb");
}
#endif /* __ALPHA_ALPHA_CPU_H__ */

649
sys/alpha/include/asm.h
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@ -1,649 +0,0 @@
/*-
* Copyright (c) 1991,1990,1989,1994,1995,1996 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
* From: NetBSD: asm.h,v 1.18 1997/11/03 04:22:06 ross Exp
* $FreeBSD$
*/
#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_
/*
* Assembly coding style
*
* This file contains macros and register defines to
* aid in writing more readable assembly code.
* Some rules to make assembly code understandable by
* a debugger are also noted.
*
* The document
*
* "ALPHA Calling Standard", DEC 27-Apr-90
*
* defines (a superset of) the rules and conventions
* we use. While we make no promise of adhering to
* such standard and its evolution (esp where we
* can get faster code paths) it is certainly intended
* that we be interoperable with such standard.
*
* In this sense, this file is a proper part of the
* definition of the (software) Alpha architecture.
*/
/*
* Symbolic register names and register saving rules
*
* Legend:
* T Saved by caller (Temporaries)
* S Saved by callee (call-Safe registers)
*/
#define v0 $0 /* (T) return value */
#define t0 $1 /* (T) temporary registers */
#define t1 $2
#define t2 $3
#define t3 $4
#define t4 $5
#define t5 $6
#define t6 $7
#define t7 $8
#define s0 $9 /* (S) call-safe registers */
#define s1 $10
#define s2 $11
#define s3 $12
#define s4 $13
#define s5 $14
#define s6 $15
#define a0 $16 /* (T) argument registers */
#define a1 $17
#define a2 $18
#define a3 $19
#define a4 $20
#define a5 $21
#define t8 $22 /* (T) temporary registers */
#define t9 $23
#define t10 $24
#define t11 $25
#define ra $26 /* (T) return address */
#define t12 $27 /* (T) another temporary */
#define at_reg $28 /* (T) assembler scratch */
#define gp $29 /* (T) (local) data pointer */
#define sp $30 /* (S) stack pointer */
#define zero $31 /* wired zero */
/* In the kernel, we use t7 to point at the per-cpu globals. */
#ifdef _KERNEL
#define pcpup $8
#endif
/* Floating point registers (XXXX VERIFY THIS) */
#define fv0 $f0 /* (T) return value (real) */
#define fv1 $f1 /* (T) return value (imaginary)*/
#define ft0 fv1
#define fs0 $f2 /* (S) call-safe registers */
#define fs1 $f3
#define fs2 $f4
#define fs3 $f5
#define fs4 $f6
#define fs5 $f7
#define fs6 $f8
#define fs7 $f9
#define ft1 $f10 /* (T) temporary registers */
#define ft2 $f11
#define ft3 $f12
#define ft4 $f13
#define ft5 $f14
#define ft6 $f15
#define fa0 $f16 /* (T) argument registers */
#define fa1 $f17
#define fa2 $f18
#define fa3 $f19
#define fa4 $f20
#define fa5 $f21
#define ft7 $f22 /* (T) more temporaries */
#define ft8 $f23
#define ft9 $f24
#define ft10 $f25
#define ft11 $f26
#define ft12 $f27
#define ft13 $f28
#define ft14 $f29
#define ft15 $f30
#define fzero $f31 /* wired zero */
/* Other DEC standard names */
#define ai $25 /* (T) argument information */
#define pv $27 /* (T) procedure value */
/*
* Useful stuff.
*/
#ifdef __STDC__
#define __CONCAT(a,b) a ## b
#else
#define __CONCAT(a,b) a/**/b
#endif
#define ___CONCAT(a,b) __CONCAT(a,b)
/*
* Macro to make a local label name.
*/
#define LLABEL(name,num) ___CONCAT(___CONCAT(L,name),num)
/*
*
* Debuggers need symbol table information to be able to properly
* decode a stack trace. The minimum that should be provided is:
*
* name:
* .proc name,numargs
*
* where "name" is the function's name;
* "numargs" how many arguments it expects. For varargs
* procedures this should be a negative number,
* indicating the minimum required number of
* arguments (which is at least 1);
*
* NESTED functions (functions that call other functions) should define
* how they handle their stack frame in a .frame directive:
*
* .frame framesize, pc_reg, i_mask, f_mask
*
* where "framesize" is the size of the frame for this function, in bytes.
* That is:
* new_sp + framesize == old_sp
* Framesizes should be rounded to a cacheline size.
* Note that old_sp plays the role of a conventional
* "frame pointer";
* "pc_reg" is either a register which preserves the caller's PC
* or 'std', if std the saved PC should be stored at
* old_sp-8
* "i_mask" is a bitmask that indicates which of the integer
* registers are saved. See the M_xx defines at the
* end for the encoding of this 32bit value.
* "f_mask" is the same, for floating point registers.
*
* Note, 10/31/97: This is interesting but it isn't the way gcc outputs
* frame directives and it isn't the way the macros below output them
* either. Frame directives look like this:
*
* .frame $15,framesize,$26,0
*
* If no fp is set up then $30 should be used instead of $15.
* Also, gdb expects to find a <lda sp,-framesize(sp)> at the beginning
* of a procedure. Don't use things like sub sp,framesize,sp for this
* reason. End Note 10/31/97. ross@netbsd.org
*
* Note that registers should be saved starting at "old_sp-8", where the
* return address should be stored. Other registers follow at -16-24-32..
* starting from register 0 (if saved) and up. Then float registers (ifany)
* are saved.
*
* If you need to alias a leaf function, or to provide multiple entry points
* use the LEAF() macro for the main entry point and XLEAF() for the other
* additional/alternate entry points.
* "XLEAF"s must be nested within a "LEAF" and a ".end".
* Similar rules for nested routines, e.g. use NESTED/XNESTED
* Symbols that should not be exported can be declared with the STATIC_xxx
* macros.
*
* All functions must be terminated by the END macro
*
* It is conceivable, although currently at the limits of compiler
* technology, that while performing inter-procedural optimizations
* the compiler/linker be able to avoid unnecessary register spills
* if told about the register usage of LEAF procedures (and by transitive
* closure of NESTED procedures as well). Assembly code can help
* this process using the .reguse directive:
*
* .reguse i_mask, f_mask
*
* where the register masks are built as above or-ing M_xx defines.
*
*
* All symbols are internal unless EXPORTed. Symbols that are IMPORTed
* must be appropriately described to the debugger.
*
*/
/*
* for `.loc' uses
*/
.file 1 __FILE__
/*
* MCOUNT
*/
#if !defined(GPROF) && !defined(PROF)
#define MCOUNT /* nothing */
#else
#define MCOUNT \
.set noat; \
jsr at_reg,_mcount; \
.set at
#endif
/*
* PALVECT, ESETUP, and ERSAVE
* Declare a palcode transfer point, and carefully construct
* gdb symbols with an unusual _negative_ register-save offset
* so that gdb can find the otherwise lost PC and then
* invert the vector for traceback. Also, fix up framesize,
* allowing for the palframe for the same reason.
*/
#define PALVECT(_name_) \
ESETUP(_name_); \
ERSAVE(); \
br pv, 1001f; \
1001:; \
LDGP(pv)
#define ESETUP(_name_) \
.loc 1 __LINE__; \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.set noat; \
lda sp,-(FRAME_SW_SIZE*8)(sp); \
.frame $30,(FRAME_SW_SIZE+6)*8,$26,0; /* give gdb the real size */\
.mask 0x4000000,-0x28; \
.set at
#define ERSAVE() \
.set noat; \
stq at_reg,(FRAME_AT*8)(sp); \
.set at; \
stq ra,(FRAME_RA*8)(sp); \
.loc 1 __LINE__; \
bsr ra,exception_save_regs /* jmp/CALL trashes pv/t12 */
/*
* LEAF
* Declare a global leaf function.
* A leaf function does not call other functions AND does not
* use any register that is callee-saved AND does not modify
* the stack pointer.
*/
#define LEAF(_name_,_n_args_) \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.frame sp,0,ra; \
MCOUNT
/* should have been
.proc _name_,_n_args_; \
.frame 0,ra,0,0
*/
#define LEAF_NOPROFILE(_name_,_n_args_) \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.frame sp,0,ra
/* should have been
.proc _name_,_n_args_; \
.frame 0,ra,0,0
*/
/*
* STATIC_LEAF
* Declare a local leaf function.
*/
#define STATIC_LEAF(_name_,_n_args_) \
.ent _name_ 0; \
_name_:; \
.frame sp,0,ra; \
MCOUNT
/* should have been
.proc _name_,_n_args_; \
.frame 0,ra,0,0
*/
/*
* XLEAF
* Global alias for a leaf function, or alternate entry point
*/
#define XLEAF(_name_,_n_args_) \
.globl _name_; \
.aent _name_ 0; \
_name_:
/* should have been
.aproc _name_,_n_args_;
*/
/*
* STATIC_XLEAF
* Local alias for a leaf function, or alternate entry point
*/
#define STATIC_XLEAF(_name_,_n_args_) \
.aent _name_ 0; \
_name_:
/* should have been
.aproc _name_,_n_args_;
*/
/*
* NESTED
* Declare a (global) nested function
* A nested function calls other functions and needs
* therefore stack space to save/restore registers.
*/
#define NESTED(_name_, _n_args_, _framesize_, _pc_reg_, _i_mask_, _f_mask_ ) \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.frame sp,_framesize_,_pc_reg_; \
.livereg _i_mask_,_f_mask_; \
MCOUNT
/* should have been
.proc _name_,_n_args_; \
.frame _framesize_, _pc_reg_, _i_mask_, _f_mask_
*/
#define NESTED_NOPROFILE(_name_, _n_args_, _framesize_, _pc_reg_, _i_mask_, _f_mask_ ) \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.frame sp,_framesize_,_pc_reg_; \
.livereg _i_mask_,_f_mask_
/* should have been
.proc _name_,_n_args_; \
.frame _framesize_, _pc_reg_, _i_mask_, _f_mask_
*/
/*
* STATIC_NESTED
* Declare a local nested function.
*/
#define STATIC_NESTED(_name_, _n_args_, _framesize_, _pc_reg_, _i_mask_, _f_mask_ ) \
.ent _name_ 0; \
_name_:; \
.frame sp,_framesize_,_pc_reg_; \
.livereg _i_mask_,_f_mask_; \
MCOUNT
/* should have been
.proc _name_,_n_args_; \
.frame _framesize_, _pc_reg_, _i_mask_, _f_mask_
*/
/*
* XNESTED
* Same as XLEAF, for a nested function.
*/
#define XNESTED(_name_,_n_args_) \
.globl _name_; \
.aent _name_ 0; \
_name_:
/* should have been
.aproc _name_,_n_args_;
*/
/*
* STATIC_XNESTED
* Same as STATIC_XLEAF, for a nested function.
*/
#define STATIC_XNESTED(_name_,_n_args_) \
.aent _name_ 0; \
_name_:
/* should have been
.aproc _name_,_n_args_;
*/
/*
* END
* Function delimiter
*/
#define END(_name_) \
.end _name_
/*
* CALL
* Function invocation
*/
#define CALL(_name_) \
.loc 1 __LINE__; \
jsr ra,_name_; \
ldgp gp,0(ra)
/* but this would cover longer jumps
br ra,.+4; \
bsr ra,_name_
*/
/*
* RET
* Return from function
*/
#define RET \
ret zero,(ra),1
/*
* EXPORT
* Export a symbol
*/
#define EXPORT(_name_) \
.globl _name_; \
_name_:
/*
* IMPORT
* Make an external name visible, typecheck the size
*/
#define IMPORT(_name_, _size_) \
.extern _name_,_size_
/*
* ABS
* Define an absolute symbol
*/
#define ABS(_name_, _value_) \
.globl _name_; \
_name_ = _value_
/*
* BSS
* Allocate un-initialized space for a global symbol
*/
#define BSS(_name_,_numbytes_) \
.comm _name_,_numbytes_
/*
* VECTOR
* Make an exception entry point look like a called function,
* to make it digestible to the debugger (KERNEL only)
*/
#define VECTOR(_name_, _i_mask_) \
.globl _name_; \
.ent _name_ 0; \
_name_:; \
.mask _i_mask_|IM_EXC,0; \
.frame sp,MSS_SIZE,ra;
/* .livereg _i_mask_|IM_EXC,0 */
/* should have been
.proc _name_,1; \
.frame MSS_SIZE,$31,_i_mask_,0; \
*/
/*
* MSG
* Allocate space for a message (a read-only ascii string)
*/
#define ASCIZ .asciz
#define MSG(msg,reg,label) \
lda reg, label; \
.data; \
label: ASCIZ msg; \
.text;
/*
* PRINTF
* Print a message
*/
#define PRINTF(msg,label) \
MSG(msg,a0,label); \
CALL(printf)
/*
* PANIC
* Fatal error (KERNEL)
*/
#define PANIC(msg,label) \
MSG(msg,a0,label); \
CALL(panic)
/*
* Register mask defines, used to define both save
* and use register sets.
*
* NOTE: The bit order should HAVE BEEN maintained when saving
* registers on the stack: sp goes at the highest
* address, gp lower on the stack, etc etc
* BUT NOONE CARES ABOUT DEBUGGERS AT MIPS
*/
#define IM_EXC 0x80000000
#define IM_SP 0x40000000
#define IM_GP 0x20000000
#define IM_AT 0x10000000
#define IM_T12 0x08000000
# define IM_PV IM_T4
#define IM_RA 0x04000000
#define IM_T11 0x02000000
# define IM_AI IM_T3
#define IM_T10 0x01000000
#define IM_T9 0x00800000
#define IM_T8 0x00400000
#define IM_A5 0x00200000
#define IM_A4 0x00100000
#define IM_A3 0x00080000
#define IM_A2 0x00040000
#define IM_A1 0x00020000
#define IM_A0 0x00010000
#define IM_S6 0x00008000
#define IM_S5 0x00004000
#define IM_S4 0x00002000
#define IM_S3 0x00001000
#define IM_S2 0x00000800
#define IM_S1 0x00000400
#define IM_S0 0x00000200
#define IM_T7 0x00000100
#define IM_T6 0x00000080
#define IM_T5 0x00000040
#define IM_T4 0x00000020
#define IM_T3 0x00000010
#define IM_T2 0x00000008
#define IM_T1 0x00000004
#define IM_T0 0x00000002
#define IM_V0 0x00000001
#define FM_T15 0x40000000
#define FM_T14 0x20000000
#define FM_T13 0x10000000
#define FM_T12 0x08000000
#define FM_T11 0x04000000
#define FM_T10 0x02000000
#define FM_T9 0x01000000
#define FM_T8 0x00800000
#define FM_T7 0x00400000
#define FM_A5 0x00200000
#define FM_A4 0x00100000
#define FM_A3 0x00080000
#define FM_A2 0x00040000
#define FM_A1 0x00020000
#define FM_A0 0x00010000
#define FM_T6 0x00008000
#define FM_T5 0x00004000
#define FM_T4 0x00002000
#define FM_T3 0x00001000
#define FM_T2 0x00000800
#define FM_T1 0x00000400
#define FM_S7 0x00000200
#define FM_S6 0x00000100
#define FM_S5 0x00000080
#define FM_S4 0x00000040
#define FM_S3 0x00000020
#define FM_S2 0x00000010
#define FM_S1 0x00000008
#define FM_S0 0x00000004
#define FM_T0 0x00000002
#define FM_V1 FM_T0
#define FM_V0 0x00000001
/* Pull in PAL "function" codes. */
#include <machine/pal.h>
/*
* System call glue.
*/
#define SYSCALLNUM(name) \
___CONCAT(SYS_,name)
#define CALLSYS_NOERROR(name) \
ldiq v0, SYSCALLNUM(name); \
call_pal PAL_OSF1_callsys
/*
* Load the global pointer.
*/
#define LDGP(reg) \
ldgp gp, 0(reg)
/*
* WEAK_ALIAS: create a weak alias (ELF only).
*/
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
/*
* Kernel RCS ID tag and copyright macros
*/
#ifdef _KERNEL
#if !defined(lint) && !defined(NO_KERNEL_RCSIDS)
#define __KERNEL_RCSID(_n, _s) .ident _s
#else
#define __KERNEL_RCSID(_n, _s) /* nothing */
#endif
#endif /* _KERNEL */
#if !defined(lint) && !defined(STRIP_FBSDID)
#define __FBSDID(s) .ident s
#else
#define __FBSDID(s) /* nothing */
#endif /* not lint and not STRIP_FBSDID */
#endif /* !_MACHINE_ASM_H_ */

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sys/alpha/include/atomic.h
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/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_ATOMIC_H_
#define _MACHINE_ATOMIC_H_
#ifndef _SYS_CDEFS_H_
#error this file needs sys/cdefs.h as a prerequisite
#endif
#include <machine/alpha_cpu.h>
/*
* Various simple arithmetic on memory which is atomic in the presence
* of interrupts and SMP safe.
*/
void atomic_set_8(volatile u_int8_t *, u_int8_t);
void atomic_clear_8(volatile u_int8_t *, u_int8_t);
void atomic_add_8(volatile u_int8_t *, u_int8_t);
void atomic_subtract_8(volatile u_int8_t *, u_int8_t);
void atomic_set_16(volatile u_int16_t *, u_int16_t);
void atomic_clear_16(volatile u_int16_t *, u_int16_t);
void atomic_add_16(volatile u_int16_t *, u_int16_t);
void atomic_subtract_16(volatile u_int16_t *, u_int16_t);
static __inline void atomic_set_32(volatile u_int32_t *p, u_int32_t v)
{
u_int32_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %3\n\t" /* load old value */
"bis %0, %2, %0\n\t" /* calculate new value */
"stl_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_clear_32(volatile u_int32_t *p, u_int32_t v)
{
u_int32_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %3\n\t" /* load old value */
"bic %0, %2, %0\n\t" /* calculate new value */
"stl_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_add_32(volatile u_int32_t *p, u_int32_t v)
{
u_int32_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %3\n\t" /* load old value */
"addl %0, %2, %0\n\t" /* calculate new value */
"stl_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_subtract_32(volatile u_int32_t *p, u_int32_t v)
{
u_int32_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %3\n\t" /* load old value */
"subl %0, %2, %0\n\t" /* calculate new value */
"stl_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline u_int32_t atomic_readandclear_32(volatile u_int32_t *addr)
{
u_int32_t result,temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"wmb\n" /* ensure pending writes have drained */
"1:\tldl_l %0,%3\n\t" /* load current value, asserting lock */
"ldiq %1,0\n\t" /* value to store */
"stl_c %1,%2\n\t" /* attempt to store */
"beq %1,1b\n" /* if the store failed, spin */
: "=&r"(result), "=&r"(temp), "=m" (*addr)
: "m" (*addr)
: "memory");
#endif
return result;
}
static __inline void atomic_set_64(volatile u_int64_t *p, u_int64_t v)
{
u_int64_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldq_l %0, %3\n\t" /* load old value */
"bis %0, %2, %0\n\t" /* calculate new value */
"stq_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_clear_64(volatile u_int64_t *p, u_int64_t v)
{
u_int64_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldq_l %0, %3\n\t" /* load old value */
"bic %0, %2, %0\n\t" /* calculate new value */
"stq_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_add_64(volatile u_int64_t *p, u_int64_t v)
{
u_int64_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldq_l %0, %3\n\t" /* load old value */
"addq %0, %2, %0\n\t" /* calculate new value */
"stq_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline void atomic_subtract_64(volatile u_int64_t *p, u_int64_t v)
{
u_int64_t temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldq_l %0, %3\n\t" /* load old value */
"subq %0, %2, %0\n\t" /* calculate new value */
"stq_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n" /* spin if failed */
: "=&r" (temp), "=m" (*p)
: "r" (v), "m" (*p)
: "memory");
#endif
}
static __inline u_int64_t atomic_readandclear_64(volatile u_int64_t *addr)
{
u_int64_t result,temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"wmb\n" /* ensure pending writes have drained */
"1:\tldq_l %0,%3\n\t" /* load current value, asserting lock */
"ldiq %1,0\n\t" /* value to store */
"stq_c %1,%2\n\t" /* attempt to store */
"beq %1,1b\n" /* if the store failed, spin */
: "=&r"(result), "=&r"(temp), "=m" (*addr)
: "m" (*addr)
: "memory");
#endif
return result;
}
#define ATOMIC_ACQ_REL(NAME, WIDTH) \
static __inline void \
atomic_##NAME##_acq_##WIDTH(volatile u_int##WIDTH##_t *p, u_int##WIDTH##_t v)\
{ \
atomic_##NAME##_##WIDTH(p, v); \
alpha_mb(); \
} \
\
static __inline void \
atomic_##NAME##_rel_##WIDTH(volatile u_int##WIDTH##_t *p, u_int##WIDTH##_t v)\
{ \
alpha_mb(); \
atomic_##NAME##_##WIDTH(p, v); \
}
/* Variants of simple arithmetic with memory barriers. */
ATOMIC_ACQ_REL(set, 8)
ATOMIC_ACQ_REL(clear, 8)
ATOMIC_ACQ_REL(add, 8)
ATOMIC_ACQ_REL(subtract, 8)
ATOMIC_ACQ_REL(set, 16)
ATOMIC_ACQ_REL(clear, 16)
ATOMIC_ACQ_REL(add, 16)
ATOMIC_ACQ_REL(subtract, 16)
ATOMIC_ACQ_REL(set, 32)
ATOMIC_ACQ_REL(clear, 32)
ATOMIC_ACQ_REL(add, 32)
ATOMIC_ACQ_REL(subtract, 32)
ATOMIC_ACQ_REL(set, 64)
ATOMIC_ACQ_REL(clear, 64)
ATOMIC_ACQ_REL(add, 64)
ATOMIC_ACQ_REL(subtract, 64)
#undef ATOMIC_ACQ_REL
/*
* We assume that a = b will do atomic loads and stores.
*/
#define ATOMIC_STORE_LOAD(WIDTH) \
static __inline u_int##WIDTH##_t \
atomic_load_acq_##WIDTH(volatile u_int##WIDTH##_t *p) \
{ \
u_int##WIDTH##_t v; \
\
v = *p; \
alpha_mb(); \
return (v); \
} \
\
static __inline void \
atomic_store_rel_##WIDTH(volatile u_int##WIDTH##_t *p, u_int##WIDTH##_t v)\
{ \
alpha_mb(); \
*p = v; \
}
ATOMIC_STORE_LOAD(32)
ATOMIC_STORE_LOAD(64)
#undef ATOMIC_STORE_LOAD
/*
* Atomically compare the value stored at *p with cmpval and if the
* two values are equal, update the value of *p with newval. Returns
* zero if the compare failed, nonzero otherwise.
*/
static __inline u_int32_t
atomic_cmpset_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
{
u_int32_t ret;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %4\n\t" /* load old value */
"cmpeq %0, %2, %0\n\t" /* compare */
"beq %0, 2f\n\t" /* exit if not equal */
"mov %3, %0\n\t" /* value to store */
"stl_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n\t" /* if it failed, spin */
"2:\n"
: "=&r" (ret), "=m" (*p)
: "r" ((long)(int)cmpval), "r" (newval), "m" (*p)
: "memory");
#endif
return ret;
}
/*
* Atomically compare the value stored at *p with cmpval and if the
* two values are equal, update the value of *p with newval. Returns
* zero if the compare failed, nonzero otherwise.
*/
static __inline u_int64_t
atomic_cmpset_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
{
u_int64_t ret;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldq_l %0, %4\n\t" /* load old value */
"cmpeq %0, %2, %0\n\t" /* compare */
"beq %0, 2f\n\t" /* exit if not equal */
"mov %3, %0\n\t" /* value to store */
"stq_c %0, %1\n\t" /* attempt to store */
"beq %0, 1b\n\t" /* if it failed, spin */
"2:\n"
: "=&r" (ret), "=m" (*p)
: "r" (cmpval), "r" (newval), "m" (*p)
: "memory");
#endif
return ret;
}
static __inline u_int32_t
atomic_cmpset_acq_32(volatile u_int32_t *p, u_int32_t cmpval, u_int32_t newval)
{
int retval;
retval = atomic_cmpset_32(p, cmpval, newval);
alpha_mb();
return (retval);
}
static __inline u_int32_t
atomic_cmpset_rel_32(volatile u_int32_t *p, u_int32_t cmpval, u_int32_t newval)
{
alpha_mb();
return (atomic_cmpset_32(p, cmpval, newval));
}
static __inline u_int64_t
atomic_cmpset_acq_64(volatile u_int64_t *p, u_int64_t cmpval, u_int64_t newval)
{
int retval;
retval = atomic_cmpset_64(p, cmpval, newval);
alpha_mb();
return (retval);
}
static __inline u_int64_t
atomic_cmpset_rel_64(volatile u_int64_t *p, u_int64_t cmpval, u_int64_t newval)
{
alpha_mb();
return (atomic_cmpset_64(p, cmpval, newval));
}
/*
* Atomically add the value of v to the integer pointed to by p and return
* the previous value of *p.
*/
static __inline u_int
atomic_fetchadd_32(volatile u_int32_t *p, u_int32_t v)
{
u_int32_t value, temp;
#ifdef __GNUCLIKE_ASM
__asm __volatile (
"1:\tldl_l %0, %1\n\t" /* load old value */
"addl %0, %3, %2\n\t" /* calculate new value */
"stl_c %2, %1\n\t" /* attempt to store */
"beq %2, 1b\n" /* spin if failed */
: "=&r" (value), "=m" (*p), "=r" (temp)
: "r" (v), "m" (*p));
#endif
return (value);
}
/* Operations on chars. */
#define atomic_set_char atomic_set_8
#define atomic_set_acq_char atomic_set_acq_8
#define atomic_set_rel_char atomic_set_rel_8
#define atomic_clear_char atomic_clear_8
#define atomic_clear_acq_char atomic_clear_acq_8
#define atomic_clear_rel_char atomic_clear_rel_8
#define atomic_add_char atomic_add_8
#define atomic_add_acq_char atomic_add_acq_8
#define atomic_add_rel_char atomic_add_rel_8
#define atomic_subtract_char atomic_subtract_8
#define atomic_subtract_acq_char atomic_subtract_acq_8
#define atomic_subtract_rel_char atomic_subtract_rel_8
/* Operations on shorts. */
#define atomic_set_short atomic_set_16
#define atomic_set_acq_short atomic_set_acq_16
#define atomic_set_rel_short atomic_set_rel_16
#define atomic_clear_short atomic_clear_16
#define atomic_clear_acq_short atomic_clear_acq_16
#define atomic_clear_rel_short atomic_clear_rel_16
#define atomic_add_short atomic_add_16
#define atomic_add_acq_short atomic_add_acq_16
#define atomic_add_rel_short atomic_add_rel_16
#define atomic_subtract_short atomic_subtract_16
#define atomic_subtract_acq_short atomic_subtract_acq_16
#define atomic_subtract_rel_short atomic_subtract_rel_16
/* Operations on ints. */
#define atomic_set_int atomic_set_32
#define atomic_set_acq_int atomic_set_acq_32
#define atomic_set_rel_int atomic_set_rel_32
#define atomic_clear_int atomic_clear_32
#define atomic_clear_acq_int atomic_clear_acq_32
#define atomic_clear_rel_int atomic_clear_rel_32
#define atomic_add_int atomic_add_32
#define atomic_add_acq_int atomic_add_acq_32
#define atomic_add_rel_int atomic_add_rel_32
#define atomic_subtract_int atomic_subtract_32
#define atomic_subtract_acq_int atomic_subtract_acq_32
#define atomic_subtract_rel_int atomic_subtract_rel_32
#define atomic_cmpset_int atomic_cmpset_32
#define atomic_cmpset_acq_int atomic_cmpset_acq_32
#define atomic_cmpset_rel_int atomic_cmpset_rel_32
#define atomic_load_acq_int atomic_load_acq_32
#define atomic_store_rel_int atomic_store_rel_32
#define atomic_readandclear_int atomic_readandclear_32
#define atomic_fetchadd_int atomic_fetchadd_32
/* Operations on longs. */
#define atomic_set_long atomic_set_64
#define atomic_set_acq_long atomic_set_acq_64
#define atomic_set_rel_long atomic_set_rel_64
#define atomic_clear_long atomic_clear_64
#define atomic_clear_acq_long atomic_clear_acq_64
#define atomic_clear_rel_long atomic_clear_rel_64
#define atomic_add_long atomic_add_64
#define atomic_add_acq_long atomic_add_acq_64
#define atomic_add_rel_long atomic_add_rel_64
#define atomic_subtract_long atomic_subtract_64
#define atomic_subtract_acq_long atomic_subtract_acq_64
#define atomic_subtract_rel_long atomic_subtract_rel_64
#define atomic_cmpset_long atomic_cmpset_64
#define atomic_cmpset_acq_long atomic_cmpset_acq_64
#define atomic_cmpset_rel_long atomic_cmpset_rel_64
#define atomic_load_acq_long atomic_load_acq_64
#define atomic_store_rel_long atomic_store_rel_64
#define atomic_readandclear_long atomic_readandclear_64
/* Operations on pointers. */
#define atomic_set_ptr atomic_set_64
#define atomic_set_acq_ptr atomic_set_acq_64
#define atomic_set_rel_ptr atomic_set_rel_64
#define atomic_clear_ptr atomic_clear_64
#define atomic_clear_acq_ptr atomic_clear_acq_64
#define atomic_clear_rel_ptr atomic_clear_rel_64
#define atomic_add_ptr atomic_add_64
#define atomic_add_acq_ptr atomic_add_acq_64
#define atomic_add_rel_ptr atomic_add_rel_64
#define atomic_subtract_ptr atomic_subtract_64
#define atomic_subtract_acq_ptr atomic_subtract_acq_64
#define atomic_subtract_rel_ptr atomic_subtract_rel_64
#define atomic_cmpset_ptr atomic_cmpset_64
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_64
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_64
#define atomic_load_acq_ptr atomic_load_acq_64
#define atomic_store_rel_ptr atomic_store_rel_64
#define atomic_readandclear_ptr atomic_readandclear_64
#endif /* ! _MACHINE_ATOMIC_H_ */

86
sys/alpha/include/bootinfo.h
View File

@ -1,86 +0,0 @@
/* $FreeBSD$ */
/*-
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* The boot program passes a pointer (in the boot environment virtual
* address address space; "BEVA") to a bootinfo to the kernel using
* the following convention:
*
* a0 contains first free page frame number
* a1 contains page number of current level 1 page table
* if a2 contains BOOTINFO_MAGIC and a4 is nonzero:
* a3 contains pointer (BEVA) to bootinfo
* a4 contains bootinfo version number
* if a2 contains BOOTINFO_MAGIC and a4 contains 0 (backward compat):
* a3 contains pointer (BEVA) to bootinfo version
* (u_long), then the bootinfo
*/
#define BOOTINFO_MAGIC 0xdeadbeeffeedface
struct bootinfo_v1 {
u_long ssym; /* 0: start of kernel sym table */
u_long esym; /* 8: end of kernel sym table */
char boot_flags[64]; /* 16: boot flags */
char booted_kernel[64]; /* 80: name of booted kernel */
void *hwrpb; /* 144: hwrpb pointer (BEVA) */
u_long hwrpbsize; /* 152: size of hwrpb data */
int (*cngetc)(void); /* 160: console getc pointer */
void (*cnputc)(int); /* 168: console putc pointer */
void (*cnpollc)(int); /* 176: console pollc pointer */
u_long pad[6]; /* 184: rsvd for future use */
char *envp; /* 232: start of environment */
u_long kernend; /* 240: end of kernel */
u_long modptr; /* 248: FreeBSD module base */
/* 256: total size */
};
/*
* Kernel-internal structure used to hold important bits of boot
* information. NOT to be used by boot blocks.
*
* Note that not all of the fields from the bootinfo struct(s)
* passed by the boot blocks aren't here (because they're not currently
* used by the kernel!). Fields here which aren't supplied by the
* bootinfo structure passed by the boot blocks are supposed to be
* filled in at startup with sane contents.
*/
struct bootinfo_kernel {
u_long ssym; /* start of syms */
u_long esym; /* end of syms */
u_long modptr; /* FreeBSD module pointer */
u_long kernend; /* "end of kernel" from boot code */
char *envp; /* "end of kernel" from boot code */
u_long hwrpb_phys; /* hwrpb physical address */
u_long hwrpb_size; /* size of hwrpb data */
char boot_flags[64]; /* boot flags */
char booted_kernel[64]; /* name of booted kernel */
char booted_dev[64]; /* name of booted device */
};
extern struct bootinfo_kernel bootinfo;

480
sys/alpha/include/bus.h
View File

@ -1,480 +0,0 @@
/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
/*-
* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _ALPHA_BUS_H_
#define _ALPHA_BUS_H_
#include <machine/_bus.h>
#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFF
#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
/* The largest address space known so far is 40 bits */
#define BUS_SPACE_MAXADDR 0xFFFFFFFFFUL
#define BUS_SPACE_UNRESTRICTED (~0)
/*
* Map a region of device bus space into CPU virtual address space.
*/
static __inline int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
bus_size_t size, int flags,
bus_space_handle_t *bshp);
static __inline int
bus_space_map(bus_space_tag_t t __unused, bus_addr_t addr,
bus_size_t size __unused, int flags __unused,
bus_space_handle_t *bshp)
{
*bshp = addr;
return (0);
}
/*
* Unmap a region of device bus space.
*/
static __inline void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t size);
static __inline void
bus_space_unmap(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused,
bus_size_t size __unused)
{
}
/*
* Get a new handle for a subregion of an already-mapped area of bus space.
*/
static __inline int bus_space_subregion(bus_space_tag_t t,
bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size,
bus_space_handle_t *nbshp);
static __inline int
bus_space_subregion(bus_space_tag_t t __unused, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size __unused,
bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
struct alpha_busspace;
struct alpha_busspace_ops {
u_int8_t (*abo_read_1)(struct alpha_busspace *space, size_t offset);
u_int16_t (*abo_read_2)(struct alpha_busspace *space, size_t offset);
u_int32_t (*abo_read_4)(struct alpha_busspace *space, size_t offset);
void (*abo_read_multi_1)(struct alpha_busspace *space,
size_t offset,
u_int8_t *addr, size_t count);
void (*abo_read_multi_2)(struct alpha_busspace *space,
size_t offset,
u_int16_t *addr, size_t count);
void (*abo_read_multi_4)(struct alpha_busspace *space,
size_t offset,
u_int32_t *addr, size_t count);
void (*abo_read_region_1)(struct alpha_busspace *space,
size_t offset,
u_int8_t *addr, size_t count);
void (*abo_read_region_2)(struct alpha_busspace *space,
size_t offset,
u_int16_t *addr, size_t count);
void (*abo_read_region_4)(struct alpha_busspace *space,
size_t offset,
u_int32_t *addr, size_t count);
void (*abo_write_1)(struct alpha_busspace *space, size_t offset,
u_int8_t value);
void (*abo_write_2)(struct alpha_busspace *space, size_t offset,
u_int16_t value);
void (*abo_write_4)(struct alpha_busspace *space, size_t offset,
u_int32_t value);
void (*abo_write_multi_1)(struct alpha_busspace *space,
size_t offset,
const u_int8_t *addr, size_t count);
void (*abo_write_multi_2)(struct alpha_busspace *space,
size_t offset,
const u_int16_t *addr, size_t count);
void (*abo_write_multi_4)(struct alpha_busspace *space,
size_t offset,
const u_int32_t *addr, size_t count);
void (*abo_write_region_1)(struct alpha_busspace *space,
size_t offset,
const u_int8_t *addr, size_t count);
void (*abo_write_region_2)(struct alpha_busspace *space,
size_t offset,
const u_int16_t *addr, size_t count);
void (*abo_write_region_4)(struct alpha_busspace *space,
size_t offset,
const u_int32_t *addr, size_t count);
void (*abo_set_multi_1)(struct alpha_busspace *space, size_t offset,
u_int8_t value, size_t count);
void (*abo_set_multi_2)(struct alpha_busspace *space, size_t offset,
u_int16_t value, size_t count);
void (*abo_set_multi_4)(struct alpha_busspace *space, size_t offset,
u_int32_t value, size_t count);
void (*abo_set_region_1)(struct alpha_busspace *space,
size_t offset,
u_int8_t value, size_t count);
void (*abo_set_region_2)(struct alpha_busspace *space,
size_t offset,
u_int16_t value, size_t count);
void (*abo_set_region_4)(struct alpha_busspace *space,
size_t offset,
u_int32_t value, size_t count);
void (*abo_copy_region_1)(struct alpha_busspace *space,
size_t offset1, size_t offset2,
size_t count);
void (*abo_copy_region_2)(struct alpha_busspace *space,
size_t offset1, size_t offset2,
size_t count);
void (*abo_copy_region_4)(struct alpha_busspace *space,
size_t offset1, size_t offset2,
size_t count);
void (*abo_barrier)(struct alpha_busspace *space, size_t offset,
size_t len, int flags);
};
struct alpha_busspace {
struct alpha_busspace_ops *ab_ops;
};
/* Back-compat functions for old ISA drivers */
extern struct alpha_busspace *busspace_isa_io;
extern struct alpha_busspace *busspace_isa_mem;
#define inb(o) bus_space_read_1(busspace_isa_io, o, 0)
#define inw(o) bus_space_read_2(busspace_isa_io, o, 0)
#define inl(o) bus_space_read_4(busspace_isa_io, o, 0)
#define outb(o, v) bus_space_write_1(busspace_isa_io, o, 0, v)
#define outw(o, v) bus_space_write_2(busspace_isa_io, o, 0, v)
#define outl(o, v) bus_space_write_4(busspace_isa_io, o, 0, v)
#define readb(o) bus_space_read_1(busspace_isa_mem, o, 0)
#define readw(o) bus_space_read_2(busspace_isa_mem, o, 0)
#define readl(o) bus_space_read_4(busspace_isa_mem, o, 0)
#define writeb(o, v) bus_space_write_1(busspace_isa_mem, o, 0, v)
#define writew(o, v) bus_space_write_2(busspace_isa_mem, o, 0, v)
#define writel(o, v) bus_space_write_4(busspace_isa_mem, o, 0, v)
#define insb(o, a, c) bus_space_read_multi_1(busspace_isa_io, o, 0, \
(void*)(a), c)
#define insw(o, a, c) bus_space_read_multi_2(busspace_isa_io, o, 0, \
(void*)(a), c)
#define insl(o, a, c) bus_space_read_multi_4(busspace_isa_io, o, 0, \
(void*)(a), c)
#define outsb(o, a, c) bus_space_write_multi_1(busspace_isa_io, o, 0, \
(void*)(a), c)
#define outsw(o, a, c) bus_space_write_multi_2(busspace_isa_io, o, 0, \
(void*)(a), c)
#define outsl(o, a, c) bus_space_write_multi_4(busspace_isa_io, o, 0, \
(void*)(a), c)
#define memcpy_fromio(d, s, c) \
bus_space_read_region_1(busspace_isa_mem, (uintptr_t)(s), 0, d, c)
#define memcpy_toio(d, s, c) \
bus_space_write_region_1(busspace_isa_mem, (uintptr_t)(d), 0, s, c)
#define memcpy_io(d, s, c) \
bus_space_copy_region_1(busspace_isa_mem, (uintptr_t)(s), 0, d, 0, c)
#define memset_io(d, v, c) \
bus_space_set_region_1(busspace_isa_mem, (uintptr_t)(d), 0, v, c)
#define memsetw_io(d, v, c) \
bus_space_set_region_2(busspace_isa_mem, (uintptr_t)(d), 0, v, c)
static __inline void
memsetw(void *d, int val, size_t size)
{
u_int16_t *sp = d;
while (size--)
*sp++ = val;
}
void busspace_generic_read_multi_1(struct alpha_busspace *space,
size_t offset,
u_int8_t *addr, size_t count);
void busspace_generic_read_multi_2(struct alpha_busspace *space,
size_t offset,
u_int16_t *addr, size_t count);
void busspace_generic_read_multi_4(struct alpha_busspace *space,
size_t offset,
u_int32_t *addr, size_t count);
void busspace_generic_read_region_1(struct alpha_busspace *space,
size_t offset,
u_int8_t *addr, size_t count);
void busspace_generic_read_region_2(struct alpha_busspace *space,
size_t offset,
u_int16_t *addr, size_t count);
void busspace_generic_read_region_4(struct alpha_busspace *space,
size_t offset,
u_int32_t *addr, size_t count);
void busspace_generic_write_multi_1(struct alpha_busspace *space,
size_t offset,
const u_int8_t *addr, size_t count);
void busspace_generic_write_multi_2(struct alpha_busspace *space,
size_t offset,
const u_int16_t *addr, size_t count);
void busspace_generic_write_multi_4(struct alpha_busspace *space,
size_t offset,
const u_int32_t *addr, size_t count);
void busspace_generic_write_region_1(struct alpha_busspace *space,
size_t offset,
const u_int8_t *addr, size_t count);
void busspace_generic_write_region_2(struct alpha_busspace *space,
size_t offset,
const u_int16_t *addr, size_t count);
void busspace_generic_write_region_4(struct alpha_busspace *space,
size_t offset,
const u_int32_t *addr, size_t count);
void busspace_generic_set_multi_1(struct alpha_busspace *space,
size_t offset,
u_int8_t value, size_t count);
void busspace_generic_set_multi_2(struct alpha_busspace *space,
size_t offset,
u_int16_t value, size_t count);
void busspace_generic_set_multi_4(struct alpha_busspace *space,
size_t offset,
u_int32_t value, size_t count);
void busspace_generic_set_region_1(struct alpha_busspace *space,
size_t offset,
u_int8_t value, size_t count);
void busspace_generic_set_region_2(struct alpha_busspace *space,
size_t offset,
u_int16_t value, size_t count);
void busspace_generic_set_region_4(struct alpha_busspace *space,
size_t offset,
u_int32_t value, size_t count);
void busspace_generic_copy_region_1(struct alpha_busspace *space,
size_t offset1,
size_t offset2,
size_t count);
void busspace_generic_copy_region_2(struct alpha_busspace *space,
size_t offset1,
size_t offset2,
size_t count);
void busspace_generic_copy_region_4(struct alpha_busspace *space,
size_t offset1,
size_t offset2,
size_t count);
void busspace_generic_barrier(struct alpha_busspace *space,
size_t offset, size_t len,
int flags);
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
#define bus_space_read_1(t, h, o) \
(t)->ab_ops->abo_read_1(t, (h)+(o))
#define bus_space_read_2(t, h, o) \
(t)->ab_ops->abo_read_2(t, (h)+(o))
#define bus_space_read_4(t, h, o) \
(t)->ab_ops->abo_read_4(t, (h)+(o))
#define bus_space_read_multi_1(t, h, o, a, c) \
(t)->ab_ops->abo_read_multi_1(t, (h)+(o), a, c)
#define bus_space_read_multi_2(t, h, o, a, c) \
(t)->ab_ops->abo_read_multi_2(t, (h)+(o), a, c)
#define bus_space_read_multi_4(t, h, o, a, c) \
(t)->ab_ops->abo_read_multi_4(t, (h)+(o), a, c)
#define bus_space_read_region_1(t, h, o, a, c) \
(t)->ab_ops->abo_read_region_1(t, (h)+(o), a, c)
#define bus_space_read_region_2(t, h, o, a, c) \
(t)->ab_ops->abo_read_region_2(t, (h)+(o), a, c)
#define bus_space_read_region_4(t, h, o, a, c) \
(t)->ab_ops->abo_read_region_4(t, (h)+(o), a, c)
#define bus_space_write_1(t, h, o, v) \
(t)->ab_ops->abo_write_1(t, (h)+(o), v)
#define bus_space_write_2(t, h, o, v) \
(t)->ab_ops->abo_write_2(t, (h)+(o), v)
#define bus_space_write_4(t, h, o, v) \
(t)->ab_ops->abo_write_4(t, (h)+(o), v)
#define bus_space_write_multi_1(t, h, o, a, c) \
(t)->ab_ops->abo_write_multi_1(t, (h)+(o), a, c)
#define bus_space_write_multi_2(t, h, o, a, c) \
(t)->ab_ops->abo_write_multi_2(t, (h)+(o), a, c)
#define bus_space_write_multi_4(t, h, o, a, c) \
(t)->ab_ops->abo_write_multi_4(t, (h)+(o), a, c)
#define bus_space_write_region_1(t, h, o, a, c) \
(t)->ab_ops->abo_write_region_1(t, (h)+(o), a, c)
#define bus_space_write_region_2(t, h, o, a, c) \
(t)->ab_ops->abo_write_region_2(t, (h)+(o), a, c)
#define bus_space_write_region_4(t, h, o, a, c) \
(t)->ab_ops->abo_write_region_4(t, (h)+(o), a, c)
#define bus_space_set_multi_1(t, h, o, v, c) \
(t)->ab_ops->abo_set_multi_1(t, (h)+(o), v, c)
#define bus_space_set_multi_2(t, h, o, v, c) \
(t)->ab_ops->abo_set_multi_2(t, (h)+(o), v, c)
#define bus_space_set_multi_4(t, h, o, v, c) \
(t)->ab_ops->abo_set_multi_4(t, (h)+(o), v, c)
#define bus_space_set_region_1(t, h, o, v, c) \
(t)->ab_ops->abo_set_region_1(t, (h)+(o), v, c)
#define bus_space_set_region_2(t, h, o, v, c) \
(t)->ab_ops->abo_set_region_2(t, (h)+(o), v, c)
#define bus_space_set_region_4(t, h, o, v, c) \
(t)->ab_ops->abo_set_region_4(t, (h)+(o), v, c)
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
(t)->ab_ops->abo_copy_region_1(t, (h1)+(o1), (h2)+(o2), c)
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
(t)->ab_ops->abo_copy_region_2(t, (h1)+(o1), (h2)+(o2), c)
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
(t)->ab_ops->abo_copy_region_4(t, (h1)+(o1), (h2)+(o2), c)
#define bus_space_barrier(t, h, o, l, f) \
(t)->ab_ops->abo_barrier(t, (h)+(o), l, f)
/*
* Stream accesses are the same as normal accesses on alpha; there are no
* supported bus systems with an endianess different from the host one.
*/
#define bus_space_read_stream_1(t, h, o) bus_space_read_1((t), (h), (o))
#define bus_space_read_stream_2(t, h, o) bus_space_read_2((t), (h), (o))
#define bus_space_read_stream_4(t, h, o) bus_space_read_4((t), (h), (o))
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
bus_space_read_multi_1((t), (h), (o), (a), (c))
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
bus_space_read_multi_2((t), (h), (o), (a), (c))
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
bus_space_read_multi_4((t), (h), (o), (a), (c))
#define bus_space_write_stream_1(t, h, o, v) \
bus_space_write_1((t), (h), (o), (v))
#define bus_space_write_stream_2(t, h, o, v) \
bus_space_write_2((t), (h), (o), (v))
#define bus_space_write_stream_4(t, h, o, v) \
bus_space_write_4((t), (h), (o), (v))
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
bus_space_write_multi_1((t), (h), (o), (a), (c))
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
bus_space_write_multi_2((t), (h), (o), (a), (c))
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
bus_space_write_multi_4((t), (h), (o), (a), (c))
#define bus_space_set_multi_stream_1(t, h, o, v, c) \
bus_space_set_multi_1((t), (h), (o), (v), (c))
#define bus_space_set_multi_stream_2(t, h, o, v, c) \
bus_space_set_multi_2((t), (h), (o), (v), (c))
#define bus_space_set_multi_stream_4(t, h, o, v, c) \
bus_space_set_multi_4((t), (h), (o), (v), (c))
#define bus_space_read_region_stream_1(t, h, o, a, c) \
bus_space_read_region_1((t), (h), (o), (a), (c))
#define bus_space_read_region_stream_2(t, h, o, a, c) \
bus_space_read_region_2((t), (h), (o), (a), (c))
#define bus_space_read_region_stream_4(t, h, o, a, c) \
bus_space_read_region_4((t), (h), (o), (a), (c))
#define bus_space_write_region_stream_1(t, h, o, a, c) \
bus_space_write_region_1((t), (h), (o), (a), (c))
#define bus_space_write_region_stream_2(t, h, o, a, c) \
bus_space_write_region_2((t), (h), (o), (a), (c))
#define bus_space_write_region_stream_4(t, h, o, a, c) \
bus_space_write_region_4((t), (h), (o), (a), (c))
#define bus_space_set_region_stream_1(t, h, o, v, c) \
bus_space_set_region_1((t), (h), (o), (v), (c))
#define bus_space_set_region_stream_2(t, h, o, v, c) \
bus_space_set_region_2((t), (h), (o), (v), (c))
#define bus_space_set_region_stream_4(t, h, o, v, c) \
bus_space_set_region_4((t), (h), (o), (v), (c))
#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \
bus_space_copy_region_1((t), (h1), (o1), (h2), (o2), (c))
#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \
bus_space_copy_region_2((t), (h1), (o1), (h2), (o2), (c))
#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \
bus_space_copy_region_4((t), (h1), (o1), (h2), (o2), (c))
#include <machine/bus_dma.h>
#endif /* _ALPHA_BUS_H_ */

33
sys/alpha/include/bus_dma.h
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@ -1,33 +0,0 @@
/*-
* Copyright (c) 2005 Scott Long
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _ALPHA_BUS_DMA_H_
#define _ALPHA_BUS_DMA_H_
#include <sys/bus_dma.h>
#endif /* _ALPHA_BUS_DMA_H_ */

117
sys/alpha/include/bwx.h
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@ -1,117 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_BWX_H_
#define _MACHINE_BWX_H_
/*
* Byte/word accesses must be made with particular values for addr<37,38>
*/
#define BWX_EV56_INT8 (0L << 37)
#define BWX_EV56_INT4 (1L << 37)
#define BWX_EV56_INT2 (2L << 37)
#define BWX_EV56_INT1 (3L << 37)
static __inline u_int8_t
ldbu(vm_offset_t va)
{
u_int64_t r;
__asm__ __volatile__ ("ldbu %0,%1" : "=r"(r) : "m"(*(u_int8_t*)va));
return r;
}
static __inline u_int16_t
ldwu(vm_offset_t va)
{
u_int64_t r;
__asm__ __volatile__ ("ldwu %0,%1" : "=r"(r) : "m"(*(u_int16_t*)va));
return r;
}
static __inline u_int32_t
ldl(vm_offset_t va)
{
return *(u_int32_t*) va;
}
static __inline void
stb(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stb %1,%0" : "=m"(*(u_int8_t*)va) : "r"(r));
__asm__ __volatile__ ("mb");
}
static __inline void
stw(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stw %1,%0" : "=m"(*(u_int16_t*)va) : "r"(r));
__asm__ __volatile__ ("mb");
}
static __inline void
stl(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stl %1,%0" : "=m"(*(u_int32_t*)va) : "r"(r));
__asm__ __volatile__ ("mb");
}
static __inline void
stb_nb(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stb %1,%0" : "=m"(*(u_int8_t*)va) : "r"(r));
}
static __inline void
stw_nb(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stw %1,%0" : "=m"(*(u_int16_t*)va) : "r"(r));
}
static __inline void
stl_nb(vm_offset_t va, u_int64_t r)
{
__asm__ __volatile__ ("stl %1,%0" : "=m"(*(u_int32_t*)va) : "r"(r));
}
#ifdef _KERNEL
/*
* A kernel object for accessing memory-like spaces (port and
* memory spaces) using BWX instructions.
*/
struct bwx_space {
struct alpha_busspace_ops *ops;
u_int64_t base; /* base address of space */
};
void bwx_init_space(struct bwx_space *bwx, u_int64_t base);
#endif /* _KERNEL */
#endif /* !_MACHINE_BWX_H_ */

73
sys/alpha/include/chipset.h
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@ -1,73 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CHIPSET_H_
#define _MACHINE_CHIPSET_H_
typedef u_int64_t alpha_chipset_read_hae_t(void);
typedef void alpha_chipset_write_hae_t(u_int64_t);
struct sgmap;
typedef struct alpha_chipset {
/*
* Access the HAE register
*/
alpha_chipset_read_hae_t* read_hae;
alpha_chipset_write_hae_t* write_hae;
/*
* Scatter-Gather map for ISA dma.
*/
struct sgmap* sgmap;
/*
* Scatter-Gather map for PCI dma.
*/
struct sgmap* pci_sgmap;
/*
* direct map
*/
long dmsize;
long dmoffset;
} alpha_chipset_t;
extern alpha_chipset_t chipset;
/*
* Exported sysctl variables describing the PCI chipset.
*/
extern char chipset_type[10];
extern int chipset_bwx;
extern long chipset_ports;
extern long chipset_memory;
extern long chipset_dense;
extern long chipset_hae_mask;
#endif /* !_MACHINE_CHIPSET_H_ */

24
sys/alpha/include/clock.h
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@ -1,24 +0,0 @@
/*-
* Kernel interface to machine-dependent clock driver.
* Garrett Wollman, September 1994.
* This file is in the public domain.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CLOCK_H_
#define _MACHINE_CLOCK_H_
#ifdef _KERNEL
extern int disable_rtc_set;
extern int wall_cmos_clock;
extern int adjkerntz;
int sysbeep(int pitch, int period);
int acquire_timer2(int mode);
int release_timer2(void);
#endif
#endif /* !_MACHINE_CLOCK_H_ */

53
sys/alpha/include/clockvar.h
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@ -1,53 +0,0 @@
/* $FreeBSD$ */
/* $NetBSD: clockvar.h,v 1.4 1997/06/22 08:02:18 jonathan Exp $ */
/*-
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* Definitions for cpu-independent clock handling for the alpha and pmax.
*/
/*
* clocktime structure:
*
* structure passed to TOY clocks when setting them. broken out this
* way, so that the time_t -> field conversion can be shared.
*/
struct clocktime {
int year; /* year - 1900 */
int mon; /* month (1 - 12) */
int day; /* day (1 - 31) */
int hour; /* hour (0 - 23) */
int min; /* minute (0 - 59) */
int sec; /* second (0 - 59) */
int dow; /* day of week (0 - 6; 0 = Sunday) */
};
#include "clock_if.h"
void clockattach(device_t);

83
sys/alpha/include/cpu.h
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@ -1,83 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: cpu.h,v 1.18 1997/09/23 23:17:49 mjacob Exp */
/*-
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1982, 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah $Hdr: cpu.h 1.16 91/03/25$
*
* @(#)cpu.h 8.4 (Berkeley) 1/5/94
*/
#ifndef _ALPHA_CPU_H_
#define _ALPHA_CPU_H_
/*
* Exported definitions unique to Alpha cpu support.
*/
#include <machine/frame.h>
#define TRAPF_USERMODE(framep) \
(((framep)->tf_regs[FRAME_PS] & ALPHA_PSL_USERMODE) != 0)
#define TRAPF_PC(framep) ((framep)->tf_regs[FRAME_PC])
/*
* CTL_MACHDEP definitions.
*/
#define CPU_ROOT_DEVICE 2 /* string: root device name */
#define CPU_UNALIGNED_PRINT 3 /* int: print unaligned accesses */
#define CPU_UNALIGNED_FIX 4 /* int: fix unaligned accesses */
#define CPU_UNALIGNED_SIGBUS 5 /* int: SIGBUS unaligned accesses */
#define CPU_BOOTED_KERNEL 6 /* string: booted kernel name */
#ifdef _KERNEL
#ifdef GPROF
extern char btext[];
extern char etext[];
#endif
#define cpu_getstack(td) (alpha_pal_rdusp())
#define cpu_spinwait() /* nothing */
#define get_cyclecount() read_cycle_count()
void cpu_halt(void);
void cpu_reset(void);
void fork_trampoline(void); /* MAGIC */
uint64_t read_cycle_count(void);
void swi_vm(void *);
#endif /* _KERNEL */
#endif /* _ALPHA_CPU_H_ */

135
sys/alpha/include/cpuconf.h
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@ -1,135 +0,0 @@
/* $FreeBSD$ */
/* $NetBSD: cpuconf.h,v 1.7 1997/11/06 00:42:03 thorpej Exp $ */
#ifndef _ALPHA_CPUCONF_H
#define _ALPHA_CPUCONF_H
/*-
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Additional reworking by Matthew Jacob for NASA/Ames Research Center.
* Copyright (c) 1997
*/
#ifdef _KERNEL
/*
* Platform Specific Information and Function Hooks.
*
* The tags family and model information are strings describing the platform.
*
* The tag iobus describes the primary iobus for the platform- primarily
* to give a hint as to where to start configuring. The likely choices
* are one of tcasic, lca, apecs, cia, or tlsb.
*
*/
struct device; /* XXX */
struct resource; /* XXX */
extern struct platform {
/*
* Platform Information.
*/
const char *family; /* Family Name */
const char *model; /* Model (variant) Name */
const char *iobus; /* Primary iobus name */
/*
* Platform Specific Function Hooks
* cons_init - console initialization
* device_register - boot configuration aid
* iointr - I/O interrupt handler
* clockintr - Clock Interrupt Handler
* mcheck_handler - Platform Specific Machine Check Handler
*/
void (*cons_init)(void);
void (*device_register)(struct device *, void *);
void (*iointr)(void *, unsigned long);
void (*clockintr)(int, uintfptr_t);
void (*mcheck_handler)(unsigned long, struct trapframe *,
unsigned long, unsigned long);
void (*cpu_idle)(void);
void (*pci_intr_init)(void);
void (*pci_intr_map)(void *);
int (*pci_intr_route)(struct device *, struct device *, int);
void (*pci_intr_disable)(int);
void (*pci_intr_enable)(int);
int (*pci_setup_ide_intr)(struct device *dev,
struct device *child,
int chan, void (*fn)(void*), void *arg);
int (*isa_setup_intr)(struct device *, struct device *,
struct resource *, int, void *, void *, void **);
int (*isa_teardown_intr)(struct device *, struct device *,
struct resource *, void *);
} platform;
/*
* Lookup table entry for Alpha system variations.
*/
struct alpha_variation_table {
u_int64_t avt_variation; /* variation, from HWRPB */
const char *avt_model; /* model string */
};
/*
* There is an array of functions to initialize the platform structure.
*
* It's responsible for filling in the family, model_name and iobus
* tags. It may optionally fill in the cons_init, device_register and
* mcheck_handler tags.
*
* The iointr tag is filled in by set_iointr (in interrupt.c).
* The clockintr tag is filled in by cpu_initclocks (in clock.c).
*
* nocpu is function to call when you can't figure what platform you're on.
* There's no return from this function.
*/
struct cpuinit {
void (*init)(int);
const char *option;
};
#define cpu_notsupp(st) { platform_not_supported, st }
#define cpu_init(fn, opt) { fn, opt }
/*
* Misc. support routines.
*/
const char *alpha_dsr_sysname(void);
const char *alpha_variation_name(u_int64_t variation,
const struct alpha_variation_table *avtp);
const char *alpha_unknown_sysname(void);
extern struct cpuinit cpuinit[];
extern struct cpuinit api_cpuinit[];
extern int ncpuinit;
extern int napi_cpuinit;
extern void platform_not_configured(int);
extern void platform_not_supported(int);
#endif /* _KERNEL */
#endif /* !_ALPHA_CPUCONF_H */

68
sys/alpha/include/cpufunc.h
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@ -1,68 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <machine/chipset.h>
#include <machine/alpha_cpu.h>
#ifndef _SYS_CDEFS_H_
#error this file needs sys/cdefs.h as a prerequisite
#endif
struct thread;
#if defined(__GNUCLIKE_ASM)
static __inline void
breakpoint(void)
{
__asm __volatile("call_pal 0x81"); /* XXX bugchk */
}
#endif
static __inline register_t
intr_disable(void)
{
return (alpha_pal_swpipl(ALPHA_PSL_IPL_MCES));
}
static __inline void
intr_restore(register_t ipl)
{
alpha_pal_swpipl(ipl);
}
#endif /* _KERNEL */
#endif /* !_MACHINE_CPUFUNC_H_ */

100
sys/alpha/include/db_machdep.h
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@ -1,100 +0,0 @@
/* $FreeBSD$ */
/* $NetBSD: db_machdep.h,v 1.6 1997/09/06 02:02:25 thorpej Exp $ */
/*-
* Copyright (c) 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#ifndef _ALPHA_DB_MACHDEP_H_
#define _ALPHA_DB_MACHDEP_H_
#include <sys/param.h>
#include <vm/vm.h>
#include <machine/frame.h>
#define DB_NO_AOUT
typedef vm_offset_t db_addr_t; /* address - unsigned */
typedef long db_expr_t; /* expression - signed */
#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_context[7])
#define BKPT_INST 0x00000080 /* breakpoint instruction */
#define BKPT_SIZE (4) /* size of breakpoint inst */
#define BKPT_SET(inst) (BKPT_INST)
#define FIXUP_PC_AFTER_BREAK (kdb_frame->tf_regs[FRAME_PC] -= BKPT_SIZE);
#define SOFTWARE_SSTEP 1 /* no hardware support */
#define IS_BREAKPOINT_TRAP(type, code) \
((type) == ALPHA_KENTRY_IF && (code) == ALPHA_IF_CODE_BPT)
#define IS_WATCHPOINT_TRAP(type, code) 0
/*
* Functions needed for software single-stepping.
*/
boolean_t db_inst_trap_return(int inst);
boolean_t db_inst_return(int inst);
boolean_t db_inst_call(int inst);
boolean_t db_inst_branch(int inst);
boolean_t db_inst_load(int inst);
boolean_t db_inst_store(int inst);
boolean_t db_inst_unconditional_flow_transfer(int inst);
db_addr_t db_branch_taken(int inst, db_addr_t pc);
#define inst_trap_return(ins) db_inst_trap_return(ins)
#define inst_return(ins) db_inst_return(ins)
#define inst_call(ins) db_inst_call(ins)
#define inst_branch(ins) db_inst_branch(ins)
#define inst_load(ins) db_inst_load(ins)
#define inst_store(ins) db_inst_store(ins)
#define inst_unconditional_flow_transfer(ins) \
db_inst_unconditional_flow_transfer(ins)
#define branch_taken(ins, pc) db_branch_taken(ins, pc)
/* No delay slots on Alpha. */
#define next_instr_address(v, b) ((db_addr_t) ((b) ? (v) : ((v) + 4)))
u_long db_register_value(int);
/*
* Pretty arbitrary
*/
#define DB_SMALL_VALUE_MAX 0x7fffffff
#define DB_SMALL_VALUE_MIN (-0x400001)
/*
* We define some of our own commands.
*/
#define DB_MACHINE_COMMANDS
/*
* We use Elf64 symbols in DDB.
*/
#define DB_ELFSIZE 64
#endif /* _ALPHA_DB_MACHDEP_H_ */

138
sys/alpha/include/elf.h
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@ -1,138 +0,0 @@
/*-
* Copyright (c) 1996-1997 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_ELF_H_
#define _MACHINE_ELF_H_ 1
/*
* ELF definitions for the alpha architecture.
*/
#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */
#define __ELF_WORD_SIZE 64 /* Used by <sys/elf_generic.h> */
#include <sys/elf_generic.h>
#define ELF_ARCH EM_ALPHA
#define ELF_MACHINE_OK(x) ((x) == EM_ALPHA)
/*
* Auxiliary vector entries for passing information to the interpreter.
*
* The i386 supplement to the SVR4 ABI specification names this "auxv_t",
* but POSIX lays claim to all symbols ending with "_t".
*/
typedef struct { /* Auxiliary vector entry on initial stack */
long a_type; /* Entry type. */
union {
long a_val; /* Integer value. */
void *a_ptr; /* Address. */
void (*a_fcn)(void); /* Function pointer (not used). */
} a_un;
} Elf64_Auxinfo;
__ElfType(Auxinfo);
/* Values for a_type. */
#define AT_NULL 0 /* Terminates the vector. */
#define AT_IGNORE 1 /* Ignored entry. */
#define AT_EXECFD 2 /* File descriptor of program to load. */
#define AT_PHDR 3 /* Program header of program already loaded. */
#define AT_PHENT 4 /* Size of each program header entry. */
#define AT_PHNUM 5 /* Number of program header entries. */
#define AT_PAGESZ 6 /* Page size in bytes. */
#define AT_BASE 7 /* Interpreter's base address. */
#define AT_FLAGS 8 /* Flags (unused for i386). */
#define AT_ENTRY 9 /* Where interpreter should transfer control. */
/*
* The following non-standard values are used for passing information
* from John Polstra's testbed program to the dynamic linker. These
* are expected to go away soon.
*
* Unfortunately, these overlap the Linux non-standard values, so they
* must not be used in the same context.
*/
#define AT_BRK 10 /* Starting point for sbrk and brk. */
#define AT_DEBUG 11 /* Debugging level. */
/*
* The following non-standard values are used in Linux ELF binaries.
*/
#define AT_NOTELF 10 /* Program is not ELF ?? */
#define AT_UID 11 /* Real uid. */
#define AT_EUID 12 /* Effective uid. */
#define AT_GID 13 /* Real gid. */
#define AT_EGID 14 /* Effective gid. */
#define AT_COUNT 15 /* Count of defined aux entry types. */
/*
* Relocation types.
*/
#define R_ALPHA_NONE 0 /* No reloc */
#define R_ALPHA_REFLONG 1 /* Direct 32 bit */
#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */
#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */
#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */
#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */
#define R_ALPHA_GPDISP 6 /* Add displacement to GP */
#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */
#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */
#define R_ALPHA_SREL16 9 /* PC relative 16 bit */
#define R_ALPHA_SREL32 10 /* PC relative 32 bit */
#define R_ALPHA_SREL64 11 /* PC relative 64 bit */
#define R_ALPHA_OP_PUSH 12 /* OP stack push */
#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */
#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */
#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */
#define R_ALPHA_GPVALUE 16
#define R_ALPHA_GPRELHIGH 17
#define R_ALPHA_GPRELLOW 18
#define R_ALPHA_IMMED_GP_16 19
#define R_ALPHA_IMMED_GP_HI32 20
#define R_ALPHA_IMMED_SCN_HI32 21
#define R_ALPHA_IMMED_BR_HI32 22
#define R_ALPHA_IMMED_LO32 23
#define R_ALPHA_COPY 24 /* Copy symbol at runtime */
#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */
#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */
#define R_ALPHA_RELATIVE 27 /* Adjust by program base */
#define R_ALPHA_COUNT 28
/* Define "machine" characteristics */
#define ELF_TARG_CLASS ELFCLASS64
#define ELF_TARG_DATA ELFDATA2LSB
#define ELF_TARG_MACH EM_ALPHA
#define ELF_TARG_VER 1
#endif /* !_MACHINE_ELF_H_ */

127
sys/alpha/include/endian.h
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@ -1,127 +0,0 @@
/*-
* Copyright (c) 1987, 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)endian.h 8.1 (Berkeley) 6/10/93
* $NetBSD: endian.h,v 1.5 1997/10/09 15:42:19 bouyer Exp $
* $FreeBSD$
*/
#ifndef _MACHINE_ENDIAN_H_
#define _MACHINE_ENDIAN_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
/*
* Define the order of 32-bit words in 64-bit words.
*/
#define _QUAD_HIGHWORD 1
#define _QUAD_LOWWORD 0
/*
* Definitions for byte order, according to byte significance from low
* address to high.
*/
#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
#define _BYTE_ORDER _LITTLE_ENDIAN
/*
* Deprecated variants that don't have enough underscores to be useful in more
* strict namespaces.
*/
#if __BSD_VISIBLE
#define LITTLE_ENDIAN _LITTLE_ENDIAN
#define BIG_ENDIAN _BIG_ENDIAN
#define PDP_ENDIAN _PDP_ENDIAN
#define BYTE_ORDER _BYTE_ORDER
#endif
#if defined(__CC_SUPPORTS___INLINE) && defined(__GNUCLIKE_ASM)
static __inline __uint64_t
__bswap64(__uint64_t _x)
{
return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
((_x << 24) & ((__uint64_t)0xff << 40)) |
((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
}
static __inline __uint32_t
__bswap32(__uint32_t _x)
{
__uint32_t __r;
__asm __volatile__ (
"insbl %1, 3, $1\n\t"
"extbl %1, 1, $2\n\t"
"extbl %1, 2, $3\n\t"
"extbl %1, 3, $4\n\t"
"sll $2, 16, $2\n\t"
"sll $3, 8, $3\n\t"
"or $4, $1, %0\n\t"
"or $2, $3, $2\n\t"
"or $2, %0, %0"
: "=r" (__r) : "r" (_x) : "$1", "$2", "$3", "$4");
return (__r);
}
static __inline __uint16_t
__bswap16(__uint16_t _x)
{
__uint16_t __r;
__asm __volatile__ (
"insbl %1, 1, $1\n\t"
"extbl %1, 1, $2\n\t"
"or $1, $2, %0"
: "=r" (__r) : "r" (_x) : "$1", "$2");
return (__r);
}
#define __htonl(x) __bswap32(x)
#define __htons(x) __bswap16(x)
#define __ntohl(x) __bswap32(x)
#define __ntohs(x) __bswap16(x)
#else /* !(__CC_SUPPORTS___INLINE && __GNUCLIKE_ASM) */
/*
* No optimizations are available for this compiler. Fall back to
* non-optimized functions by defining the constant usually used to prevent
* redefinition.
*/
#define _BYTEORDER_FUNC_DEFINED
#endif /* __CC_SUPPORTS___INLINE && __GNUCLIKE_ASM */
#endif /* !_MACHINE_ENDIAN_H_ */

40
sys/alpha/include/exec.h
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@ -1,40 +0,0 @@
/*-
* Copyright (c) 1998 John Birrell <jb@cimlogic.com.au>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by John Birrell.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_EXEC_H_
#define _MACHINE_EXEC_H_
#define __LDPGSZ 8192
#endif /* !_MACHINE_EXEC_H_ */

79
sys/alpha/include/float.h
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@ -1,79 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: float.h,v 1.6 1997/07/17 21:36:03 thorpej Exp */
/*-
* Copyright (c) 1989, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ALPHA_FLOAT_H_
#define _ALPHA_FLOAT_H_
#include <sys/cdefs.h>
__BEGIN_DECLS
int __flt_rounds(void);
__END_DECLS
#define FLT_RADIX 2 /* b */
#define FLT_ROUNDS __flt_rounds()
#if __ISO_C_VISIBLE >= 1999
#define FLT_EVAL_METHOD 0 /* no promotions */
#define DECIMAL_DIG 17 /* max precision in decimal digits */
#endif
#define FLT_MANT_DIG 24 /* p */
#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
#define FLT_MIN_EXP -125 /* emin */
#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
#define FLT_MIN_10_EXP -37 /* ceil(log10(b**(emin-1))) */
#define FLT_MAX_EXP 128 /* emax */
#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
#define DBL_MANT_DIG 53
#define DBL_EPSILON 2.2204460492503131E-16
#define DBL_DIG 15
#define DBL_MIN_EXP -1021
#define DBL_MIN 2.2250738585072014E-308
#define DBL_MIN_10_EXP -307
#define DBL_MAX_EXP 1024
#define DBL_MAX 1.7976931348623157E+308
#define DBL_MAX_10_EXP 308
#define LDBL_MANT_DIG DBL_MANT_DIG
#define LDBL_EPSILON DBL_EPSILON
#define LDBL_DIG DBL_DIG
#define LDBL_MIN_EXP DBL_MIN_EXP
#define LDBL_MIN DBL_MIN
#define LDBL_MIN_10_EXP DBL_MIN_10_EXP
#define LDBL_MAX_EXP DBL_MAX_EXP
#define LDBL_MAX DBL_MAX
#define LDBL_MAX_10_EXP DBL_MAX_10_EXP
#endif /* _ALPHA_FLOAT_H_ */

35
sys/alpha/include/floatingpoint.h
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@ -1,35 +0,0 @@
/*-
* Copyright (c) 1998 John Birrell <jb@cimlogic.com.au>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by John Birrell.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <machine/ieeefp.h>

124
sys/alpha/include/fpu.h
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@ -1,124 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_FPU_H_
#define _MACHINE_FPU_H_
/*
* Floating point control register bits.
*
* From Alpha AXP Architecture Reference Manual, Instruction
* Descriptions (I) PP 4-69.
*/
#define FPCR_INVD (1LL << 49) /* Invalid Operation DIsable */
#define FPCR_DZED (1LL << 50) /* Division by Zero Disable */
#define FPCR_OVFD (1LL << 51) /* Overflow Disable */
#define FPCR_INV (1LL << 52) /* Invalid Operation */
#define FPCR_DZE (1LL << 53) /* Division by Zero */
#define FPCR_OVF (1LL << 54) /* Overflow */
#define FPCR_UNF (1LL << 55) /* Underflow */
#define FPCR_INE (1LL << 56) /* Inexact Result */
#define FPCR_IOV (1LL << 57) /* Integer Overflow */
#define FPCR_DYN_CHOPPED (0LL << 58) /* Chopped rounding mode */
#define FPCR_DYN_MINUS (1LL << 58) /* Minus infinity */
#define FPCR_DYN_NORMAL (2LL << 58) /* Normal rounding */
#define FPCR_DYN_PLUS (3LL << 58) /* Plus infinity */
#define FPCR_DYN_MASK (3LL << 58) /* Rounding mode mask */
#define FPCR_DYN_SHIFT 58
#define FPCR_UNDZ (1LL << 60) /* Underflow to Zero */
#define FPCR_UNFD (1LL << 61) /* Underflow Disable */
#define FPCR_INED (1LL << 62) /* Inexact Disable */
#define FPCR_SUM (1LL << 63) /* Summary Bit */
#define FPCR_MASK (~0LL << 49)
#define FPCR_STATUS_MASK (FPCR_INV | FPCR_DZE | FPCR_OVF | \
FPCR_UNF | FPCR_INE | FPCR_IOV)
/*
* Exception summary bits.
*
* From Alpha AXP Architecture Reference Manual, DEC OSF/1 Exceptions
* and Interrupts (II-B) PP 5-5.
*/
#define EXCSUM_SWC (1LL << 0) /* Software completion */
#define EXCSUM_INV (1LL << 1) /* Invalid operation */
#define EXCSUM_DZE (1LL << 2) /* Division by zero */
#define EXCSUM_OVF (1LL << 3) /* Overflow */
#define EXCSUM_UNF (1LL << 4) /* Underflow */
#define EXCSUM_INE (1LL << 5) /* Inexact result */
#define EXCSUM_IOV (1LL << 6) /* Integer overflow */
/*
* Definitions for IEEE trap enables. These are implemented in
* software and should be compatible with OSF/1 and Linux.
*/
/* read/write flags */
#define IEEE_TRAP_ENABLE_INV (1LL << 1) /* Invalid operation */
#define IEEE_TRAP_ENABLE_DZE (1LL << 2) /* Division by zero */
#define IEEE_TRAP_ENABLE_OVF (1LL << 3) /* Overflow */
#define IEEE_TRAP_ENABLE_UNF (1LL << 4) /* Underflow */
#define IEEE_TRAP_ENABLE_INE (1LL << 5) /* Inexact result */
#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV \
| IEEE_TRAP_ENABLE_DZE \
| IEEE_TRAP_ENABLE_OVF \
| IEEE_TRAP_ENABLE_UNF \
| IEEE_TRAP_ENABLE_INE)
/* read only flags */
#define IEEE_STATUS_INV (1LL << 17) /* Invalid operation */
#define IEEE_STATUS_DZE (1LL << 18) /* Division by zero */
#define IEEE_STATUS_OVF (1LL << 19) /* Overflow */
#define IEEE_STATUS_UNF (1LL << 20) /* Underflow */
#define IEEE_STATUS_INE (1LL << 21) /* Inexact result */
#define IEEE_STATUS_MASK (IEEE_STATUS_INV \
| IEEE_STATUS_DZE \
| IEEE_STATUS_OVF \
| IEEE_STATUS_UNF \
| IEEE_STATUS_INE)
#define IEEE_STATUS_TO_EXCSUM_SHIFT 16 /* convert to excsum */
#define IEEE_STATUS_TO_FPCR_SHIFT 35 /* convert to fpcr */
#define IEEE_INHERIT (1LL << 63) /* inherit on fork */
/* read and write floating point control register */
#define GET_FPCR(x) \
__asm__("trapb"); \
__asm__("mf_fpcr %0" : "=f" (x)); \
__asm__("trapb")
#define SET_FPCR(x) \
__asm__("trapb"); \
__asm__("mt_fpcr %0" : : "f" (x)); \
__asm__("trapb")
#ifdef _KERNEL
extern int fp_software_completion(u_int64_t regmask, struct thread *td);
#endif
#endif /* ! _MACHINE_FPU_H_ */

101
sys/alpha/include/frame.h
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@ -1,101 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: frame.h,v 1.4 1997/04/06 08:47:27 cgd Exp */
/*-
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#ifndef _ALPHA_FRAME_H_
#define _ALPHA_FRAME_H_
#include <machine/alpha_cpu.h>
/*
* Software trap, exception, and syscall frame.
*
* Includes "hardware" (PALcode) frame.
*
* PALcode puts ALPHA_HWFRAME_* fields on stack. We have to add
* all of the general-purpose registers except for zero, for sp
* (which is automatically saved in the PCB's USP field for entries
* from user mode, and which is implicitly saved and restored by the
* calling conventions for entries from kernel mode), and (on traps
* and exceptions) for a0, a1, and a2 (which are saved by PALcode).
*/
/* Quadword offsets of the registers to be saved. */
#define FRAME_V0 0
#define FRAME_T0 1
#define FRAME_T1 2
#define FRAME_T2 3
#define FRAME_T3 4
#define FRAME_T4 5
#define FRAME_T5 6
#define FRAME_T6 7
#define FRAME_T7 8
#define FRAME_S0 9
#define FRAME_S1 10
#define FRAME_S2 11
#define FRAME_S3 12
#define FRAME_S4 13
#define FRAME_S5 14
#define FRAME_S6 15
#define FRAME_A3 16
#define FRAME_A4 17
#define FRAME_A5 18
#define FRAME_T8 19
#define FRAME_T9 20
#define FRAME_T10 21
#define FRAME_T11 22
#define FRAME_RA 23
#define FRAME_T12 24
#define FRAME_AT 25
#define FRAME_SP 26
#define FRAME_FLAGS 27
#define FRAME_FLAGS_SYSCALL 1 /* partial frame for syscalls */
/* The following are set only when a signal is to be delivered to a process. */
#define FRAME_TRAPARG_A0 28
#define FRAME_TRAPARG_A1 29
#define FRAME_TRAPARG_A2 30
#define FRAME_SW_SIZE (FRAME_TRAPARG_A2 + 1)
#define FRAME_HW_OFFSET FRAME_SW_SIZE
#define FRAME_PS (FRAME_HW_OFFSET + ALPHA_HWFRAME_PS)
#define FRAME_PC (FRAME_HW_OFFSET + ALPHA_HWFRAME_PC)
#define FRAME_GP (FRAME_HW_OFFSET + ALPHA_HWFRAME_GP)
#define FRAME_A0 (FRAME_HW_OFFSET + ALPHA_HWFRAME_A0)
#define FRAME_A1 (FRAME_HW_OFFSET + ALPHA_HWFRAME_A1)
#define FRAME_A2 (FRAME_HW_OFFSET + ALPHA_HWFRAME_A2)
#define FRAME_HW_SIZE ALPHA_HWFRAME_SIZE
#define FRAME_SIZE (FRAME_HW_OFFSET + FRAME_HW_SIZE)
struct trapframe {
unsigned long tf_regs[FRAME_SIZE]; /* See above */
};
#endif /* _ALPHA_FRAME_H_ */

52
sys/alpha/include/gdb_machdep.h
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@ -1,52 +0,0 @@
/*-
* Copyright (c) 2004 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_GDB_MACHDEP_H_
#define _MACHINE_GDB_MACHDEP_H_
#define GDB_BUFSZ 600
#define GDB_NREGS 67
#define GDB_REG_PC 64
static __inline size_t
gdb_cpu_regsz(int regnum)
{
return (sizeof(long));
}
static __inline int
gdb_cpu_query(void)
{
return (0);
}
void *gdb_cpu_getreg(int, size_t *);
void gdb_cpu_setreg(int, void *);
int gdb_cpu_signal(int, int);
#endif /* !_MACHINE_GDB_MACHDEP_H_ */

115
sys/alpha/include/ieee.h
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@ -1,115 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: ieee.h,v 1.2 1997/04/06 08:47:27 cgd Exp */
/*-
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ieee.h 8.1 (Berkeley) 6/11/93
*
* from: Header: ieee.h,v 1.7 92/11/26 02:04:37 torek Exp
*/
/*
* ieee.h defines the machine-dependent layout of the machine's IEEE
* floating point. It does *not* define (yet?) any of the rounding
* mode bits, exceptions, and so forth.
*/
/*
* Define the number of bits in each fraction and exponent.
*
* k k+1
* Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
*
* (-exp_bias+1)
* as fractions that look like 0.fffff x 2 . This means that
*
* -126
* the number 0.10000 x 2 , for instance, is the same as the normalized
*
* -127 -128
* float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
*
* -129
* in the fraction; to represent 2 , we need two, and so on. This
*
* (-exp_bias-fracbits+1)
* implies that the smallest denormalized number is 2
*
* for whichever format we are talking about: for single precision, for
*
* -126 -149
* instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
*
* -149 == -127 - 23 + 1.
*/
#define SNG_EXPBITS 8
#define SNG_FRACBITS 23
#define DBL_EXPBITS 11
#define DBL_FRACBITS 52
struct ieee_single {
u_int sng_frac:23;
u_int sng_exp:8;
u_int sng_sign:1;
};
struct ieee_double {
u_int dbl_fracl;
u_int dbl_frach:20;
u_int dbl_exp:11;
u_int dbl_sign:1;
};
/*
* Floats whose exponent is in [1..INFNAN) (of whatever type) are
* `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
* Floats whose exponent is zero are either zero (iff all fraction
* bits are zero) or subnormal values.
*
* A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
* high fraction; if the bit is set, it is a `quiet NaN'.
*/
#define SNG_EXP_INFNAN 255
#define DBL_EXP_INFNAN 2047
#if 0
#define SNG_QUIETNAN (1 << 22)
#define DBL_QUIETNAN (1 << 19)
#endif
/*
* Exponent biases.
*/
#define SNG_EXP_BIAS 127
#define DBL_EXP_BIAS 1023

29
sys/alpha/include/ieeefp.h
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@ -1,29 +0,0 @@
/* $FreeBSD$ */
/* From: NetBSD: ieeefp.h,v 1.2 1997/04/06 08:47:28 cgd Exp */
/*-
* Written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _ALPHA_IEEEFP_H_
#define _ALPHA_IEEEFP_H_
typedef int fp_except_t;
#define FP_X_INV (1LL << 1) /* invalid operation exception */
#define FP_X_DZ (1LL << 2) /* divide-by-zero exception */
#define FP_X_OFL (1LL << 3) /* overflow exception */
#define FP_X_UFL (1LL << 4) /* underflow exception */
#define FP_X_IMP (1LL << 5) /* imprecise(inexact) exception */
#if 0
#define FP_X_IOV (1LL << 6) /* integer overflow XXX? */
#endif
typedef enum {
FP_RZ=0, /* round to zero (truncate) */
FP_RM=1, /* round toward negative infinity */
FP_RN=2, /* round to nearest representable number */
FP_RP=3 /* round toward positive infinity */
} fp_rnd_t;
#endif /* _ALPHA_IEEEFP_H_ */

76
sys/alpha/include/in_cksum.h
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@ -1,76 +0,0 @@
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from tahoe: in_cksum.c 1.2 86/01/05
* from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
* from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
* $FreeBSD$
*/
#ifndef _MACHINE_IN_CKSUM_H_
#define _MACHINE_IN_CKSUM_H_ 1
#include <sys/cdefs.h>
#define in_cksum(m, len) in_cksum_skip(m, len, 0)
/*
* It it useful to have an Internet checksum routine which is inlineable
* and optimized specifically for the task of computing IP header checksums
* in the normal case (where there are no options and the header length is
* therefore always exactly five 32-bit words.
*/
#ifdef __CC_SUPPORTS___INLINE
static __inline void
in_cksum_update(struct ip *ip)
{
int __tmpsum;
__tmpsum = (int)ntohs(ip->ip_sum) + 256;
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
}
#else
#define in_cksum_update(ip) \
do { \
int __tmpsum; \
__tmpsum = (int)ntohs(ip->ip_sum) + 256; \
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16)); \
} while(0)
#endif
#ifdef _KERNEL
u_int in_cksum_hdr(const struct ip *ip);
u_short in_addword(u_short sum, u_short b);
u_short in_pseudo(u_int sum, u_int b, u_int c);
u_short in_cksum_skip(struct mbuf *m, int len, int skip);
#endif
#endif /* _MACHINE_IN_CKSUM_H_ */

462
sys/alpha/include/inst.h
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@ -1,462 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_INST_H_
#define _MACHINE_INST_H_
union alpha_instruction {
u_int32_t word;
struct {
u_int32_t argument : 26;
u_int32_t opcode : 6;
#define op_call_pal 0x00
#define op_lda 0x08
#define op_ldah 0x09
#define op_ldbu 0x0a
#define op_unop 0x0b
#define op_ldq_u 0x0b
#define op_ldwu 0x0c
#define op_stw 0x0d
#define op_stb 0x0e
#define op_stq_u 0x0f
#define op_inta 0x10
#define inta_addl 0x00
#define inta_s4addl 0x02
#define inta_subl 0x09
#define inta_s4subl 0x0b
#define inta_cmpbge 0x0f
#define inta_s8addl 0x12
#define inta_s8subl 0x1b
#define inta_cmpult 0x1d
#define inta_addq 0x20
#define inta_s4addq 0x22
#define inta_subq 0x29
#define inta_s4subq 0x2b
#define inta_cmpeq 0x2d
#define inta_s8addq 0x32
#define inta_s8subq 0x3b
#define inta_cmpule 0x3d
#define inta_addlv 0x40
#define inta_sublv 0x49
#define inta_cmplt 0x4d
#define inta_addqv 0x60
#define inta_subqv 0x69
#define inta_cmple 0x6d
#define op_intl 0x11
#define intl_and 0x00
#define intl_andnot 0x08
#define intl_bic 0x08
#define intl_cmovlbs 0x14
#define intl_cmovlbc 0x16
#define intl_or 0x20
#define intl_bis 0x20
#define intl_cmoveq 0x24
#define intl_cmovne 0x26
#define intl_ornot 0x28
#define intl_xor 0x40
#define intl_cmovlt 0x44
#define intl_cmovge 0x46
#define intl_eqv 0x48
#define intl_amask 0x61
#define intl_cmovle 0x64
#define intl_cmovgt 0x66
#define intl_implver 0x6c
#define op_ints 0x12
#define ints_mskbl 0x02
#define ints_extbl 0x06
#define ints_insbl 0x0b
#define ints_mskwl 0x12
#define ints_extwl 0x16
#define ints_inswl 0x1b
#define ints_mskll 0x22
#define ints_extll 0x26
#define ints_insll 0x2b
#define ints_zap 0x30
#define ints_zapnot 0x31
#define ints_mskql 0x32
#define ints_srl 0x34
#define ints_extql 0x36
#define ints_sll 0x39
#define ints_insql 0x3b
#define ints_sra 0x3c
#define ints_mskwh 0x52
#define ints_inswh 0x57
#define ints_extwh 0x5a
#define ints_msklh 0x62
#define ints_inslh 0x67
#define ints_extlh 0x6a
#define ints_mskqh 0x72
#define ints_insqh 0x77
#define ints_extqh 0x7a
#define op_intm 0x13
#define intm_mull 0x00
#define intm_mulq 0x20
#define intm_umulh 0x30
#define intm_mullv 0x40
#define intm_mulqv 0x60
#define op_opc14 0x14
#define op_fltv 0x15
#define op_flti 0x16
#define flti_addsc 0x000
#define flti_subsc 0x001
#define flti_mulsc 0x002
#define flti_divsc 0x003
#define flti_addtc 0x020
#define flti_subtc 0x021
#define flti_multc 0x022
#define flti_divtc 0x023
#define flti_cvttsc 0x02c
#define flti_cvttqc 0x02f
#define flti_cvtqsc 0x03c
#define flti_cvtqtc 0x03e
#define flti_addsm 0x040
#define flti_subsm 0x041
#define flti_mulsm 0x042
#define flti_divsm 0x043
#define flti_addtm 0x060
#define flti_subtm 0x061
#define flti_multm 0x062
#define flti_divtm 0x063
#define flti_cvttsm 0x06c
#define flti_cvttqm 0x06f
#define flti_cvtqsm 0x07c
#define flti_cvtqtm 0x07e
#define flti_adds 0x080
#define flti_subs 0x081
#define flti_muls 0x082
#define flti_divs 0x083
#define flti_addt 0x0a0
#define flti_subt 0x0a1
#define flti_mult 0x0a2
#define flti_divt 0x0a3
#define flti_cmptun 0x0a4
#define flti_cmpteq 0x0a5
#define flti_cmptlt 0x0a6
#define flti_cmptle 0x0a7
#define flti_cvtts 0x0ac
#define flti_cvttq 0x0af
#define flti_cvtqs 0x0bc
#define flti_cvtqt 0x0be
#define flti_addsd 0x0c0
#define flti_subsd 0x0c1
#define flti_mulsd 0x0c2
#define flti_divsd 0x0c3
#define flti_addtd 0x0e0
#define flti_subtd 0x0e1
#define flti_multd 0x0e2
#define flti_divtd 0x0e3
#define flti_cvttsd 0x0ec
#define flti_cvttqd 0x0ef
#define flti_cvtqsd 0x0fc
#define flti_cvtqtd 0x0fe
#define flti_addsuc 0x100
#define flti_subsuc 0x101
#define flti_mulsuc 0x102
#define flti_divsuc 0x103
#define flti_addtuc 0x120
#define flti_subtuc 0x121
#define flti_multuc 0x122
#define flti_divtuc 0x123
#define flti_cvttsuc 0x12c
#define flti_cvttqvc 0x12f
#define flti_addsum 0x140
#define flti_subsum 0x141
#define flti_mulsum 0x142
#define flti_divsum 0x143
#define flti_addtum 0x160
#define flti_subtum 0x161
#define flti_multum 0x162
#define flti_divtum 0x163
#define flti_cvttsum 0x16c
#define flti_cvttqvm 0x16f
#define flti_addsu 0x180
#define flti_subsu 0x181
#define flti_mulsu 0x182
#define flti_divsu 0x183
#define flti_addtu 0x1a0
#define flti_subtu 0x1a1
#define flti_multu 0x1a2
#define flti_divtu 0x1a3
#define flti_cvttsu 0x1ac
#define flti_cvttqv 0x1af
#define flti_addsud 0x1c0
#define flti_subsud 0x1c1
#define flti_mulsud 0x1c2
#define flti_divsud 0x1c3
#define flti_addtud 0x1e0
#define flti_subtud 0x1e1
#define flti_multud 0x1e2
#define flti_divtud 0x1e3
#define flti_cvttsud 0x1ec
#define flti_cvttqvd 0x1ef
#define flti_cvtst 0x2ac
#define flti_addssuc 0x500
#define flti_subssuc 0x501
#define flti_mulssuc 0x502
#define flti_divssuc 0x503
#define flti_addtsuc 0x520
#define flti_subtsuc 0x521
#define flti_multsuc 0x522
#define flti_divtsuc 0x523
#define flti_cvttssuc 0x52c
#define flti_cvttqsvc 0x52f
#define flti_addssum 0x540
#define flti_subssum 0x541
#define flti_mulssum 0x542
#define flti_divssum 0x543
#define flti_addtsum 0x560
#define flti_subtsum 0x561
#define flti_multsum 0x562
#define flti_divtsum 0x563
#define flti_cvttssum 0x56c
#define flti_cvttqsvm 0x56f
#define flti_addssu 0x580
#define flti_subssu 0x581
#define flti_mulssu 0x582
#define flti_divssu 0x583
#define flti_addtsu 0x5a0
#define flti_subtsu 0x5a1
#define flti_multsu 0x5a2
#define flti_divtsu 0x5a3
#define flti_cmptunsu 0x5a4
#define flti_cmpteqsu 0x5a5
#define flti_cmptltsu 0x5a6
#define flti_cmptlesu 0x5a7
#define flti_cvttssu 0x5ac
#define flti_cvttqsv 0x5af
#define flti_addssud 0x5c0
#define flti_subssud 0x5c1
#define flti_mulssud 0x5c2
#define flti_divssud 0x5c3
#define flti_addtsud 0x5e0
#define flti_subtsud 0x5e1
#define flti_multsud 0x5e2
#define flti_divtsud 0x5e3
#define flti_cvttssud 0x5ec
#define flti_cvttqsvd 0x5ef
#define flti_cvtsts 0x6ac
#define flti_addssuic 0x700
#define flti_subssuic 0x701
#define flti_mulssuic 0x702
#define flti_divssuic 0x703
#define flti_addtsuic 0x720
#define flti_subtsuic 0x721
#define flti_multsuic 0x722
#define flti_divtsuic 0x723
#define flti_cvttssuic 0x72c
#define flti_cvttqsvic 0x72f
#define flti_cvtqssuic 0x73c
#define flti_cvtqtsuic 0x73e
#define flti_addssuim 0x740
#define flti_subssuim 0x741
#define flti_mulssuim 0x742
#define flti_divssuim 0x743
#define flti_addtsuim 0x760
#define flti_subtsuim 0x761
#define flti_multsuim 0x762
#define flti_divtsuim 0x763
#define flti_cvttssuim 0x76c
#define flti_cvttqsvim 0x76f
#define flti_cvtqssuim 0x77c
#define flti_cvtqtsuim 0x77e
#define flti_addssui 0x780
#define flti_subssui 0x781
#define flti_mulssui 0x782
#define flti_divssui 0x783
#define flti_addtsui 0x7a0
#define flti_subtsui 0x7a1
#define flti_multsui 0x7a2
#define flti_divtsui 0x7a3
#define flti_cmptunsui 0x7a4
#define flti_cmpteqsui 0x7a5
#define flti_cmptltsui 0x7a6
#define flti_cmptlesui 0x7a7
#define flti_cvttssui 0x7ac
#define flti_cvttqsvi 0x7af
#define flti_cvtqssui 0x7bc
#define flti_cvtqtsui 0x7bc
#define flti_addssuid 0x7c0
#define flti_subssuid 0x7c1
#define flti_mulssuid 0x7c2
#define flti_divssuid 0x7c3
#define flti_addtsuid 0x7e0
#define flti_subtsuid 0x7e1
#define flti_multsuid 0x7e2
#define flti_divtsuid 0x7e3
#define flti_cvttssuid 0x7ec
#define flti_cvttqsvid 0x7ef
#define flti_cvtqssuid 0x7fc
#define flti_cvtqtsuid 0x7fc
#define op_fltl 0x17
#define fltl_cvtlq 0x010
#define fltl_cpys 0x020
#define fltl_cpysn 0x021
#define fltl_cpyse 0x022
#define fltl_mt_fpcr 0x024
#define fltl_mf_fpcr 0x025
#define fltl_fcmoveq 0x02a
#define fltl_fcmovne 0x02b
#define fltl_fcmovlt 0x02c
#define fltl_fcmovge 0x02d
#define fltl_fcmovle 0x02e
#define fltl_fcmovgt 0x02f
#define fltl_cvtql 0x030
#define fltl_cvtqlv 0x130
#define fltl_cvtqlsv 0x530
#define op_misc 0x18
#define misc_trapb 0x0000
#define misc_excb 0x0400
#define misc_mb 0x4000
#define misc_wmb 0x4400
#define misc_fetch 0x8000
#define misc_fetch_m 0xa000
#define misc_rpcc 0xc000
#define misc_rc 0xe000
#define misc_ecb 0xe800
#define misc_rs 0xf000
#define misc_wh64 0xf800
#define op_pal19 0x19
#define op_jsr 0x1a
#define op_pal1b 0x1b
#define op_pal1c 0x1c
#define op_pal1d 0x1d
#define op_pal1e 0x1e
#define op_pal1f 0x1f
#define op_ldf 0x20
#define op_ldg 0x21
#define op_lds 0x22
#define op_ldt 0x23
#define op_stf 0x24
#define op_stg 0x25
#define op_sts 0x26
#define op_stt 0x27
#define op_ldl 0x28
#define op_ldq 0x29
#define op_ldl_l 0x2a
#define op_ldq_l 0x2b
#define op_stl 0x2c
#define op_stq 0x2d
#define op_stl_c 0x2e
#define op_stq_c 0x2f
#define op_br 0x30
#define op_fbeq 0x31
#define op_fblt 0x32
#define op_fble 0x33
#define op_bsr 0x34
#define op_fbne 0x35
#define op_fbge 0x36
#define op_fbgt 0x37
#define op_blbc 0x38
#define op_beq 0x39
#define op_blt 0x3a
#define op_ble 0x3b
#define op_blbs 0x3c
#define op_bne 0x3d
#define op_bge 0x3e
#define op_bgt 0x3f
} common;
struct {
u_int32_t function : 16;
u_int32_t rb : 5;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} memory_format;
struct {
u_int32_t hint : 14;
u_int32_t function : 2;
#define jsr_jmp 0
#define jsr_jsr 1
#define jsr_ret 2
#define jsr_jsr_coroutine 3
u_int32_t rb : 5;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} j_format;
struct {
int32_t memory_displacement : 16;
u_int32_t rb : 5;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} m_format;
struct {
u_int32_t rc : 5;
u_int32_t function : 7;
u_int32_t form : 1;
u_int32_t sbz : 3;
u_int32_t rb : 5;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} o_format;
struct {
u_int32_t rc : 5;
u_int32_t function : 7;
u_int32_t form : 1;
u_int32_t literal : 8;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} l_format;
struct {
u_int32_t fc : 5;
u_int32_t function : 11;
u_int32_t fb : 5;
u_int32_t fa : 5;
u_int32_t opcode : 6;
} f_format;
struct {
u_int32_t function : 26;
u_int32_t opcode : 6;
} pal_format;
struct {
int32_t branch_displacement : 21;
u_int32_t ra : 5;
u_int32_t opcode : 6;
} b_format;
};
#endif /* _MACHINE_INST_H_ */

41
sys/alpha/include/intr.h
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@ -1,41 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
extern struct mtx icu_lock;
int alpha_setup_intr(const char *name, uintptr_t vector,
driver_intr_t handler, void *arg, enum intr_type flags,
void **cookiep, volatile long *cntp,
void (*disable)(uintptr_t), void (*enable)(uintptr_t));
int alpha_teardown_intr(void *cookie);
void alpha_dispatch_intr(void *frame, unsigned long vector);
#endif /* !_MACHINE_INTR_H_ */

73
sys/alpha/include/intrcnt.h
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@ -1,73 +0,0 @@
/* $FreeBSD$ */
/* $NetBSD: intrcnt.h,v 1.17 1998/11/19 01:48:04 ross Exp $ */
/*-
* Copyright (c) 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#define INTRCNT_CLOCK 0
#define INTRCNT_ISA_IRQ (INTRCNT_CLOCK + 1)
#define INTRCNT_ISA_IRQ_LEN 16
#define INTRCNT_OTHER_BASE (INTRCNT_ISA_IRQ + INTRCNT_ISA_IRQ_LEN)
#define INTRCNT_OTHER_LEN 48
#define INTRCNT_COUNT (INTRCNT_OTHER_BASE + INTRCNT_OTHER_LEN)
#define INTRCNT_A12_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_DEC_1000A_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_DEC_1000_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_DEC_2100_A500_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_DEC_550_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_EB164_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_EB64PLUS_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_EB66_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_IOASIC INTRCNT_OTHER_BASE
#define INTRCNT_KN15 INTRCNT_OTHER_BASE
#define INTRCNT_KN16 INTRCNT_OTHER_BASE
#define INTRCNT_KN20AA_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_KN300_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_KN8AE_IRQ INTRCNT_OTHER_BASE
#define INTRCNT_TCDS INTRCNT_OTHER_BASE
#define INTRCNT_A12_IRQ_LEN 10
#define INTRCNT_DEC_1000A_IRQ_LEN 32
#define INTRCNT_DEC_1000_IRQ_LEN 16
#define INTRCNT_DEC_2100_A500_IRQ_LEN 16
#define INTRCNT_DEC_550_IRQ_LEN 48
#define INTRCNT_EB164_IRQ_LEN 24
#define INTRCNT_EB64PLUS_IRQ_LEN 32
#define INTRCNT_EB66_IRQ_LEN 32
#define INTRCNT_IOASIC_LEN 4
#define INTRCNT_ISA_IRQ_LEN 16
#define INTRCNT_KN15_LEN 9
#define INTRCNT_KN16_LEN 5
#define INTRCNT_KN20AA_IRQ_LEN 32
#define INTRCNT_KN300_LEN 19
#define INTRCNT_KN8AE_IRQ_LEN 2
#define INTRCNT_TCDS_LEN 2
# define INTRCNT_KN300_NCR810 INTRCNT_KN300_IRQ + 16
# define INTRCNT_KN300_I2C_CTRL INTRCNT_KN300_IRQ + 17
# define INTRCNT_KN300_I2C_BUS INTRCNT_KN300_IRQ + 18

40
sys/alpha/include/ioctl_bt848.h
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@ -1,40 +0,0 @@
/*-
* Copyright (c) 2003 David O'Brien
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_IOCTL_BT848_H_
#define _MACHINE_IOCTL_BT848_H_
#include <sys/cdefs.h>
#ifdef __CC_SUPPORTS_WARNING
#warning Include dev/bktr/ioctl_bt848.h instead of this header.
#endif
#include <dev/bktr/ioctl_bt848.h>
#endif /* _MACHINE_IOCTL_BT848_H_ */

40
sys/alpha/include/ioctl_meteor.h
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@ -1,40 +0,0 @@
/*-
* Copyright (c) 2003 David O'Brien
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_IOCTL_METEOR_H_
#define _MACHINE_IOCTL_METEOR_H_
#include <sys/cdefs.h>
#ifdef __CC_SUPPORTS_WARNING
#warning Include dev/bktr/ioctl_meteor.h instead of this header.
#endif
#include <dev/bktr/ioctl_meteor.h>
#endif /* _MACHINE_IOCTL_METEOR_H_ */

51
sys/alpha/include/kdb.h
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@ -1,51 +0,0 @@
/*-
* Copyright (c) 2004 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_KDB_H_
#define _MACHINE_KDB_H_
#include <machine/frame.h>
#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid]
static __inline void
kdb_cpu_clear_singlestep(void)
{
}
static __inline void
kdb_cpu_set_singlestep(void)
{
}
static __inline void
kdb_cpu_trap(int vector, int _)
{
}
#endif /* _MACHINE_KDB_H_ */

45
sys/alpha/include/limits.h
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@ -1,45 +0,0 @@
/*-
* Copyright (c) 1988, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
* From: NetBSD: limits.h,v 1.3 1997/04/06 08:47:31 cgd Exp
* $FreeBSD$
*/
#ifndef _MACHINE_LIMITS_H_
#define _MACHINE_LIMITS_H_
#include <sys/cdefs.h>
#ifdef __CC_SUPPORTS_WARNING
#warning "machine/limits.h is deprecated. Include sys/limits.h instead."
#endif
#include <sys/limits.h>
#endif /* !_MACHINE_LIMITS_H_ */

110
sys/alpha/include/md_var.h
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@ -1,110 +0,0 @@
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_MD_VAR_H_
#define _MACHINE_MD_VAR_H_
/*
* Miscellaneous machine-dependent declarations.
*/
struct cam_sim;
struct reg;
struct rpb;
struct thread;
struct trapframe;
extern char sigcode[];
extern char esigcode[];
extern int szsigcode;
#ifdef COMPAT_43
extern int szosigcode;
#endif
#ifdef COMPAT_FREEBSD4
extern int szfreebsd4_sigcode;
#endif
extern long Maxmem;
extern int busdma_swi_pending;
extern struct rpb *hwrpb;
extern volatile int mc_expected;
extern volatile int mc_received;
void XentArith(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void XentIF(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void XentInt(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void XentMM(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void XentRestart(void); /* MAGIC */
void XentSys(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void XentUna(u_int64_t, u_int64_t, u_int64_t); /* MAGIC */
void alpha_fpstate_check(struct thread *td);
void alpha_fpstate_drop(struct thread *td);
void alpha_fpstate_save(struct thread *td, int write);
void alpha_fpstate_switch(struct thread *td);
void alpha_init(u_long, u_long, u_long, u_long, u_long);
int alpha_pa_access(u_long);
void alpha_register_pci_scsi(int bus, int slot, struct cam_sim *sim);
int badaddr(void *, size_t);
int badaddr_read(void *, size_t, void *);
void busdma_swi(void);
u_int64_t console_restart(u_int64_t, u_int64_t, u_int64_t);
void dumpconf(void);
void exception_return(void); /* MAGIC */
void frametoreg(struct trapframe *, struct reg *);
long fswintrberr(void); /* MAGIC */
u_int64_t hwrpb_checksum(void);
void hwrpb_restart_setup(void);
void init_prom_interface(struct rpb*);
void interrupt(unsigned long, unsigned long, unsigned long,
struct trapframe *);
int is_physical_memory(vm_offset_t addr);
void machine_check(unsigned long, struct trapframe *, unsigned long,
unsigned long);
void regdump(struct trapframe *);
void regtoframe(struct reg *, struct trapframe *);
void set_iointr(void (*)(void *, unsigned long));
void switch_exit(struct thread *); /* MAGIC */
void syscall(u_int64_t, struct trapframe *);
void trap(unsigned long, unsigned long, unsigned long, unsigned long,
struct trapframe *);
#ifdef _SYS_BUS_H_
struct resource *alpha_platform_alloc_ide_intr(int chan);
int alpha_platform_release_ide_intr(int chan, struct resource *res);
int alpha_platform_setup_ide_intr(struct device *dev, struct resource *res,
driver_intr_t *fn, void *arg, void **cookiep);
int alpha_platform_teardown_ide_intr(struct device *dev,
struct resource *res, void *cookie);
int alpha_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags, driver_intr_t *intr, void *arg,
void **cookiep);
int alpha_platform_pci_teardown_intr(device_t dev, device_t child,
struct resource *irq, void *cookie);
int alpha_pci_route_interrupt(device_t bus, device_t dev, int pin);
#endif
#endif /* !_MACHINE_MD_VAR_H_ */

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