Add C11 atomic fallbacks for ARM.
Basically the situation is as follows: - When using Clang + armv6, we should not need any intrinsics. It should support it, even though due to a target misconfiguration it does not. We should fix this in Clang. - When using Clang + noarmv6, provide __atomic_* functions that disable interrupts. - When using GCC + armv6, we can provide __sync_* intrinsics, similar to what we did for MIPS. As ARM and MIPS are quite similar, simply base this implementation on the one I did for MIPS. - When using GCC + noarmv6, disable the interrupts, like we do for Clang. This implementation still lacks functions for noarmv6 userspace. To be done.
This commit is contained in:
Ed Schouten
parent
87d2d3599e
commit
67ccda16de
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=251695
540
sys/arm/arm/stdatomic.c
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540
sys/arm/arm/stdatomic.c
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@ -0,0 +1,540 @@
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/*-
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* Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/stdatomic.h>
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#include <sys/types.h>
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#include <machine/cpufunc.h>
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#ifdef _KERNEL
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#include "opt_global.h"
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#endif
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/*
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* Executing statements with interrupts disabled.
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*/
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#ifndef SMP
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#define WITHOUT_INTERRUPTS(s) do { \
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register_t regs; \
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\
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regs = intr_disable(); \
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do s while (0); \
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intr_restore(regs); \
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} while (0)
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#endif /* !SMP */
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/*
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* Memory barriers.
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*
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* It turns out __sync_synchronize() does not emit any code when used
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* with GCC 4.2. Implement our own version that does work reliably.
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*
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* Although __sync_lock_test_and_set() should only perform an acquire
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* barrier, make it do a full barrier like the other functions. This
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* should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
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*/
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static inline void
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do_sync(void)
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{
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#if defined(_KERNEL) && !defined(SMP)
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__asm volatile ("" : : : "memory");
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#elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
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__asm volatile ("dmb" : : : "memory");
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#else /* __ARM_ARCH_6__ */
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__asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
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#endif
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}
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#if defined(__CLANG_ATOMICS) || defined(__GNUC_ATOMICS)
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/*
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* New C11 __atomic_* API.
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*/
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#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || \
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defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
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/* These systems should be supported by the compiler. */
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#elif defined(_KERNEL)
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#ifdef SMP
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#error "On SMP systems we should have proper atomic operations."
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#endif
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/* Clang doesn't allow us to reimplement builtins without this. */
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#ifdef __clang__
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#pragma redefine_extname __sync_synchronize_ext __sync_synchronize
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#define __sync_synchronize __sync_synchronize_ext
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#endif
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void
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__sync_synchronize(void)
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{
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do_sync();
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}
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/*
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* On uniprocessor systems, we can perform the atomic operations by
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* disabling interrupts.
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*/
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#define EMIT_LOAD_N(N, uintN_t) \
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uintN_t \
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__atomic_load_##N(uintN_t *mem, int model __unused) \
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{ \
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uintN_t ret; \
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\
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WITHOUT_INTERRUPTS({ \
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ret = *mem; \
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}); \
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return (ret); \
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}
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#define EMIT_STORE_N(N, uintN_t) \
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void \
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__atomic_store_##N(uintN_t *mem, uintN_t val, int model __unused) \
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{ \
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\
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WITHOUT_INTERRUPTS({ \
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*mem = val; \
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}); \
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}
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#define EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
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_Bool \
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__atomic_compare_exchange_##N(uintN_t *mem, uintN_t *expected, \
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uintN_t desired, int success __unused, int failure __unused) \
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{ \
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_Bool ret; \
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\
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WITHOUT_INTERRUPTS({ \
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if (*mem == *expected) { \
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*mem = desired; \
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ret = 1; \
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} else { \
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*expected = *mem; \
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ret = 0; \
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} \
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}); \
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return (ret); \
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}
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#define EMIT_FETCH_OP_N(N, uintN_t, name, op) \
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uintN_t \
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__atomic_##name##_##N(uintN_t *mem, uintN_t val, int model __unused) \
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{ \
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uintN_t ret; \
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\
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WITHOUT_INTERRUPTS({ \
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ret = *mem; \
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*mem op val; \
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}); \
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return (ret); \
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}
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#define EMIT_ALL_OPS_N(N, uintN_t) \
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EMIT_LOAD_N(N, uintN_t) \
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EMIT_STORE_N(N, uintN_t) \
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EMIT_COMPARE_EXCHANGE_N(N, uintN_t) \
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EMIT_FETCH_OP_N(N, uintN_t, exchange, =) \
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EMIT_FETCH_OP_N(N, uintN_t, fetch_add, +=) \
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EMIT_FETCH_OP_N(N, uintN_t, fetch_and, &=) \
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EMIT_FETCH_OP_N(N, uintN_t, fetch_or, |=) \
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EMIT_FETCH_OP_N(N, uintN_t, fetch_sub, -=) \
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EMIT_FETCH_OP_N(N, uintN_t, fetch_xor, ^=)
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EMIT_ALL_OPS_N(1, uint8_t)
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EMIT_ALL_OPS_N(2, uint16_t)
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EMIT_ALL_OPS_N(4, uint32_t)
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EMIT_ALL_OPS_N(8, uint64_t)
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#else /* !__ARM_ARCH_6__ && !__ARM_ARCH_7__ && !_KERNEL */
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/* XXX: Implement intrinsics for ARMv5 userspace. */
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#endif
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#endif /* __CLANG_ATOMICS || __GNUC_ATOMICS */
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/*
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* Old __sync_* API.
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*/
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#if defined(__SYNC_ATOMICS)
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#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || \
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defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
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/* Implementations for old GCC versions, lacking support for atomics. */
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typedef union {
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uint8_t v8[4];
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uint32_t v32;
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} reg_t;
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/*
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* Given a memory address pointing to an 8-bit or 16-bit integer, return
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* the address of the 32-bit word containing it.
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*/
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static inline uint32_t *
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round_to_word(void *ptr)
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{
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return ((uint32_t *)((intptr_t)ptr & ~3));
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}
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/*
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* Utility functions for loading and storing 8-bit and 16-bit integers
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* in 32-bit words at an offset corresponding with the location of the
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* atomic variable.
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*/
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static inline void
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put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
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{
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size_t offset;
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offset = (intptr_t)offset_ptr & 3;
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r->v8[offset] = val;
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}
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static inline uint8_t
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get_1(const reg_t *r, const uint8_t *offset_ptr)
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{
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size_t offset;
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offset = (intptr_t)offset_ptr & 3;
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return (r->v8[offset]);
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}
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static inline void
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put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
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{
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size_t offset;
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union {
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uint16_t in;
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uint8_t out[2];
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} bytes;
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offset = (intptr_t)offset_ptr & 3;
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bytes.in = val;
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r->v8[offset] = bytes.out[0];
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r->v8[offset + 1] = bytes.out[1];
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}
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static inline uint16_t
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get_2(const reg_t *r, const uint16_t *offset_ptr)
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{
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size_t offset;
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union {
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uint8_t in[2];
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uint16_t out;
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} bytes;
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offset = (intptr_t)offset_ptr & 3;
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bytes.in[0] = r->v8[offset];
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bytes.in[1] = r->v8[offset + 1];
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return (bytes.out);
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}
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/*
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* 8-bit and 16-bit routines.
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*
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* These operations are not natively supported by the CPU, so we use
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* some shifting and bitmasking on top of the 32-bit instructions.
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*/
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#define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
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uintN_t \
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__sync_lock_test_and_set_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, negmask, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_##N(&val32, mem, val); \
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negmask.v32 = 0xffffffff; \
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put_##N(&negmask, mem, 0); \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tldrex %0, %6\n" /* Load old value. */ \
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"\tand %2, %5, %0\n" /* Remove the old value. */ \
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"\torr %2, %2, %4\n" /* Put in the new value. */ \
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"\tstrex %3, %2, %1\n" /* Attempt to store. */ \
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"\tcmp %3, #0\n" /* Did it succeed? */ \
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"\tbne 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
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EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
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#define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
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uintN_t \
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__sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
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uintN_t desired) \
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{ \
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uint32_t *mem32; \
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reg_t expected32, desired32, posmask, negmask, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem); \
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expected32.v32 = 0x00000000; \
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put_##N(&expected32, mem, expected); \
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desired32.v32 = 0x00000000; \
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put_##N(&desired32, mem, desired); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask.v32 = ~posmask.v32; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tldrex %0, %8\n" /* Load old value. */ \
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"\tand %2, %6, %0\n" /* Isolate the old value. */ \
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"\tcmp %2, %4\n" /* Compare to expected value. */\
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"\tbne 2f\n" /* Values are unequal. */ \
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"\tand %2, %7, %0\n" /* Remove the old value. */ \
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"\torr %2, %5\n" /* Put in the new value. */ \
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"\tstrex %3, %2, %1\n" /* Attempt to store. */ \
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"\tcmp %3, #0\n" /* Did it succeed? */ \
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"\tbne 1b\n" /* Spin if failed. */ \
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"2:" \
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: "=&r" (old), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (expected32.v32), "r" (desired32.v32), \
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"r" (posmask.v32), "r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
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EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
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#define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask, negmask, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_##N(&val32, mem, val); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask.v32 = ~posmask.v32; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tldrex %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate the new value. */ \
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"\tand %3, %6, %0\n" /* Remove the old value. */ \
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"\torr %2, %2, %3\n" /* Put in the new value. */ \
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"\tstrex %3, %2, %1\n" /* Attempt to store. */ \
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"\tcmp %3, #0\n" /* Did it succeed? */ \
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"\tbne 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask.v32), \
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"r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "add")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "sub")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "add")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "sub")
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#define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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put_##N(&val32, mem, val); \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tldrex %0, %5\n" /* Load old value. */ \
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"\t"op" %2, %4, %0\n" /* Calculate new value. */ \
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"\tstrex %3, %2, %1\n" /* Attempt to store. */ \
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"\tcmp %3, #0\n" /* Did it succeed? */ \
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"\tbne 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "orr", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "eor", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "orr", 0)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "eor", 0)
|
||||
|
||||
/*
|
||||
* 32-bit routines.
|
||||
*/
|
||||
|
||||
uint32_t
|
||||
__sync_val_compare_and_swap_4(uint32_t *mem, uint32_t expected,
|
||||
uint32_t desired)
|
||||
{
|
||||
uint32_t old, temp1, temp2;
|
||||
|
||||
do_sync();
|
||||
__asm volatile (
|
||||
"1:"
|
||||
"\tldrex %0, %6\n" /* Load old value. */
|
||||
"\tcmp %0, %4\n" /* Compare to expected value. */
|
||||
"\tbne 2f\n" /* Values are unequal. */
|
||||
"\tmov %2, %5\n" /* Value to store. */
|
||||
"\tstrex %3, %2, %1\n" /* Attempt to store. */
|
||||
"\tcmp %3, #0\n" /* Did it succeed? */
|
||||
"\tbne 1b\n" /* Spin if failed. */
|
||||
"2:"
|
||||
: "=&r" (old), "=m" (*mem), "=&r" (temp1), "=&r" (temp2)
|
||||
: "r" (expected), "r" (desired), "m" (*mem));
|
||||
return (old);
|
||||
}
|
||||
|
||||
#define EMIT_FETCH_AND_OP_4(name, op) \
|
||||
uint32_t \
|
||||
__sync_##name##_4(uint32_t *mem, uint32_t val) \
|
||||
{ \
|
||||
uint32_t old, temp1, temp2; \
|
||||
\
|
||||
do_sync(); \
|
||||
__asm volatile ( \
|
||||
"1:" \
|
||||
"\tldrex %0, %5\n" /* Load old value. */ \
|
||||
"\t"op"\n" /* Calculate new value. */ \
|
||||
"\tstrex %3, %2, %1\n" /* Attempt to store. */ \
|
||||
"\tcmp %3, #0\n" /* Did it succeed? */ \
|
||||
"\tbne 1b\n" /* Spin if failed. */ \
|
||||
: "=&r" (old), "=m" (*mem), "=&r" (temp1), \
|
||||
"=&r" (temp2) \
|
||||
: "r" (val), "m" (*mem)); \
|
||||
return (old); \
|
||||
}
|
||||
|
||||
EMIT_FETCH_AND_OP_4(lock_test_and_set, "mov %2, %4")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_add, "add %2, %0, %4")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_and, "and %2, %0, %4")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_or, "orr %2, %0, %4")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_sub, "sub %2, %0, %4")
|
||||
EMIT_FETCH_AND_OP_4(fetch_and_xor, "eor %2, %0, %4")
|
||||
|
||||
#elif defined(_KERNEL)
|
||||
|
||||
#ifdef SMP
|
||||
#error "On SMP systems we should have proper atomic operations."
|
||||
#endif
|
||||
|
||||
/*
|
||||
* On uniprocessor systems, we can perform the atomic operations by
|
||||
* disabling interrupts.
|
||||
*/
|
||||
|
||||
#define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
|
||||
uintN_t \
|
||||
__sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
|
||||
uintN_t desired) \
|
||||
{ \
|
||||
uintN_t ret; \
|
||||
\
|
||||
WITHOUT_INTERRUPTS({ \
|
||||
ret = *mem; \
|
||||
if (*mem == expected) \
|
||||
*mem = desired; \
|
||||
}); \
|
||||
return (ret); \
|
||||
}
|
||||
|
||||
#define EMIT_FETCH_AND_OP_N(N, uintN_t, name, op) \
|
||||
uintN_t \
|
||||
__sync_##name##_##N(uintN_t *mem, uintN_t val) \
|
||||
{ \
|
||||
uintN_t ret; \
|
||||
\
|
||||
WITHOUT_INTERRUPTS({ \
|
||||
ret = *mem; \
|
||||
*mem op val; \
|
||||
}); \
|
||||
return (ret); \
|
||||
}
|
||||
|
||||
#define EMIT_ALL_OPS_N(N, uintN_t) \
|
||||
EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, lock_test_and_set, =) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_add, +=) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_and, &=) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_or, |=) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_sub, -=) \
|
||||
EMIT_FETCH_AND_OP_N(N, uintN_t, fetch_and_xor, ^=)
|
||||
|
||||
EMIT_ALL_OPS_N(1, uint8_t)
|
||||
EMIT_ALL_OPS_N(2, uint16_t)
|
||||
EMIT_ALL_OPS_N(4, uint32_t)
|
||||
EMIT_ALL_OPS_N(8, uint64_t)
|
||||
|
||||
#else /* !__ARM_ARCH_6__ && !__ARM_ARCH_7__ && !_KERNEL */
|
||||
|
||||
/* XXX: Implement intrinsics for ARMv5 userspace. */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SYNC_ATOMICS */
|
||||
@ -40,6 +40,8 @@ arm/arm/sc_machdep.c optional sc
|
||||
arm/arm/setcpsr.S standard
|
||||
arm/arm/setstack.s standard
|
||||
arm/arm/stack_machdep.c optional ddb | stack
|
||||
arm/arm/stdatomic.c standard \
|
||||
compile-with "${NORMAL_C:N-Wmissing-prototypes}"
|
||||
arm/arm/support.S standard
|
||||
arm/arm/swtch.S standard
|
||||
arm/arm/sys_machdep.c standard
|
||||
|
||||
Loading…
Reference in New Issue
Block a user