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Merge commit 28de0fb48 from llvm git (by Luís Marques):

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[RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x defines

  The RISCV target did not set the GCC atomic compare and swap defines,
  unlike other targets. This broke builds for things like glib on
  RISCV.

  Patch by Kristof Provost (kprovost)

  Differential Revision: https://reviews.llvm.org/D91784

This should fix building glib20 on RISC-V and unblock a number of
dependent ports.

Requested by:	kp
MFC after:	3 days
This commit is contained in:
Dimitry Andric 2020-12-09 18:37:43 +00:00
parent 02354beae7
commit 6813f2420b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=368489
1 changed files with 7 additions and 1 deletions
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8
contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
View File

@ -115,8 +115,14 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__riscv_muldiv");
}
if (HasA)
if (HasA) {
Builder.defineMacro("__riscv_atomic");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
if (Is64Bit)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
if (HasF || HasD) {
Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");