bus_dma_dmar_set_buswide(9): KPI to indicate that the whole dmar
context should share page tables. Practically it means that dma requests from any device on the bus are translated according to the entries loaded for the bus:0:0 device. KPI requires that the slot and function of the device be 0:0, and that no tags for other devices on the bus were used. The intended use are NTBs which pass TLPs from the downstream to the host with slot:func of the downstream originator. Reviewed and tested by: mav Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D22434
This commit is contained in:
parent
738b2d5ceb
commit
685666aaf7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354830
@ -191,5 +191,7 @@ _bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
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return (tc->impl->map_complete(dmat, map, segs, nsegs, error));
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}
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bool bus_dma_dmar_set_buswide(device_t dev);
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#endif /* !_X86_BUS_DMA_H_ */
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@ -289,6 +289,34 @@ dmar_get_dma_tag(device_t dev, device_t child)
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return (res);
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}
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bool
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bus_dma_dmar_set_buswide(device_t dev)
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{
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struct dmar_unit *dmar;
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device_t parent;
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u_int busno, slot, func;
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parent = device_get_parent(dev);
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if (device_get_devclass(parent) != devclass_find("pci"))
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return (false);
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dmar = dmar_find(dev, bootverbose);
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if (dmar == NULL)
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return (false);
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busno = pci_get_bus(dev);
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slot = pci_get_slot(dev);
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func = pci_get_function(dev);
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if (slot != 0 || func != 0) {
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if (bootverbose) {
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device_printf(dev,
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"dmar%d pci%d:%d:%d requested buswide busdma\n",
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dmar->unit, busno, slot, func);
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}
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return (false);
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}
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dmar_set_buswide_ctx(dmar, busno);
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return (true);
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}
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static MALLOC_DEFINE(M_DMAR_DMAMAP, "dmar_dmamap", "Intel DMAR DMA Map");
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static void dmar_bus_schedule_dmamap(struct dmar_unit *unit,
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@ -67,8 +67,8 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcivar.h>
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static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context");
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@ -141,20 +141,9 @@ ctx_tag_init(struct dmar_ctx *ctx, device_t dev)
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}
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static void
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ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move)
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ctx_id_entry_init_one(dmar_ctx_entry_t *ctxp, struct dmar_domain *domain,
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vm_page_t ctx_root)
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{
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struct dmar_unit *unit;
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struct dmar_domain *domain;
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vm_page_t ctx_root;
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domain = ctx->domain;
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unit = domain->dmar;
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KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0),
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("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",
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unit->unit, pci_get_bus(ctx->ctx_tag.owner),
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pci_get_slot(ctx->ctx_tag.owner),
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pci_get_function(ctx->ctx_tag.owner),
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ctxp->ctx1, ctxp->ctx2));
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/*
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* For update due to move, the store is not atomic. It is
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* possible that DMAR read upper doubleword, while low
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@ -166,16 +155,48 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move)
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*/
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dmar_pte_store1(&ctxp->ctx2, DMAR_CTX2_DID(domain->domain) |
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domain->awlvl);
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if (ctx_root == NULL) {
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dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_PASS | DMAR_CTX1_P);
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} else {
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dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_UNTR |
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(DMAR_CTX1_ASR_MASK & VM_PAGE_TO_PHYS(ctx_root)) |
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DMAR_CTX1_P);
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}
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}
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static void
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ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move,
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int busno)
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{
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struct dmar_unit *unit;
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struct dmar_domain *domain;
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vm_page_t ctx_root;
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int i;
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domain = ctx->domain;
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unit = domain->dmar;
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KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0),
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("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",
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unit->unit, busno, pci_get_slot(ctx->ctx_tag.owner),
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pci_get_function(ctx->ctx_tag.owner),
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ctxp->ctx1, ctxp->ctx2));
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if ((domain->flags & DMAR_DOMAIN_IDMAP) != 0 &&
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(unit->hw_ecap & DMAR_ECAP_PT) != 0) {
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KASSERT(domain->pgtbl_obj == NULL,
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("ctx %p non-null pgtbl_obj", ctx));
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dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_PASS | DMAR_CTX1_P);
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ctx_root = NULL;
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} else {
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ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0, DMAR_PGF_NOALLOC);
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dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_UNTR |
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(DMAR_CTX1_ASR_MASK & VM_PAGE_TO_PHYS(ctx_root)) |
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DMAR_CTX1_P);
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}
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if (dmar_is_buswide_ctx(unit, busno)) {
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MPASS(!move);
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for (i = 0; i <= PCI_BUSMAX; i++) {
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ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
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}
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} else {
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ctx_id_entry_init_one(ctxp, domain, ctx_root);
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}
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dmar_flush_ctx_to_ram(unit, ctxp);
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}
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@ -444,6 +465,9 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
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enable = false;
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TD_PREP_PINNED_ASSERT;
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DMAR_LOCK(dmar);
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KASSERT(!dmar_is_buswide_ctx(dmar, bus) || (slot == 0 && func == 0),
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("dmar%d pci%d:%d:%d get_ctx for buswide", dmar->unit, bus,
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slot, func));
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ctx = dmar_find_ctx_locked(dmar, rid);
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error = 0;
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if (ctx == NULL) {
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@ -492,7 +516,7 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
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if (LIST_EMPTY(&dmar->domains))
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enable = true;
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LIST_INSERT_HEAD(&dmar->domains, domain, link);
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ctx_id_entry_init(ctx, ctxp, false);
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ctx_id_entry_init(ctx, ctxp, false, bus);
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if (dev != NULL) {
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device_printf(dev,
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"dmar%d pci%d:%d:%d:%d rid %x domain %d mgaw %d "
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@ -597,7 +621,7 @@ dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx)
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dmar_ctx_unlink(ctx);
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ctx->domain = domain;
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dmar_ctx_link(ctx);
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ctx_id_entry_init(ctx, ctxp, true);
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ctx_id_entry_init(ctx, ctxp, true, PCI_BUSMAX + 100);
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dmar_unmap_pgtbl(sf);
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error = dmar_flush_for_ctx_entry(dmar, true);
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/* If flush failed, rolling back would not work as well. */
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@ -239,6 +239,15 @@ struct dmar_unit {
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struct taskqueue *delayed_taskqueue;
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int dma_enabled;
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/*
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* Bitmap of buses for which context must ignore slot:func,
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* duplicating the page table pointer into all context table
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* entries. This is a client-controlled quirk to support some
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* NTBs.
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*/
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uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
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};
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#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock)
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@ -377,6 +386,9 @@ void dmar_quirks_pre_use(struct dmar_unit *dmar);
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int dmar_init_irt(struct dmar_unit *unit);
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void dmar_fini_irt(struct dmar_unit *unit);
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void dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno);
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bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
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#define DMAR_GM_CANWAIT 0x0001
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#define DMAR_GM_CANSPLIT 0x0002
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@ -69,9 +69,9 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <x86/iommu/intel_dmar.h>
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#ifdef DEV_APIC
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#include "pcib_if.h"
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@ -595,6 +595,26 @@ static driver_t dmar_driver = {
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DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
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MODULE_DEPEND(dmar, acpi, 1, 1, 1);
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void
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dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno)
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{
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MPASS(busno <= PCI_BUSMAX);
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DMAR_LOCK(unit);
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unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
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1 << (busno % (NBBY * sizeof(uint32_t)));
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DMAR_UNLOCK(unit);
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}
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bool
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dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
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{
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MPASS(busno <= PCI_BUSMAX);
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return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
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(1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
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}
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static void
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dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
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{
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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/*
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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static int domain_unmap_buf_locked(struct dmar_domain *domain,
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@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcivar.h>
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#include <x86/iommu/iommu_intrmap.h>
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@ -58,6 +58,7 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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static bool
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@ -60,6 +60,7 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcivar.h>
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@ -66,6 +66,7 @@ __FBSDID("$FreeBSD$");
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <dev/pci/pcireg.h>
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#include <x86/iommu/intel_dmar.h>
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u_int
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@ -33,6 +33,8 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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@ -245,3 +247,10 @@ bus_dma_tag_destroy(bus_dma_tag_t dmat)
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return (tc->impl->tag_destroy(dmat));
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}
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#ifndef ACPI_DMAR
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bool
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bus_dma_dmar_set_buswide(device_t dev)
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{
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return (false);
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}
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#endif
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