- Use moderate gap counts listed in IEEE1394a.
- Simplify and correct the bus manager election process. - Check link_active when choosing cycle master. - Fix location of the cmr bit. Approved by: re (scottl)
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=114909
@ -113,9 +113,10 @@ static device_method_t firewire_methods[] = {
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};
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char linkspeed[7][0x10]={"S100","S200","S400","S800","S1600","S3200","Unknown"};
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#define MAX_GAPHOP 16
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u_int gap_cnt[] = {1, 1, 4, 6, 9, 12, 14, 17,
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20, 23, 25, 28, 31, 33, 36, 39, 42};
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/* IEEE-1394a Table C-2 Gap count as a function of hops*/
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#define MAX_GAPHOP 15
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u_int gap_cnt[] = { 5, 5, 7, 8, 10, 13, 16, 18,
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21, 24, 26, 29, 32, 35, 37, 40};
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extern struct cdevsw firewire_cdevsw;
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@ -1107,25 +1108,18 @@ void fw_sidrcv(struct firewire_comm* fc, u_int32_t *sid, u_int len)
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printf("\n");
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if (try_bmr && (fc->irm != -1) && (CSRARC(fc, BUS_MGR_ID) == 0x3f)) {
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if (fc->irm == ((CSRARC(fc, NODE_IDS) >> 16 ) & 0x3f)) {
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if (fc->irm == fc->nodeid) {
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fc->status = FWBUSMGRDONE;
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CSRARC(fc, BUS_MGR_ID) = fc->set_bmr(fc, fc->irm);
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fw_bmr(fc);
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} else {
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fc->status = FWBUSMGRELECT;
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callout_reset(&fc->bmr_callout, hz/8,
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(void *)fw_try_bmr, (void *)fc);
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}
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} else {
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} else
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fc->status = FWBUSMGRDONE;
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#if 0
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device_printf(fc->bdev, "BMR = %x\n",
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CSRARC(fc, BUS_MGR_ID));
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#endif
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}
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if(fc->irm == ((CSRARC(fc, NODE_IDS) >> 16 ) & 0x3f)){
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/* I am BMGR */
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fw_bmr(fc);
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}
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callout_reset(&fc->busprobe_callout, hz/4,
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(void *)fw_bus_probe, (void *)fc);
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}
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@ -1888,15 +1882,12 @@ fw_try_bmr_callback(struct fw_xfer *xfer)
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bmr = fc->nodeid;
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CSRARC(fc, BUS_MGR_ID) = fc->set_bmr(fc, bmr & 0x3f);
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device_printf(fc->bdev, "new bus manager %d ",
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CSRARC(fc, BUS_MGR_ID));
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if(bmr == fc->nodeid){
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printf("(me)\n");
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fw_bmr(fc);
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}else{
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printf("\n");
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}
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fw_xfer_free(xfer);
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fw_bmr(fc);
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return;
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error:
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device_printf(fc->bdev, "bus manager election failed\n");
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fw_xfer_free(xfer);
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}
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@ -2047,15 +2038,28 @@ fw_bmr(struct firewire_comm *fc)
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/* Check to see if the current root node is cycle master capable */
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self_id = &fc->topology_map->self_id[fc->max_node];
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if (fc->max_node > 0) {
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if (self_id->p0.contender)
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/* XXX check cmc bit of businfo block rather than contender */
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if (self_id->p0.link_active && self_id->p0.contender)
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cmstr = fc->max_node;
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else
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/* XXX shall we be cycle master? */
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else {
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device_printf(fc->bdev,
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"root node is not cycle master capable\n");
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/* XXX shall we be the cycle master? */
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cmstr = fc->nodeid;
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/* XXX bus reset? */
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/* XXX need bus reset */
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}
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} else
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cmstr = -1;
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/* If I am the bus manager, optimize gapcount */
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device_printf(fc->bdev, "bus manager %d ", CSRARC(fc, BUS_MGR_ID));
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if(CSRARC(fc, BUS_MGR_ID) != fc->nodeid) {
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/* We are not the bus manager */
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printf("\n");
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return(0);
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}
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printf("(me)\n");
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/* Optimize gapcount */
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if(fc->max_hop <= MAX_GAPHOP )
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fw_phy_config(fc, cmstr, gap_cnt[fc->max_hop]);
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/* If we are the cycle master, nothing to do */
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@ -2070,7 +2074,7 @@ fw_bmr(struct firewire_comm *fc)
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fwdev.status = FWDEVINIT;
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/* Set cmstr bit on the cycle master */
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fwmem_write_quad(&fwdev, NULL, 0/*spd*/,
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0xffff, 0xf0000000 | STATE_SET, htonl(1 << 16),
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0xffff, 0xf0000000 | STATE_SET, htonl(1 << 8),
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fw_asy_callback_free);
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return 0;
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