mlx5en: Implement support for internal queues, IQ.
Internal send queues are regular sendqueues which are reserved for WQE commands towards the hardware and firmware. These queues typically carry resync information for ongoing TLS RX connections and when changing schedule queues for rate limited connections. The internal queue, IQ, code is more or less a stripped down copy of the existing SQ managing code with exception of: 1) An optional single segment memory buffer which can be read or written as a whole by the hardware, may be provided. 2) An optional completion callback for all transmit operations, may be provided. 3) Does not support mbufs. MFC after: 1 week Sponsored by: NVIDIA Networking
This commit is contained in:
Hans Petter Selasky
parent
21228c67ab
commit
694263572f
@ -4927,6 +4927,8 @@ dev/mlx5/mlx5_en/mlx5_en_flow_table.c optional mlx5en pci inet inet6 \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_en/mlx5_en_hw_tls.c optional mlx5en pci inet inet6 \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_en/mlx5_en_iq.c optional mlx5en pci inet inet6 \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_en/mlx5_en_rx.c optional mlx5en pci inet inet6 \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_en/mlx5_en_rl.c optional mlx5en pci inet inet6 \
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@ -778,6 +778,52 @@ struct mlx5e_rq {
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struct mlx5e_channel *channel;
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} __aligned(MLX5E_CACHELINE_SIZE);
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typedef void (mlx5e_iq_callback_t)(void *arg);
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struct mlx5e_iq_data {
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bus_dmamap_t dma_map;
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mlx5e_iq_callback_t *callback;
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void *arg;
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volatile s32 *p_refcount; /* in use refcount, if any */
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u32 num_wqebbs;
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u32 dma_sync;
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};
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struct mlx5e_iq {
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/* persistant fields */
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struct mtx lock;
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struct mtx comp_lock;
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int db_inhibit;
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/* data path */
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#define mlx5e_iq_zero_start dma_tag
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bus_dma_tag_t dma_tag;
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u16 cc; /* consumer counter */
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u16 pc __aligned(MLX5E_CACHELINE_SIZE);
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u16 running;
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union {
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u32 d32[2];
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u64 d64;
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} doorbell;
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struct mlx5e_cq cq;
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/* pointers to per request info: write@xmit, read@completion */
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struct mlx5e_iq_data *data;
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/* read only */
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struct mlx5_wq_cyc wq;
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void __iomem *uar_map;
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u32 sqn;
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u32 mkey_be;
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/* control path */
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5e_priv *priv;
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};
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struct mlx5e_sq_mbuf {
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bus_dmamap_t dma_map;
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struct mbuf *mbuf;
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@ -873,6 +919,7 @@ struct mlx5e_channel {
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struct m_snd_tag tag;
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struct mlx5_sq_bfreg bfreg;
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struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
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struct mlx5e_iq iq;
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struct mlx5e_priv *priv;
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struct completion completion;
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int ix;
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@ -1223,4 +1270,14 @@ int mlx5e_update_buf_lossy(struct mlx5e_priv *priv);
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int mlx5e_fec_update(struct mlx5e_priv *priv);
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int mlx5e_hw_temperature_update(struct mlx5e_priv *priv);
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/* Internal Queue, IQ, API functions */
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void mlx5e_iq_send_nop(struct mlx5e_iq *, u32);
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int mlx5e_iq_open(struct mlx5e_channel *, struct mlx5e_sq_param *, struct mlx5e_cq_param *, struct mlx5e_iq *);
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void mlx5e_iq_close(struct mlx5e_iq *);
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void mlx5e_iq_static_init(struct mlx5e_iq *);
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void mlx5e_iq_static_destroy(struct mlx5e_iq *);
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void mlx5e_iq_notify_hw(struct mlx5e_iq *);
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int mlx5e_iq_get_producer_index(struct mlx5e_iq *);
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void mlx5e_iq_load_memory_single(struct mlx5e_iq *, u16, void *, size_t, u64 *, u32);
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#endif /* _MLX5_EN_H_ */
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524
sys/dev/mlx5/mlx5_en/mlx5_en_iq.c
Normal file
524
sys/dev/mlx5/mlx5_en/mlx5_en_iq.c
Normal file
@ -0,0 +1,524 @@
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/*-
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* Copyright (c) 2021 NVIDIA corporation & affiliates. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* The internal queue, IQ, code is more or less a stripped down copy
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* of the existing SQ managing code with exception of:
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*
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* - an optional single segment memory buffer which can be read or
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* written as a whole by the hardware, may be provided.
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*
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* - an optional completion callback for all transmit operations, may
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* be provided.
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*
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* - does not support mbufs.
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*/
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#include <dev/mlx5/mlx5_en/en.h>
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static void
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mlx5e_iq_poll(struct mlx5e_iq *iq, int budget)
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{
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const struct mlx5_cqe64 *cqe;
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u16 ci;
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u16 iqcc;
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/*
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* iq->cc must be updated only after mlx5_cqwq_update_db_record(),
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* otherwise a cq overrun may occur
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*/
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iqcc = iq->cc;
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while (budget-- > 0) {
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cqe = mlx5e_get_cqe(&iq->cq);
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if (!cqe)
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break;
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mlx5_cqwq_pop(&iq->cq.wq);
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ci = iqcc & iq->wq.sz_m1;
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if (likely(iq->data[ci].dma_sync != 0)) {
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/* make sure data written by hardware is visible to CPU */
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bus_dmamap_sync(iq->dma_tag, iq->data[ci].dma_map, iq->data[ci].dma_sync);
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bus_dmamap_unload(iq->dma_tag, iq->data[ci].dma_map);
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iq->data[ci].dma_sync = 0;
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}
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if (likely(iq->data[ci].callback != NULL)) {
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iq->data[ci].callback(iq->data[ci].arg);
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iq->data[ci].callback = NULL;
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}
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if (unlikely(iq->data[ci].p_refcount != NULL)) {
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atomic_add_int(iq->data[ci].p_refcount, -1);
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iq->data[ci].p_refcount = NULL;
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}
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iqcc += iq->data[ci].num_wqebbs;
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}
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mlx5_cqwq_update_db_record(&iq->cq.wq);
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/* Ensure cq space is freed before enabling more cqes */
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atomic_thread_fence_rel();
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iq->cc = iqcc;
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}
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static void
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mlx5e_iq_completion(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused)
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{
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struct mlx5e_iq *iq = container_of(mcq, struct mlx5e_iq, cq.mcq);
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mtx_lock(&iq->comp_lock);
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mlx5e_iq_poll(iq, MLX5E_BUDGET_MAX);
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mlx5e_cq_arm(&iq->cq, MLX5_GET_DOORBELL_LOCK(&iq->priv->doorbell_lock));
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mtx_unlock(&iq->comp_lock);
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}
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void
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mlx5e_iq_send_nop(struct mlx5e_iq *iq, u32 ds_cnt)
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{
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u16 pi = iq->pc & iq->wq.sz_m1;
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struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&iq->wq, pi);
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mtx_assert(&iq->lock, MA_OWNED);
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memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
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wqe->ctrl.opmod_idx_opcode = cpu_to_be32((iq->pc << 8) | MLX5_OPCODE_NOP);
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wqe->ctrl.qpn_ds = cpu_to_be32((iq->sqn << 8) | ds_cnt);
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wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
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/* Copy data for doorbell */
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memcpy(iq->doorbell.d32, &wqe->ctrl, sizeof(iq->doorbell.d32));
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iq->data[pi].callback = NULL;
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iq->data[pi].arg = NULL;
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iq->data[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
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iq->data[pi].dma_sync = 0;
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iq->pc += iq->data[pi].num_wqebbs;
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}
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static void
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mlx5e_iq_free_db(struct mlx5e_iq *iq)
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{
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int wq_sz = mlx5_wq_cyc_get_size(&iq->wq);
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int x;
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for (x = 0; x != wq_sz; x++) {
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if (likely(iq->data[x].dma_sync != 0)) {
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bus_dmamap_unload(iq->dma_tag, iq->data[x].dma_map);
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iq->data[x].dma_sync = 0;
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}
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if (likely(iq->data[x].callback != NULL)) {
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iq->data[x].callback(iq->data[x].arg);
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iq->data[x].callback = NULL;
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}
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bus_dmamap_destroy(iq->dma_tag, iq->data[x].dma_map);
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}
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free(iq->data, M_MLX5EN);
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}
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static int
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mlx5e_iq_alloc_db(struct mlx5e_iq *iq)
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{
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int wq_sz = mlx5_wq_cyc_get_size(&iq->wq);
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int err;
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int x;
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iq->data = malloc_domainset(wq_sz * sizeof(iq->data[0]), M_MLX5EN,
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mlx5_dev_domainset(iq->priv->mdev), M_WAITOK | M_ZERO);
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/* Create DMA descriptor maps */
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for (x = 0; x != wq_sz; x++) {
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err = -bus_dmamap_create(iq->dma_tag, 0, &iq->data[x].dma_map);
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if (err != 0) {
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while (x--)
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bus_dmamap_destroy(iq->dma_tag, iq->data[x].dma_map);
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free(iq->data, M_MLX5EN);
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return (err);
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}
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}
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return (0);
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}
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static int
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mlx5e_iq_create(struct mlx5e_channel *c,
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struct mlx5e_sq_param *param,
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struct mlx5e_iq *iq)
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{
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struct mlx5e_priv *priv = c->priv;
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struct mlx5_core_dev *mdev = priv->mdev;
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void *sqc = param->sqc;
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void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
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int err;
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/* Create DMA descriptor TAG */
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if ((err = -bus_dma_tag_create(
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bus_get_dma_tag(mdev->pdev->dev.bsddev),
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1, /* any alignment */
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0, /* no boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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PAGE_SIZE, /* maxsize */
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1, /* nsegments */
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PAGE_SIZE, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockfuncarg */
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&iq->dma_tag)))
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goto done;
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iq->mkey_be = cpu_to_be32(priv->mr.key);
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iq->priv = priv;
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err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq,
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&iq->wq, &iq->wq_ctrl);
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if (err)
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goto err_free_dma_tag;
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iq->wq.db = &iq->wq.db[MLX5_SND_DBR];
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err = mlx5e_iq_alloc_db(iq);
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if (err)
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goto err_iq_wq_destroy;
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return (0);
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err_iq_wq_destroy:
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mlx5_wq_destroy(&iq->wq_ctrl);
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err_free_dma_tag:
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bus_dma_tag_destroy(iq->dma_tag);
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done:
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return (err);
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}
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static void
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mlx5e_iq_destroy(struct mlx5e_iq *iq)
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{
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mlx5e_iq_free_db(iq);
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mlx5_wq_destroy(&iq->wq_ctrl);
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bus_dma_tag_destroy(iq->dma_tag);
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}
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static int
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mlx5e_iq_enable(struct mlx5e_iq *iq, struct mlx5e_sq_param *param,
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const struct mlx5_sq_bfreg *bfreg, int tis_num)
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{
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void *in;
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void *sqc;
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void *wq;
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int inlen;
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int err;
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u8 ts_format;
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inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
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sizeof(u64) * iq->wq_ctrl.buf.npages;
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in = mlx5_vzalloc(inlen);
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if (in == NULL)
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return (-ENOMEM);
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iq->uar_map = bfreg->map;
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ts_format = mlx5_get_sq_default_ts(iq->priv->mdev);
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sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
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wq = MLX5_ADDR_OF(sqc, sqc, wq);
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memcpy(sqc, param->sqc, sizeof(param->sqc));
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MLX5_SET(sqc, sqc, tis_num_0, tis_num);
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MLX5_SET(sqc, sqc, cqn, iq->cq.mcq.cqn);
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MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
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MLX5_SET(sqc, sqc, ts_format, ts_format);
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MLX5_SET(sqc, sqc, tis_lst_sz, 1);
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MLX5_SET(sqc, sqc, flush_in_error_en, 1);
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MLX5_SET(sqc, sqc, allow_swp, 1);
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MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
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MLX5_SET(wq, wq, uar_page, bfreg->index);
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MLX5_SET(wq, wq, log_wq_pg_sz, iq->wq_ctrl.buf.page_shift -
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PAGE_SHIFT);
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MLX5_SET64(wq, wq, dbr_addr, iq->wq_ctrl.db.dma);
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mlx5_fill_page_array(&iq->wq_ctrl.buf,
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(__be64 *) MLX5_ADDR_OF(wq, wq, pas));
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err = mlx5_core_create_sq(iq->priv->mdev, in, inlen, &iq->sqn);
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kvfree(in);
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return (err);
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}
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static int
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mlx5e_iq_modify(struct mlx5e_iq *iq, int curr_state, int next_state)
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{
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void *in;
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void *sqc;
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int inlen;
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int err;
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inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
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in = mlx5_vzalloc(inlen);
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if (in == NULL)
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return (-ENOMEM);
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sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
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MLX5_SET(modify_sq_in, in, sqn, iq->sqn);
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MLX5_SET(modify_sq_in, in, sq_state, curr_state);
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MLX5_SET(sqc, sqc, state, next_state);
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err = mlx5_core_modify_sq(iq->priv->mdev, in, inlen);
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kvfree(in);
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return (err);
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}
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static void
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mlx5e_iq_disable(struct mlx5e_iq *iq)
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{
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mlx5_core_destroy_sq(iq->priv->mdev, iq->sqn);
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}
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int
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mlx5e_iq_open(struct mlx5e_channel *c,
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struct mlx5e_sq_param *sq_param,
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struct mlx5e_cq_param *cq_param,
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struct mlx5e_iq *iq)
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{
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int err;
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err = mlx5e_open_cq(c->priv, cq_param, &iq->cq,
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&mlx5e_iq_completion, c->ix);
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if (err)
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return (err);
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err = mlx5e_iq_create(c, sq_param, iq);
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if (err)
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goto err_close_cq;
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err = mlx5e_iq_enable(iq, sq_param, &c->bfreg, c->priv->tisn[0]);
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if (err)
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goto err_destroy_sq;
|
||||
|
||||
err = mlx5e_iq_modify(iq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
|
||||
if (err)
|
||||
goto err_disable_sq;
|
||||
|
||||
WRITE_ONCE(iq->running, 1);
|
||||
|
||||
return (0);
|
||||
|
||||
err_disable_sq:
|
||||
mlx5e_iq_disable(iq);
|
||||
err_destroy_sq:
|
||||
mlx5e_iq_destroy(iq);
|
||||
err_close_cq:
|
||||
mlx5e_close_cq(&iq->cq);
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
static void
|
||||
mlx5e_iq_drain(struct mlx5e_iq *iq)
|
||||
{
|
||||
struct mlx5_core_dev *mdev = iq->priv->mdev;
|
||||
|
||||
/*
|
||||
* Check if already stopped.
|
||||
*
|
||||
* NOTE: Serialization of this function is managed by the
|
||||
* caller ensuring the priv's state lock is locked or in case
|
||||
* of rate limit support, a single thread manages drain and
|
||||
* resume of SQs. The "running" variable can therefore safely
|
||||
* be read without any locks.
|
||||
*/
|
||||
if (READ_ONCE(iq->running) == 0)
|
||||
return;
|
||||
|
||||
/* don't put more packets into the SQ */
|
||||
WRITE_ONCE(iq->running, 0);
|
||||
|
||||
/* wait till SQ is empty or link is down */
|
||||
mtx_lock(&iq->lock);
|
||||
while (iq->cc != iq->pc &&
|
||||
(iq->priv->media_status_last & IFM_ACTIVE) != 0 &&
|
||||
mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
|
||||
pci_channel_offline(mdev->pdev) == 0) {
|
||||
mtx_unlock(&iq->lock);
|
||||
msleep(1);
|
||||
iq->cq.mcq.comp(&iq->cq.mcq, NULL);
|
||||
mtx_lock(&iq->lock);
|
||||
}
|
||||
mtx_unlock(&iq->lock);
|
||||
|
||||
/* error out remaining requests */
|
||||
(void) mlx5e_iq_modify(iq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
|
||||
|
||||
/* wait till SQ is empty */
|
||||
mtx_lock(&iq->lock);
|
||||
while (iq->cc != iq->pc &&
|
||||
mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
|
||||
pci_channel_offline(mdev->pdev) == 0) {
|
||||
mtx_unlock(&iq->lock);
|
||||
msleep(1);
|
||||
iq->cq.mcq.comp(&iq->cq.mcq, NULL);
|
||||
mtx_lock(&iq->lock);
|
||||
}
|
||||
mtx_unlock(&iq->lock);
|
||||
}
|
||||
|
||||
void
|
||||
mlx5e_iq_close(struct mlx5e_iq *iq)
|
||||
{
|
||||
mlx5e_iq_drain(iq);
|
||||
mlx5e_iq_disable(iq);
|
||||
mlx5e_iq_destroy(iq);
|
||||
mlx5e_close_cq(&iq->cq);
|
||||
}
|
||||
|
||||
void
|
||||
mlx5e_iq_static_init(struct mlx5e_iq *iq)
|
||||
{
|
||||
mtx_init(&iq->lock, "mlx5iq",
|
||||
MTX_NETWORK_LOCK " IQ", MTX_DEF);
|
||||
mtx_init(&iq->comp_lock, "mlx5iq_comp",
|
||||
MTX_NETWORK_LOCK " IQ COMP", MTX_DEF);
|
||||
}
|
||||
|
||||
void
|
||||
mlx5e_iq_static_destroy(struct mlx5e_iq *iq)
|
||||
{
|
||||
mtx_destroy(&iq->lock);
|
||||
mtx_destroy(&iq->comp_lock);
|
||||
}
|
||||
|
||||
void
|
||||
mlx5e_iq_notify_hw(struct mlx5e_iq *iq)
|
||||
{
|
||||
mtx_assert(&iq->lock, MA_OWNED);
|
||||
|
||||
/* Check if we need to write the doorbell */
|
||||
if (unlikely(iq->db_inhibit != 0 || iq->doorbell.d64 == 0))
|
||||
return;
|
||||
|
||||
/* Ensure wqe is visible to device before updating doorbell record */
|
||||
wmb();
|
||||
|
||||
*iq->wq.db = cpu_to_be32(iq->pc);
|
||||
|
||||
/*
|
||||
* Ensure the doorbell record is visible to device before ringing
|
||||
* the doorbell:
|
||||
*/
|
||||
wmb();
|
||||
|
||||
mlx5_write64(iq->doorbell.d32, iq->uar_map,
|
||||
MLX5_GET_DOORBELL_LOCK(&iq->priv->doorbell_lock));
|
||||
|
||||
iq->doorbell.d64 = 0;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
mlx5e_iq_has_room_for(struct mlx5e_iq *iq, u16 n)
|
||||
{
|
||||
u16 cc = iq->cc;
|
||||
u16 pc = iq->pc;
|
||||
|
||||
return ((iq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
|
||||
}
|
||||
|
||||
int
|
||||
mlx5e_iq_get_producer_index(struct mlx5e_iq *iq)
|
||||
{
|
||||
u16 pi;
|
||||
|
||||
mtx_assert(&iq->lock, MA_OWNED);
|
||||
|
||||
if (unlikely(iq->running == 0))
|
||||
return (-1);
|
||||
if (unlikely(!mlx5e_iq_has_room_for(iq, 2 * MLX5_SEND_WQE_MAX_WQEBBS)))
|
||||
return (-1);
|
||||
|
||||
/* Align IQ edge with NOPs to avoid WQE wrap around */
|
||||
pi = ((~iq->pc) & iq->wq.sz_m1);
|
||||
if (unlikely(pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1))) {
|
||||
/* Send one multi NOP message instead of many */
|
||||
mlx5e_iq_send_nop(iq, (pi + 1) * MLX5_SEND_WQEBB_NUM_DS);
|
||||
pi = ((~iq->pc) & iq->wq.sz_m1);
|
||||
if (unlikely(pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)))
|
||||
return (-1);
|
||||
}
|
||||
return (iq->pc & iq->wq.sz_m1);
|
||||
}
|
||||
|
||||
static void
|
||||
mlx5e_iq_load_memory_cb(void *arg, bus_dma_segment_t *segs,
|
||||
int nseg, int error)
|
||||
{
|
||||
u64 *pdma_address = arg;
|
||||
|
||||
if (unlikely(error || nseg != 1))
|
||||
panic("mlx5e_iq_load_memory_cb: error=%d nseg=%d", error, nseg);
|
||||
|
||||
*pdma_address = segs[0].ds_addr;
|
||||
}
|
||||
|
||||
CTASSERT(BUS_DMASYNC_POSTREAD != 0);
|
||||
CTASSERT(BUS_DMASYNC_POSTWRITE != 0);
|
||||
|
||||
void
|
||||
mlx5e_iq_load_memory_single(struct mlx5e_iq *iq, u16 pi, void *buffer, size_t size,
|
||||
u64 *pdma_address, u32 dma_sync)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = bus_dmamap_load(iq->dma_tag, iq->data[pi].dma_map, buffer, size,
|
||||
&mlx5e_iq_load_memory_cb, pdma_address, BUS_DMA_NOWAIT);
|
||||
if (unlikely(error))
|
||||
panic("mlx5e_iq_load_memory: error=%d buffer=%p size=%zd", error, buffer, size);
|
||||
|
||||
switch (dma_sync) {
|
||||
case BUS_DMASYNC_PREREAD:
|
||||
iq->data[pi].dma_sync = BUS_DMASYNC_POSTREAD;
|
||||
break;
|
||||
case BUS_DMASYNC_PREWRITE:
|
||||
iq->data[pi].dma_sync = BUS_DMASYNC_POSTWRITE;
|
||||
break;
|
||||
default:
|
||||
panic("mlx5e_iq_load_memory_single: Invalid DMA sync operation(%d)", dma_sync);
|
||||
}
|
||||
|
||||
/* make sure data in buffer is visible to hardware */
|
||||
bus_dmamap_sync(iq->dma_tag, iq->data[pi].dma_map, dma_sync);
|
||||
}
|
||||
@ -2205,6 +2205,8 @@ mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
|
||||
|
||||
callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
|
||||
}
|
||||
|
||||
mlx5e_iq_static_init(&c->iq);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -2238,6 +2240,8 @@ mlx5e_chan_static_destroy(struct mlx5e_channel *c)
|
||||
mtx_destroy(&c->sq[tc].lock);
|
||||
mtx_destroy(&c->sq[tc].comp_lock);
|
||||
}
|
||||
|
||||
mlx5e_iq_static_destroy(&c->iq);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -2252,6 +2256,7 @@ mlx5e_open_channel(struct mlx5e_priv *priv,
|
||||
MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
|
||||
for (i = 0; i != priv->num_tc; i++)
|
||||
MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
|
||||
MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start);
|
||||
|
||||
/* open transmit completion queue */
|
||||
err = mlx5e_open_tx_cqs(c, cparam);
|
||||
@ -2268,10 +2273,14 @@ mlx5e_open_channel(struct mlx5e_priv *priv,
|
||||
if (err)
|
||||
goto err_close_rx_cq;
|
||||
|
||||
err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
|
||||
err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq);
|
||||
if (err)
|
||||
goto err_close_sqs;
|
||||
|
||||
err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
|
||||
if (err)
|
||||
goto err_close_iq;
|
||||
|
||||
/* poll receive queue initially */
|
||||
NET_EPOCH_ENTER(et);
|
||||
c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
|
||||
@ -2279,6 +2288,9 @@ mlx5e_open_channel(struct mlx5e_priv *priv,
|
||||
|
||||
return (0);
|
||||
|
||||
err_close_iq:
|
||||
mlx5e_iq_close(&c->iq);
|
||||
|
||||
err_close_sqs:
|
||||
mlx5e_close_sqs_wait(c);
|
||||
|
||||
@ -2302,6 +2314,7 @@ static void
|
||||
mlx5e_close_channel_wait(struct mlx5e_channel *c)
|
||||
{
|
||||
mlx5e_close_rq_wait(&c->rq);
|
||||
mlx5e_iq_close(&c->iq);
|
||||
mlx5e_close_sqs_wait(c);
|
||||
mlx5e_close_tx_cqs(c);
|
||||
}
|
||||
|
||||
@ -591,6 +591,10 @@ mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused)
|
||||
mtx_unlock(&c->sq[j].lock);
|
||||
}
|
||||
|
||||
mtx_lock(&c->iq.lock);
|
||||
c->iq.db_inhibit++;
|
||||
mtx_unlock(&c->iq.lock);
|
||||
|
||||
mtx_lock(&rq->mtx);
|
||||
|
||||
/*
|
||||
@ -621,4 +625,9 @@ mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused)
|
||||
mlx5e_tx_notify_hw(c->sq + j, true);
|
||||
mtx_unlock(&c->sq[j].lock);
|
||||
}
|
||||
|
||||
mtx_lock(&c->iq.lock);
|
||||
c->iq.db_inhibit--;
|
||||
mlx5e_iq_notify_hw(&c->iq);
|
||||
mtx_unlock(&c->iq.lock);
|
||||
}
|
||||
|
||||
@ -9,6 +9,7 @@ mlx5_en_main.c \
|
||||
mlx5_en_tx.c \
|
||||
mlx5_en_flow_table.c \
|
||||
mlx5_en_hw_tls.c \
|
||||
mlx5_en_iq.c \
|
||||
mlx5_en_rx.c \
|
||||
mlx5_en_rl.c \
|
||||
mlx5_en_txrx.c \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user