- Added few more Intel HDA ids (ICH 6/7) which does have backward
compatible AC97 codec. - As the driver supports so many variants, create a table ids for ease of probing and maintenance. Submitted by: yongari Reviewed/Tested by: multimedia@ - From luigi: The code to compute fragment sizes in the ich driver almost invariably ends up using the full buffer available, no matter how the user specifies fragment size and number. With audio telephony (8khz, 16bit-stereo) and the 16k buffer size this results in an unbearable 500ms delay. This patch makes sure that we never use more than 4 fragments, (i don't think we need more unless there are huge interrupt servicing latencies), and obey to the requested fragment size, so that latency is acceptable. Based on this (and after much regression tests), I can conclude that this driver works best with 2 fragments, thus solving various long standing issues of ICH driver not capable to flush or play short files perfectly. Suggested by: luigi (the idea of smaller fragments) - MPSAFE conversion. Approved by: netchild (mentor)
This commit is contained in:
Ariff Abdullah
parent
0ae68fd446
commit
6a728ce536
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=152420
@ -41,11 +41,81 @@ SND_DECLARE_FILE("$FreeBSD$");
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#define ICH_DEFAULT_BUFSZ 16384
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#define ICH_MAX_BUFSZ 65536
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#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
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#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
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#define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */
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#define I6300ESBID 0x25a68086 /* 6300ESB needs to be treated as ICH4 */
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#define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */
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#define INTEL_VENDORID 0x8086
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#define SIS_VENDORID 0x1039
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#define NVIDIA_VENDORID 0x10de
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#define AMD_VENDORID 0x1022
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#define INTEL_82440MX 0x7195
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#define INTEL_82801AA 0x2415
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#define INTEL_82801AB 0x2425
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#define INTEL_82801BA 0x2445
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#define INTEL_82801CA 0x2485
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#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
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#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
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#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
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#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
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#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
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#define SIS_7012 0x7012 /* SiS 7012 needs special handling */
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#define NVIDIA_NFORCE 0x01b1
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#define NVIDIA_NFORCE2 0x006a
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#define NVIDIA_NFORCE2_400 0x008a
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#define NVIDIA_NFORCE3 0x00da
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#define NVIDIA_NFORCE3_250 0x00ea
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#define NVIDIA_NFORCE4 0x0059
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#define AMD_768 0x7445
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#define AMD_8111 0x746d
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#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
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#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
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#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
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static const struct ich_type {
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uint16_t vendor;
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uint16_t devid;
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uint32_t options;
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#define PROBE_LOW 0x01
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char *name;
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} ich_devs[] = {
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{ INTEL_VENDORID, INTEL_82440MX, 0,
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"Intel 440MX" },
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{ INTEL_VENDORID, INTEL_82801AA, 0,
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"Intel ICH (82801AA)" },
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{ INTEL_VENDORID, INTEL_82801AB, 0,
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"Intel ICH (82801AB)" },
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{ INTEL_VENDORID, INTEL_82801BA, 0,
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"Intel ICH2 (82801BA)" },
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{ INTEL_VENDORID, INTEL_82801CA, 0,
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"Intel ICH3 (82801CA)" },
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{ INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
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"Intel ICH4 (82801DB)" },
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{ INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
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"Intel ICH5 (82801EB)" },
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{ INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
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"Intel 6300ESB" },
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{ INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
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"Intel ICH6 (82801FB)" },
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{ INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
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"Intel ICH7 (82801GB)" },
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{ SIS_VENDORID, SIS_7012, 0,
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"SiS 7012" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
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"nVidia nForce" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
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"nVidia nForce2" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
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"nVidia nForce2 400" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
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"nVidia nForce3" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
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"nVidia nForce3 250" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
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"nVidia nForce4" },
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{ AMD_VENDORID, AMD_768, 0,
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"AMD-768" },
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{ AMD_VENDORID, AMD_8111, 0,
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"AMD-8111" }
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};
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/* buffer descriptor */
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struct ich_desc {
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@ -93,6 +163,9 @@ struct sc_info {
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bus_addr_t desc_addr;
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struct intr_config_hook intrhook;
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int use_intrhook;
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uint16_t vendor;
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uint16_t devid;
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struct mtx *ich_lock;
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};
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/* -------------------------------------------------------------------- */
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@ -106,7 +179,7 @@ static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
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/* -------------------------------------------------------------------- */
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/* Hardware */
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static u_int32_t
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static __inline u_int32_t
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ich_rd(struct sc_info *sc, int regno, int size)
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{
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switch (size) {
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@ -121,7 +194,7 @@ ich_rd(struct sc_info *sc, int regno, int size)
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}
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}
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static void
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static __inline void
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ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
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{
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switch (size) {
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@ -190,15 +263,15 @@ AC97_DECLARE(ich_ac97);
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static void
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ich_filldtbl(struct sc_chinfo *ch)
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{
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struct sc_info *sc = ch->parent;
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u_int32_t base;
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int i;
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base = sndbuf_getbufaddr(ch->buffer);
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ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
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if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
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ch->blkcnt = 2;
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ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
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}
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if (ch->blksz > sc->bufsz / ch->blkcnt)
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ch->blksz = sc->bufsz / ch->blkcnt;
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sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz);
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ch->blksz = sndbuf_getblksz(ch->buffer);
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for (i = 0; i < ICH_DTBL_LENGTH; i++) {
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ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
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@ -249,6 +322,7 @@ ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *
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struct sc_chinfo *ch;
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unsigned int num;
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ICH_LOCK(sc);
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num = sc->chnum++;
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ch = &sc->ch[num];
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ch->num = num;
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@ -288,10 +362,13 @@ ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *
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return NULL;
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}
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ICH_UNLOCK(sc);
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if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0)
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return NULL;
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
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ICH_UNLOCK(sc);
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return ch;
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}
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@ -309,16 +386,20 @@ ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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struct sc_info *sc = ch->parent;
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if (ch->spdreg) {
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int r;
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int r, ac97rate;
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ICH_LOCK(sc);
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if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
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sc->ac97rate = 48000;
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r = (speed * 48000) / sc->ac97rate;
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ac97rate = sc->ac97rate;
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ICH_UNLOCK(sc);
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r = (speed * 48000) / ac97rate;
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/*
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* Cast the return value of ac97_setrate() to u_int so that
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* the math don't overflow into the negative range.
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*/
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ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
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sc->ac97rate) / 48000;
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ac97rate) / 48000;
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} else {
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ch->spd = 48000;
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}
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@ -333,7 +414,9 @@ ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
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ch->blksz = blocksize;
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ich_filldtbl(ch);
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
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ICH_UNLOCK(sc);
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return ch->blksz;
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}
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@ -347,12 +430,16 @@ ichchan_trigger(kobj_t obj, void *data, int go)
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switch (go) {
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case PCMTRIG_START:
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ch->run = 1;
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
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ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
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ICH_UNLOCK(sc);
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break;
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case PCMTRIG_ABORT:
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ICH_LOCK(sc);
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ich_resetchan(sc, ch->num);
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ICH_UNLOCK(sc);
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ch->run = 0;
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break;
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}
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@ -366,7 +453,9 @@ ichchan_getptr(kobj_t obj, void *data)
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struct sc_info *sc = ch->parent;
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u_int32_t pos;
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ICH_LOCK(sc);
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ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
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ICH_UNLOCK(sc);
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pos = ch->civ * ch->blksz;
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@ -404,6 +493,7 @@ ich_intr(void *p)
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u_int32_t cbi, lbi, lvi, st, gs;
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int i;
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ICH_LOCK(sc);
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gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
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if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
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/* Clear resume interrupt(s) - nothing doing with them */
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@ -422,8 +512,11 @@ ich_intr(void *p)
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st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
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if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
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/* block complete - update buffer */
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if (ch->run)
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if (ch->run) {
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ICH_UNLOCK(sc);
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chn_intr(ch->channel);
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ICH_LOCK(sc);
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}
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lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
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cbi = ch->civ % ch->blkcnt;
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if (cbi == 0)
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@ -444,6 +537,7 @@ ich_intr(void *p)
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(sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
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st, 2);
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}
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ICH_UNLOCK(sc);
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if (gs != 0) {
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device_printf(sc->dev,
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"Unhandled interrupt, gs_intr = %x\n", gs);
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@ -586,10 +680,10 @@ ich_init(struct sc_info *sc)
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if ((stat & ICH_GLOB_STA_PCR) == 0) {
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/* ICH4/ICH5 may fail when busmastering is enabled. Continue */
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if ((pci_get_devid(sc->dev) != ICH4ID) &&
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(pci_get_devid(sc->dev) != ICH5ID) &&
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(pci_get_devid(sc->dev) != I6300ESBID) &&
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(pci_get_devid(sc->dev) != ICH6ID)) {
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if (sc->vendor == INTEL_VENDORID && (
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sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
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sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
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sc->devid == INTEL_82801GB)) {
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return ENXIO;
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}
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}
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@ -616,104 +710,47 @@ ich_init(struct sc_info *sc)
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static int
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ich_pci_probe(device_t dev)
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{
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switch(pci_get_devid(dev)) {
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case 0x71958086:
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device_set_desc(dev, "Intel 443MX");
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return BUS_PROBE_DEFAULT;
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int i;
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uint16_t devid, vendor;
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case 0x24158086:
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device_set_desc(dev, "Intel ICH (82801AA)");
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return BUS_PROBE_DEFAULT;
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case 0x24258086:
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device_set_desc(dev, "Intel ICH (82801AB)");
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return BUS_PROBE_DEFAULT;
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case 0x24458086:
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device_set_desc(dev, "Intel ICH2 (82801BA)");
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return BUS_PROBE_DEFAULT;
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case 0x24858086:
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device_set_desc(dev, "Intel ICH3 (82801CA)");
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return BUS_PROBE_DEFAULT;
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case ICH4ID:
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device_set_desc(dev, "Intel ICH4 (82801DB)");
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return BUS_PROBE_LOW_PRIORITY;
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case ICH5ID:
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device_set_desc(dev, "Intel ICH5 (82801EB)");
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return BUS_PROBE_LOW_PRIORITY;
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case I6300ESBID:
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device_set_desc(dev, "Intel 6300ESB");
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return BUS_PROBE_LOW_PRIORITY;
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case ICH6ID:
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device_set_desc(dev, "Intel ICH6 (82801FB)");
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return BUS_PROBE_LOW_PRIORITY;
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case SIS7012ID:
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device_set_desc(dev, "SiS 7012");
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return BUS_PROBE_DEFAULT;
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case 0x01b110de:
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device_set_desc(dev, "nVidia nForce");
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return BUS_PROBE_DEFAULT;
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case 0x006a10de:
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device_set_desc(dev, "nVidia nForce2");
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return BUS_PROBE_DEFAULT;
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case 0x008a10de:
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device_set_desc(dev, "nVidia nForce2 400");
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return BUS_PROBE_DEFAULT;
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case 0x00da10de:
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device_set_desc(dev, "nVidia nForce3");
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return BUS_PROBE_DEFAULT;
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case 0x00ea10de:
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device_set_desc(dev, "nVidia nForce3 250");
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return BUS_PROBE_DEFAULT;
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case 0x005910de:
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device_set_desc(dev, "nVidia nForce4");
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return BUS_PROBE_DEFAULT;
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case 0x74451022:
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device_set_desc(dev, "AMD-768");
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return BUS_PROBE_DEFAULT;
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case 0x746d1022:
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device_set_desc(dev, "AMD-8111");
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return BUS_PROBE_DEFAULT;
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default:
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return ENXIO;
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vendor = pci_get_vendor(dev);
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devid = pci_get_device(dev);
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for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) {
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if (vendor == ich_devs[i].vendor &&
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devid == ich_devs[i].devid) {
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device_set_desc(dev, ich_devs[i].name);
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/* allow a better driver to override us */
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if ((ich_devs[i].options & PROBE_LOW) != 0)
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return (BUS_PROBE_LOW_PRIORITY);
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return (BUS_PROBE_DEFAULT);
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}
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}
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return (ENXIO);
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}
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static int
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ich_pci_attach(device_t dev)
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{
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u_int16_t extcaps;
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uint16_t devid, vendor;
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struct sc_info *sc;
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char status[SND_STATUSLEN];
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if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
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if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
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device_printf(dev, "cannot allocate softc\n");
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return ENXIO;
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}
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bzero(sc, sizeof(*sc));
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sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
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sc->dev = dev;
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vendor = sc->vendor = pci_get_vendor(dev);
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devid = sc->devid = pci_get_device(dev);
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/*
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* The SiS 7012 register set isn't quite like the standard ich.
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* There really should be a general "quirks" mechanism.
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*/
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if (pci_get_devid(dev) == SIS7012ID) {
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if (vendor == SIS_VENDORID && devid == SIS_7012) {
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sc->swap_reg = 1;
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sc->sample_size = 1;
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} else {
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@ -728,7 +765,7 @@ ich_pci_attach(device_t dev)
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* but doing so will mess things up here. ich4 has enough new
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* features it warrants it's own driver.
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*/
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if (pci_get_devid(dev) == ICH4ID) {
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if (vendor == INTEL_VENDORID && devid == INTEL_82801DB) {
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pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
|
||||
}
|
||||
|
||||
@ -738,9 +775,9 @@ ich_pci_attach(device_t dev)
|
||||
*/
|
||||
pci_enable_busmaster(dev);
|
||||
|
||||
if (pci_get_devid(dev) == ICH5ID ||
|
||||
pci_get_devid(dev) == I6300ESBID ||
|
||||
pci_get_devid(dev) == ICH6ID) {
|
||||
if (vendor == INTEL_VENDORID && (devid == INTEL_82801EB ||
|
||||
devid == INTEL_6300ESB || devid == INTEL_82801FB ||
|
||||
devid == INTEL_82801GB)) {
|
||||
sc->nambarid = PCIR_MMBAR;
|
||||
sc->nabmbarid = PCIR_MBBAR;
|
||||
sc->regtype = SYS_RES_MEMORY;
|
||||
@ -768,7 +805,7 @@ ich_pci_attach(device_t dev)
|
||||
sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
|
||||
if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
|
||||
NULL, NULL, sc->bufsz, 1, 0x3ffff, 0,
|
||||
busdma_lock_mutex, &Giant, &sc->dmat) != 0) {
|
||||
NULL, NULL, &sc->dmat) != 0) {
|
||||
device_printf(dev, "unable to create dma tag\n");
|
||||
goto bad;
|
||||
}
|
||||
@ -776,7 +813,7 @@ ich_pci_attach(device_t dev)
|
||||
sc->irqid = 0;
|
||||
sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
|
||||
RF_ACTIVE | RF_SHAREABLE);
|
||||
if (!sc->irq || snd_setup_intr(dev, sc->irq, 0, ich_intr, sc, &sc->ih)) {
|
||||
if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
|
||||
device_printf(dev, "unable to map interrupt\n");
|
||||
goto bad;
|
||||
}
|
||||
@ -837,6 +874,8 @@ ich_pci_attach(device_t dev)
|
||||
if (sc->nabmbar)
|
||||
bus_release_resource(dev, sc->regtype,
|
||||
sc->nabmbarid, sc->nabmbar);
|
||||
if (sc->ich_lock)
|
||||
snd_mtxfree(sc->ich_lock);
|
||||
free(sc, M_DEVBUF);
|
||||
return ENXIO;
|
||||
}
|
||||
@ -857,6 +896,7 @@ ich_pci_detach(device_t dev)
|
||||
bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
|
||||
bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
|
||||
bus_dma_tag_destroy(sc->dmat);
|
||||
snd_mtxfree(sc->ich_lock);
|
||||
free(sc, M_DEVBUF);
|
||||
return 0;
|
||||
}
|
||||
@ -890,12 +930,16 @@ ich_pci_suspend(device_t dev)
|
||||
int i;
|
||||
|
||||
sc = pcm_getdevinfo(dev);
|
||||
ICH_LOCK(sc);
|
||||
for (i = 0 ; i < 3; i++) {
|
||||
sc->ch[i].run_save = sc->ch[i].run;
|
||||
if (sc->ch[i].run) {
|
||||
ICH_UNLOCK(sc);
|
||||
ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
|
||||
ICH_LOCK(sc);
|
||||
}
|
||||
}
|
||||
ICH_UNLOCK(sc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -913,9 +957,11 @@ ich_pci_resume(device_t dev)
|
||||
pci_enable_io(dev, SYS_RES_MEMORY);
|
||||
pci_enable_busmaster(dev);
|
||||
|
||||
ICH_LOCK(sc);
|
||||
/* Reinit audio device */
|
||||
if (ich_init(sc) == -1) {
|
||||
device_printf(dev, "unable to reinitialize the card\n");
|
||||
ICH_UNLOCK(sc);
|
||||
return ENXIO;
|
||||
}
|
||||
/* Reinit mixer */
|
||||
@ -923,17 +969,21 @@ ich_pci_resume(device_t dev)
|
||||
ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
|
||||
if (mixer_reinit(dev) == -1) {
|
||||
device_printf(dev, "unable to reinitialize the mixer\n");
|
||||
ICH_UNLOCK(sc);
|
||||
return ENXIO;
|
||||
}
|
||||
/* Re-start DMA engines */
|
||||
for (i = 0 ; i < 3; i++) {
|
||||
struct sc_chinfo *ch = &sc->ch[i];
|
||||
if (sc->ch[i].run_save) {
|
||||
ICH_UNLOCK(sc);
|
||||
ichchan_setblocksize(0, ch, ch->blksz);
|
||||
ichchan_setspeed(0, ch, ch->spd);
|
||||
ichchan_trigger(0, ch, PCMTRIG_START);
|
||||
ICH_LOCK(sc);
|
||||
}
|
||||
}
|
||||
ICH_UNLOCK(sc);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user