Remove support for ARMv6/v7 platform from elf_trampoline.
The elf_trampoline.c is not connected to build for ARMv6/v7 for long time and it uses outdated low level cpu functions. This blocks forthcoming cleanup of ARM code. MFC after: 3 weeks
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=325439
@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$");
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#include <machine/armreg.h>
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#include <machine/cpu.h>
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#if __ARM_ARCH >= 6
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#error "elf_trampline is not supported on ARMv6/v7 platforms"
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#endif
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extern char kernel_start[];
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extern char kernel_end[];
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@ -51,8 +54,6 @@ void __start(void);
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void __startC(unsigned r0, unsigned r1, unsigned r2, unsigned r3);
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extern unsigned int cpu_ident(void);
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extern void armv6_idcache_wbinv_all(void);
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extern void armv7_idcache_wbinv_all(void);
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extern void do_call(void *, void *, void *, int);
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#define GZ_HEAD 0xa
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@ -66,36 +67,23 @@ extern void fa526_idcache_wbinv_all(void);
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#elif defined(CPU_ARM9E)
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#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
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extern void armv5_ec_idcache_wbinv_all(void);
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#elif defined(CPU_ARM1176)
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#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
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#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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#define cpu_idcache_wbinv_all xscale_cache_purgeID
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extern void xscale_cache_purgeID(void);
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#elif defined(CPU_XSCALE_81342)
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#define cpu_idcache_wbinv_all xscalec3_cache_purgeID
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extern void xscalec3_cache_purgeID(void);
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#elif defined(CPU_MV_PJ4B)
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#if !defined(SOC_MV_ARMADAXP)
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#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
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extern void armv6_idcache_wbinv_all(void);
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#else
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#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all
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#endif
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#endif /* CPU_MV_PJ4B */
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#ifdef CPU_XSCALE_81342
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#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
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extern void xscalec3_l2cache_purge(void);
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#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
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extern void sheeva_l2cache_wbinv_all(void);
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#elif defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT)
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#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all
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#define cpu_l2cache_wbinv_all()
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#else
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#define cpu_l2cache_wbinv_all()
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#endif
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static void armadaxp_idcache_wbinv_all(void);
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int arm_picache_size;
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int arm_picache_line_size;
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@ -389,18 +377,6 @@ arm9_setup(void)
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arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
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}
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static void
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armadaxp_idcache_wbinv_all(void)
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{
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uint32_t feat;
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__asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat));
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if (feat & ARM_PFR0_THUMBEE_MASK)
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armv7_idcache_wbinv_all();
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else
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armv6_idcache_wbinv_all();
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}
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#ifdef KZIP
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static unsigned char *orig_input, *i_input, *i_output;
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