Add support for the Nuvoton NCT5104D.
Make it compile only for i386/amd64 for now as it's been tested there. It's quite possible it'll show up elsewhere and we can enable it for other architectures later. Tested: * PC Engines APU1C4 Submitted by: Daniel Wyatt <daniel@dewyatt.com> Reviewed by: adrian, loos Differential Revision: https://reviews.freebsd.org/D5389
This commit is contained in:
Adrian Chadd
parent
1ac0fb85bf
commit
6b7b2d80ed
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=297443
802
sys/dev/nctgpio/nctgpio.c
Normal file
802
sys/dev/nctgpio/nctgpio.c
Normal file
@ -0,0 +1,802 @@
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/*-
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* Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/*
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* Nuvoton GPIO driver.
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*
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/eventhandler.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <isa/isavar.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/gpio/gpiobusvar.h>
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#include "gpio_if.h"
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/*
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* Global configuration registers (CR).
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*/
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#define NCT_CR_LDN 0x07 /* Logical Device Number */
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#define NCT_CR_CHIP_ID 0x20 /* Chip ID */
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#define NCT_CR_CHIP_ID_H 0x20 /* Chip ID (high byte) */
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#define NCT_CR_CHIP_ID_L 0x21 /* Chip ID (low byte) */
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#define NCT_CR_OPT_1 0x26 /* Global Options (1) */
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/* Logical Device Numbers. */
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#define NCT_LDN_GPIO 0x07
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#define NCT_LDN_GPIO_CFG 0x08
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#define NCT_LDN_GPIO_MODE 0x0f
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/* Logical Device 7 */
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#define NCT_LD7_GPIO_ENABLE 0x30
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#define NCT_LD7_GPIO0_IOR 0xe0
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#define NCT_LD7_GPIO0_DAT 0xe1
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#define NCT_LD7_GPIO0_INV 0xe2
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#define NCT_LD7_GPIO0_DST 0xe3
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#define NCT_LD7_GPIO1_IOR 0xe4
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#define NCT_LD7_GPIO1_DAT 0xe5
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#define NCT_LD7_GPIO1_INV 0xe6
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#define NCT_LD7_GPIO1_DST 0xe7
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/* Logical Device F */
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#define NCT_LDF_GPIO0_OUTCFG 0xe0
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#define NCT_LDF_GPIO1_OUTCFG 0xe1
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#define NCT_EXTFUNC_ENTER 0x87
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#define NCT_EXTFUNC_EXIT 0xaa
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#define NCT_MAX_PIN 15
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#define NCT_IS_VALID_PIN(_p) ((_p) >= 0 && (_p) <= NCT_MAX_PIN)
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#define NCT_PIN_BIT(_p) (1 << ((_p) % 8))
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#define NCT_GPIO_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
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GPIO_PIN_INVIN | GPIO_PIN_INVOUT)
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struct nct_softc {
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device_t dev;
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device_t busdev;
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struct mtx mtx;
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struct resource *portres;
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int rid;
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struct gpio_pin pins[NCT_MAX_PIN];
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};
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#define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
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device_get_nameunit(dev), NULL, MTX_DEF)
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#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
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#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED)
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#define NCT_BARRIER_WRITE(_sc) \
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bus_barrier((_sc)->portres, 0, 2, BUS_SPACE_BARRIER_WRITE)
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#define NCT_BARRIER_READ_WRITE(_sc) \
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bus_barrier((_sc)->portres, 0, 2, \
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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static void ext_cfg_enter(struct nct_softc *);
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static void ext_cfg_exit(struct nct_softc *);
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/*
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* Potential Extended Function Enable Register addresses.
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* Same address as EFIR.
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*/
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uint8_t probe_addrs[] = {0x2e, 0x4e};
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struct nuvoton_vendor_device_id {
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uint16_t chip_id;
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const char * descr;
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} nct_devs[] = {
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{
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.chip_id = 0x1061,
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.descr = "Nuvoton NCT5104D",
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},
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{
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.chip_id = 0xc452,
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.descr = "Nuvoton NCT5104D (PC-Engines APU)",
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},
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};
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static void
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write_cfg_reg_1(struct nct_softc *sc, uint8_t reg, uint8_t value)
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{
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GPIO_ASSERT_LOCKED(sc);
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bus_write_1(sc->portres, 0, reg);
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NCT_BARRIER_WRITE(sc);
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bus_write_1(sc->portres, 1, value);
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NCT_BARRIER_WRITE(sc);
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}
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static uint8_t
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read_cfg_reg_1(struct nct_softc *sc, uint8_t reg)
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{
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uint8_t value;
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GPIO_ASSERT_LOCKED(sc);
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bus_write_1(sc->portres, 0, reg);
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NCT_BARRIER_READ_WRITE(sc);
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value = bus_read_1(sc->portres, 1);
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NCT_BARRIER_READ_WRITE(sc);
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return (value);
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}
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static uint16_t
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read_cfg_reg_2(struct nct_softc *sc, uint8_t reg)
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{
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uint16_t value;
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value = read_cfg_reg_1(sc, reg) << 8;
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value |= read_cfg_reg_1(sc, reg + 1);
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return (value);
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}
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/*
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* Enable extended function mode.
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*
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*/
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static void
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ext_cfg_enter(struct nct_softc *sc)
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{
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GPIO_ASSERT_LOCKED(sc);
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bus_write_1(sc->portres, 0, NCT_EXTFUNC_ENTER);
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NCT_BARRIER_WRITE(sc);
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bus_write_1(sc->portres, 0, NCT_EXTFUNC_ENTER);
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NCT_BARRIER_WRITE(sc);
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}
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/*
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* Disable extended function mode.
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*
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*/
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static void
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ext_cfg_exit(struct nct_softc *sc)
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{
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GPIO_ASSERT_LOCKED(sc);
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bus_write_1(sc->portres, 0, NCT_EXTFUNC_EXIT);
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NCT_BARRIER_WRITE(sc);
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}
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/*
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* Select a Logical Device.
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*/
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static void
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select_ldn(struct nct_softc *sc, uint8_t ldn)
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{
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write_cfg_reg_1(sc, NCT_CR_LDN, ldn);
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}
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/*
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* Get the GPIO Input/Output register address
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* for a pin.
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*/
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static uint8_t
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nct_ior_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_IOR;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_IOR;
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return (addr);
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}
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/*
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* Get the GPIO Data register address for a pin.
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*/
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static uint8_t
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nct_dat_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_DAT;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_DAT;
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return (addr);
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}
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/*
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* Get the GPIO Inversion register address
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* for a pin.
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*/
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static uint8_t
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nct_inv_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_INV;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_INV;
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return (addr);
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}
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/*
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* Get the GPIO Output Configuration/Mode
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* register address for a pin.
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*/
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static uint8_t
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nct_outcfg_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LDF_GPIO0_OUTCFG;
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if (pin_num > 7)
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addr = NCT_LDF_GPIO1_OUTCFG;
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return (addr);
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}
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/*
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* Set a pin to output mode.
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*/
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static void
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nct_set_pin_is_output(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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ior = read_cfg_reg_1(sc, reg);
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ior &= ~(NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, ior);
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}
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/*
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* Set a pin to input mode.
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*/
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static void
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nct_set_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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ior = read_cfg_reg_1(sc, reg);
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ior |= NCT_PIN_BIT(pin_num);
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write_cfg_reg_1(sc, reg, ior);
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}
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/*
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* Check whether a pin is configured as an input.
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*/
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static bool
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nct_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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ior = read_cfg_reg_1(sc, reg);
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return (ior & NCT_PIN_BIT(pin_num));
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}
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/*
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* Write a value to an output pin.
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*/
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static void
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nct_write_pin(struct nct_softc *sc, uint32_t pin_num, uint8_t data)
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{
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uint8_t reg;
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uint8_t value;
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reg = nct_dat_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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value = read_cfg_reg_1(sc, reg);
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if (data)
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value |= NCT_PIN_BIT(pin_num);
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else
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value &= ~(NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, value);
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}
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static bool
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nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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reg = nct_dat_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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return (read_cfg_reg_1(sc, reg) & NCT_PIN_BIT(pin_num));
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}
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static void
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nct_set_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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inv = read_cfg_reg_1(sc, reg);
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inv |= (NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, inv);
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}
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static void
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nct_set_pin_not_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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inv = read_cfg_reg_1(sc, reg);
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inv &= ~(NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, inv);
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}
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static bool
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nct_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO);
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inv = read_cfg_reg_1(sc, reg);
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return (inv & NCT_PIN_BIT(pin_num));
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}
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static void
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nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t outcfg;
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reg = nct_outcfg_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO_MODE);
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outcfg = read_cfg_reg_1(sc, reg);
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outcfg |= (NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, outcfg);
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}
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static void
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nct_set_pin_pushpull(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t outcfg;
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reg = nct_outcfg_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO_MODE);
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outcfg = read_cfg_reg_1(sc, reg);
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outcfg &= ~(NCT_PIN_BIT(pin_num));
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write_cfg_reg_1(sc, reg, outcfg);
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}
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static bool
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nct_pin_is_opendrain(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t outcfg;
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reg = nct_outcfg_addr(pin_num);
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select_ldn(sc, NCT_LDN_GPIO_MODE);
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outcfg = read_cfg_reg_1(sc, reg);
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return (outcfg & NCT_PIN_BIT(pin_num));
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}
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static void
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nct_identify(driver_t *driver, device_t parent)
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{
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if (device_find_child(parent, driver->name, 0) != NULL)
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return;
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BUS_ADD_CHILD(parent, 0, driver->name, 0);
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}
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static int
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nct_probe(device_t dev)
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{
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int i, j;
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int rc;
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struct nct_softc *sc;
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uint16_t chipid;
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/* Make sure we do not claim some ISA PNP device. */
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if (isa_get_logicalid(dev) != 0)
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return (ENXIO);
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sc = device_get_softc(dev);
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for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) {
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sc->rid = 0;
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sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
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probe_addrs[i], probe_addrs[i] + 1, 2, RF_ACTIVE);
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if (sc->portres == NULL)
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continue;
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GPIO_LOCK_INIT(sc);
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GPIO_ASSERT_UNLOCKED(sc);
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GPIO_LOCK(sc);
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ext_cfg_enter(sc);
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chipid = read_cfg_reg_2(sc, NCT_CR_CHIP_ID);
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ext_cfg_exit(sc);
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GPIO_UNLOCK(sc);
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GPIO_LOCK_DESTROY(sc);
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|
||||
bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
|
||||
bus_delete_resource(dev, SYS_RES_IOPORT, sc->rid);
|
||||
|
||||
for (j = 0; j < sizeof(nct_devs) / sizeof(*nct_devs); j++) {
|
||||
if (chipid == nct_devs[j].chip_id) {
|
||||
rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, probe_addrs[i], 2);
|
||||
if (rc != 0) {
|
||||
device_printf(dev, "bus_set_resource failed for address 0x%02X\n", probe_addrs[i]);
|
||||
continue;
|
||||
}
|
||||
device_set_desc(dev, nct_devs[j].descr);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_attach(device_t dev)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
sc->rid = 0;
|
||||
sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
|
||||
0ul, ~0ul, 2, RF_ACTIVE);
|
||||
if (sc->portres == NULL) {
|
||||
device_printf(dev, "cannot allocate ioport\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
GPIO_LOCK_INIT(sc);
|
||||
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
ext_cfg_enter(sc);
|
||||
select_ldn(sc, NCT_LDN_GPIO);
|
||||
/* Enable gpio0 and gpio1. */
|
||||
write_cfg_reg_1(sc, NCT_LD7_GPIO_ENABLE,
|
||||
read_cfg_reg_1(sc, NCT_LD7_GPIO_ENABLE) | 0x03);
|
||||
|
||||
for (i = 0; i <= NCT_MAX_PIN; i++) {
|
||||
struct gpio_pin *pin;
|
||||
|
||||
pin = &sc->pins[i];
|
||||
pin->gp_pin = i;
|
||||
pin->gp_caps = NCT_GPIO_CAPS;
|
||||
pin->gp_flags = 0;
|
||||
|
||||
snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%02u", i);
|
||||
pin->gp_name[GPIOMAXNAME - 1] = '\0';
|
||||
|
||||
if (nct_pin_is_input(sc, i))
|
||||
pin->gp_flags |= GPIO_PIN_INPUT;
|
||||
else
|
||||
pin->gp_flags |= GPIO_PIN_OUTPUT;
|
||||
|
||||
if (nct_pin_is_opendrain(sc, i))
|
||||
pin->gp_flags |= GPIO_PIN_OPENDRAIN;
|
||||
else
|
||||
pin->gp_flags |= GPIO_PIN_PUSHPULL;
|
||||
|
||||
if (nct_pin_is_inverted(sc, i))
|
||||
pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
|
||||
}
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
sc->busdev = gpiobus_attach_bus(dev);
|
||||
if (sc->busdev == NULL) {
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
ext_cfg_exit(sc);
|
||||
GPIO_UNLOCK(sc);
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
|
||||
GPIO_LOCK_DESTROY(sc);
|
||||
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_detach(device_t dev)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
gpiobus_detach_bus(dev);
|
||||
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
ext_cfg_exit(sc);
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
/* Cleanup resources. */
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
|
||||
|
||||
GPIO_LOCK_DESTROY(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_t
|
||||
nct_gpio_get_bus(device_t dev)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
return (sc->busdev);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_max(device_t dev, int *npins)
|
||||
{
|
||||
*npins = NCT_MAX_PIN;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
nct_write_pin(sc, pin_num, pin_value);
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
*pin_value = nct_read_pin(sc, pin_num);
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_toggle(device_t dev, uint32_t pin_num)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if (nct_read_pin(sc, pin_num))
|
||||
nct_write_pin(sc, pin_num, 0);
|
||||
else
|
||||
nct_write_pin(sc, pin_num, 1);
|
||||
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
*caps = sc->pins[pin_num].gp_caps;
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
*flags = sc->pins[pin_num].gp_flags;
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME);
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
nct_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
|
||||
{
|
||||
struct nct_softc *sc;
|
||||
struct gpio_pin *pin;
|
||||
|
||||
if (!NCT_IS_VALID_PIN(pin_num))
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
pin = &sc->pins[pin_num];
|
||||
if ((flags & pin->gp_caps) != flags)
|
||||
return (EINVAL);
|
||||
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
|
||||
(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & GPIO_PIN_INPUT)
|
||||
nct_set_pin_is_input(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_is_output(sc, pin_num);
|
||||
}
|
||||
|
||||
if (flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
|
||||
if (flags & GPIO_PIN_INPUT) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) ==
|
||||
(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & GPIO_PIN_OPENDRAIN)
|
||||
nct_set_pin_opendrain(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_pushpull(sc, pin_num);
|
||||
}
|
||||
|
||||
if (flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
|
||||
if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) !=
|
||||
(GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & GPIO_PIN_INVIN)
|
||||
nct_set_pin_is_inverted(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_not_inverted(sc, pin_num);
|
||||
}
|
||||
|
||||
pin->gp_flags = flags;
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t nct_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_identify, nct_identify),
|
||||
DEVMETHOD(device_probe, nct_probe),
|
||||
DEVMETHOD(device_attach, nct_attach),
|
||||
DEVMETHOD(device_detach, nct_detach),
|
||||
|
||||
/* GPIO */
|
||||
DEVMETHOD(gpio_get_bus, nct_gpio_get_bus),
|
||||
DEVMETHOD(gpio_pin_max, nct_gpio_pin_max),
|
||||
DEVMETHOD(gpio_pin_get, nct_gpio_pin_get),
|
||||
DEVMETHOD(gpio_pin_set, nct_gpio_pin_set),
|
||||
DEVMETHOD(gpio_pin_toggle, nct_gpio_pin_toggle),
|
||||
DEVMETHOD(gpio_pin_getname, nct_gpio_pin_getname),
|
||||
DEVMETHOD(gpio_pin_getcaps, nct_gpio_pin_getcaps),
|
||||
DEVMETHOD(gpio_pin_getflags, nct_gpio_pin_getflags),
|
||||
DEVMETHOD(gpio_pin_setflags, nct_gpio_pin_setflags),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t nct_isa_driver = {
|
||||
"gpio",
|
||||
nct_methods,
|
||||
sizeof(struct nct_softc)
|
||||
};
|
||||
|
||||
static devclass_t nct_devclass;
|
||||
|
||||
DRIVER_MODULE(nctgpio, isa, nct_isa_driver, nct_devclass, NULL, NULL);
|
||||
MODULE_DEPEND(nctgpio, gpiobus, 1, 1, 1);
|
||||
@ -250,6 +250,7 @@ SUBDIR= \
|
||||
${_nandfs} \
|
||||
${_nandsim} \
|
||||
${_ncr} \
|
||||
${_nctgpio} \
|
||||
${_ncv} \
|
||||
${_ndis} \
|
||||
netfpga10g \
|
||||
@ -558,6 +559,7 @@ _ixv= ixv
|
||||
_linprocfs= linprocfs
|
||||
_linsysfs= linsysfs
|
||||
_linux= linux
|
||||
_nctgpio= nctgpio
|
||||
_ndis= ndis
|
||||
_pccard= pccard
|
||||
.if ${MK_OFED} != "no" || defined(ALL_MODULES)
|
||||
|
||||
8
sys/modules/nctgpio/Makefile
Normal file
8
sys/modules/nctgpio/Makefile
Normal file
@ -0,0 +1,8 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/nctgpio
|
||||
KMOD= nctgpio
|
||||
SRCS= nctgpio.c
|
||||
SRCS+= device_if.h bus_if.h isa_if.h gpio_if.h opt_platform.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in New Issue
Block a user