Document the alternate event names supported for "architectural" PMC events.
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@ -23,7 +23,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd September 24, 2008
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.Dd November 12, 2008
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.Os
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.Dt PMC.ATOM 3
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.Sh NAME
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@ -273,13 +273,17 @@ The number of branch instructions decoded.
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The number of branches executed, but not necessarily retired.
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.It Li BR_INST_RETIRED.ANY
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.Pq Event C4H , Umask 00H
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.Pq Alias Qq "Branch Instruction Retired"
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li BR_INST_RETIRED.ANY1
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.Pq Event C4H , Umask 0FH
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The number of branch instructions retired that were mispredicted.
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.It Li BR_INST_RETIRED.MISPRED
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.Pq Event C5, Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
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.Pq Event C4H , Umask 02H
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The number of not taken branch instructions retired that were
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@ -458,10 +462,14 @@ The number of times the L1 data cache is snooped by the other core in
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the same processor.
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.It Li CPU_CLK_UNHALTED.BUS
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.Pq Event 3CH , Umask 01H
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.Pq Alias Qq "Unhalted Reference Cycles"
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The number of bus cycles when the core is not in the halt state.
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This is an architectural performance event.
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.It Li CPU_CLK_UNHALTED.CORE_P
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.Pq Event 3CH , Umask 00H
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.Pq Alias Qq "Unhalted Core Cycles"
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The number of core cycles while the core is not in a halt state.
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This is an architectural performance event.
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.It Li CPU_CLK_UNHALTED.NO_OTHER
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.Pq Event 3CH , Umask 02H
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The number of bus cycles during which the core remains unhalted and
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@ -597,7 +605,9 @@ length changing prefix.
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The number of cycles during which the instruction queue is full.
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.It Li INST_RETIRED.ANY_P
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.Pq Event C0H , Umask 00H
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.Pq Alias Qq "Instruction Retired"
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The number of instructions retired.
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This is an architectural performance event.
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.It Li INST_RETIRED.LOADS
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.Pq Event C0H , Umask 01H
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The number of instructions retired that contained a load operation.
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@ -744,10 +754,13 @@ The number of L2 cache requests that were rejected.
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The number of completed L2 cache requests.
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.It Li L2_RQSTS.SELF.DEMAND.I_STATE
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.Pq Event 2EH , Umask 41H
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.Pq Alias Qq "LLC Misses"
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The number of completed L2 cache demand requests from this core that
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missed the L2 cache.
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This is an architectural performance event.
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.It Li L2_RQSTS.SELF.DEMAND.MESI
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.Pq Event 2EH , Umask 4FH
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.Pq Alias Qq "LLC References"
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The number of completed L2 cache demand requests from this core.
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.It Li L2_ST Xo
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.Op ,cachestate= Ns Ar state
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@ -1154,16 +1167,15 @@ instructions retired.
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "Description"
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.It Em Alias Ta Em Event
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.It Li branches Ta Li BR_INST_RETIRED.ANY
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.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED
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.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi
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.It Li ic-misses Ta Li ICACHE.MISSES
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.It Li instructions Ta Li INST_RETIRED.ANY_P
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.It Li interrupts Ta Li HW_INT_RCV
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.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P
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and the underlying hardware events used on these CPUs.
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.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
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.It Em Alias Ta Em Event Ta Em PMC Class
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.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP
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.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
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.It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP
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.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF
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.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP
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.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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@ -23,7 +23,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd September 21, 2008
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.Dd November 12, 2008
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.Os
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.Dt PMC.CORE 3
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.Sh NAME
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@ -234,11 +234,15 @@ The number of branch instructions executed including speculative branches.
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.Pq Event E0H
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The number of branch instructions decoded.
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.It Li Br_Instr_Ret
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.Pq Event C4H
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.Pq Event C4H, Umask 00H
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.Pq Alias Qq "Branch Instruction Retired"
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li Br_MisPred_Ret
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.Pq Event C5H
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.Pq Event C5H, Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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.It Li Br_MisPred_Taken_Ret
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.Pq Event CAH
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The number of taken and mispredicted branches retired.
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@ -475,7 +479,9 @@ The number of instruction TLB misses.
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The number of instructions decoded.
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.It Li Instr_Ret
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.Pq Event C0H
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.Pq Alias Qq "Instruction Retired"
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The number of instructions retired.
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This is an architectural performance event.
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.It Li L1_Pref_Req
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.Pq Event 4FH
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The number of L1 prefetch request due to data cache misses.
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@ -546,6 +552,17 @@ The number of L2 cache writes including speculative writes.
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.It Li LD_Blocks
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.Pq Event 03H
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The number of load operations delayed due to store buffer blocks.
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.It Li LLC_Misses
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.Pq Event 2EH, Umask 41H
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The number of cache misses for references to the last level cache,
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excluding misses due to hardware prefetches.
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This is an architectural performance event.
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.It Li LLC_Reference
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The number of references to the last level cache,
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excluding those due to hardware prefetches.
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This is an architectural performance event.
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.Pq Event 2EH, Umask 4FH
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This is an architectural performance event.
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.It Li MMX_Assist
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.Pq Event CDH
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The number of EMMX instructions executed.
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@ -573,7 +590,9 @@ and integer multiplies.
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This event is available on PMC1 only.
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.It Li NonHlt_Ref_Cycles
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.Pq Event 3CH , Umask 01H
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.Pq Alias Qq "Unhalted Reference Cycles"
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The number of non-halted bus cycles.
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This is an architectural performance event.
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.It Li Pref_Rqsts_Dn
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.Pq Event F8H
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The number of hardware prefetch requests issued in backward streams.
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@ -690,6 +709,11 @@ The duration in a thermal trip based on the current core clock.
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.It Li Unfusion
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.Pq Event DBH
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The number of unfusion events.
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.It Li "Unhalted_Core_Cycles"
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.Pq Event 3CH , Umask 00H
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The number of core clock cycles when the clock signal on a specific
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core is not halted.
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This is an architectural performance event.
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.It Li Uops_Ret
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.Pq Event C2H
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The number of micro-ops retired.
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@ -23,7 +23,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd September 24, 2008
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.Dd November 12, 2008
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.Os
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.Dt PMC.CORE2 3
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.Sh NAME
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@ -271,10 +271,14 @@ The number of branch instructions decoded.
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The number of branches executed, but not necessarily retired.
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.It Li BR_INST_RETIRED.ANY
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.Pq Event C4H , Umask 00H
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.Pq Alias Qq "Branch Instruction Retired"
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li BR_INST_RETIRED.MISPRED
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.Pq Event C5H
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.Pq Event C5H, Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
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.Pq Event C4H , Umask 02H
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The number of not taken branch instructions retired that were
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@ -446,10 +450,14 @@ The number of times the L1 data cache is snooped by the other core in
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the same processor.
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.It Li CPU_CLK_UNHALTED.BUS
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.Pq Event 3CH , Umask 01H
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.Pq Alias Qq "Unhalted Reference Cycles"
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The number of bus cycles when the core is not in the halt state.
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This is an architectural performance event.
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.It Li CPU_CLK_UNHALTED.CORE_P
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.Pq Event 3CH , Umask 00H
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.Pq Alias Qq "Unhalted Core Cycles"
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The number of core cycles while the core is not in a halt state.
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This is an architectural performance event.
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.It Li CPU_CLK_UNHALTED.NO_OTHER
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.Pq Event 3CH , Umask 02H
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The number of bus cycles during which the core remains unhalted and
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@ -553,7 +561,9 @@ length changing prefix.
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The number of cycles during which the instruction queue is full.
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.It Li INST_RETIRED.ANY_P
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.Pq Event C0H , Umask 00H
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.Pq Alias Qq "Instruction Retired"
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The number of instructions retired.
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This is an architectural performance event.
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.It Li INST_RETIRED.LOADS
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.Pq Event C0H , Umask 01H
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The number of instructions retired that contained a load operation.
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@ -705,11 +715,15 @@ The number of L2 cache requests that were rejected.
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The number of completed L2 cache requests.
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.It Li L2_RQSTS.SELF.DEMAND.I_STATE
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.Pq Event 2EH , Umask 41H
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.Pq Alias Qq "LLC Misses"
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The number of completed L2 cache demand requests from this core that
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missed the L2 cache.
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This is an architectural performance event.
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.It Li L2_RQSTS.SELF.DEMAND.MESI
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.Pq Event 2EH , Umask 4FH
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.Pq Alias Qq "LLC References"
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The number of completed L2 cache demand requests from this core.
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This is an architectural performance event.
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.It Li L2_ST Xo
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.Op ,cachestate= Ns Ar state
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.Op ,core= Ns Ar core
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@ -1075,15 +1089,14 @@ The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "Description"
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.It Em Alias Ta Em Event
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.It Li branches Ta Li BR_INST_RETIRED.ANY
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.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED
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.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi
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.It Li ic-misses Ta Li L1I_MISSES
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.It Li instructions Ta Li INST_RETIRED.ANY_P
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.It Li interrupts Ta Li HW_INT_RCV
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.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P
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.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
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.It Em Alias Ta Em Event Ta Em PMC Class
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.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP
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.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
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.It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP
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.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF
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.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP
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.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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