Add a cpufreq driver for the SpeedStep capability in the ICH chipset. This
driver offers two settings. Information for this driver was obtained from the Intel datasheets and by reviewing the Linux driver.
This commit is contained in:
Nate Lawson
parent
73347b071d
commit
6c7b11ccfa
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=141241
372
sys/dev/cpufreq/ichss.c
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372
sys/dev/cpufreq/ichss.c
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@ -0,0 +1,372 @@
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/*-
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* Copyright (c) 2004-2005 Nate Lawson (SDG)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/pcpu.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <machine/clock.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include "cpufreq_if.h"
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/*
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* The SpeedStep ICH feature is a chipset-initiated voltage and frequency
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* transition available on the ICH2M, 3M, and 4M. It is different from
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* the newer Pentium-M SpeedStep feature. It offers only two levels of
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* frequency/voltage. Often, the BIOS will select one of the levels via
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* SMM code during the power-on process (i.e., choose a lower level if the
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* system is off AC power.)
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*/
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struct ichss_softc {
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device_t dev;
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int bm_rid; /* Bus-mastering control (PM2REG). */
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struct resource *bm_reg;
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int ctrl_rid; /* Control/status register. */
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struct resource *ctrl_reg;
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struct cf_setting sets[2]; /* Only two settings. */
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};
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/* Supported PCI IDs. */
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#define PCI_VENDOR_INTEL 0x8086
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#define PCI_DEV_82801BA 0x244c /* ICH2M */
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#define PCI_DEV_82801CA 0x248c /* ICH3M */
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#define PCI_DEV_82801DB 0x24cc /* ICH4M */
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#define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */
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/* PCI config registers for finding PMBASE and enabling SpeedStep. */
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#define ICHSS_PMBASE_OFFSET 0x40
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#define ICHSS_PMCFG_OFFSET 0xa0
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/* Values and masks. */
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#define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */
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#define ICHSS_IO_REG 0x1 /* Access register via I/O space. */
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#define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */
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#define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */
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#define ICHSS_BM_DISABLE 0x1
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/* Offsets from PMBASE for various registers. */
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#define ICHSS_BM_OFFSET 0x20
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#define ICHSS_CTRL_OFFSET 0x50
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#define ICH_GET_REG(reg) \
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(bus_space_read_1(rman_get_bustag((reg)), \
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rman_get_bushandle((reg)), 0))
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#define ICH_SET_REG(reg, val) \
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(bus_space_write_1(rman_get_bustag((reg)), \
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rman_get_bushandle((reg)), 0, (val)))
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static int ichss_pci_probe(device_t dev);
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static int ichss_probe(device_t dev);
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static int ichss_attach(device_t dev);
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static int ichss_detach(device_t dev);
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static int ichss_settings(device_t dev, struct cf_setting *sets,
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int *count, int *type);
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static int ichss_set(device_t dev, const struct cf_setting *set);
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static int ichss_get(device_t dev, struct cf_setting *set);
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static device_method_t ichss_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ichss_probe),
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DEVMETHOD(device_attach, ichss_attach),
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DEVMETHOD(device_detach, ichss_detach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, ichss_set),
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DEVMETHOD(cpufreq_drv_get, ichss_get),
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DEVMETHOD(cpufreq_drv_settings, ichss_settings),
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{0, 0}
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};
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static driver_t ichss_driver = {
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"ichss", ichss_methods, sizeof(struct ichss_softc)
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};
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static devclass_t ichss_devclass;
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DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0);
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static device_method_t ichss_pci_methods[] = {
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DEVMETHOD(device_probe, ichss_pci_probe),
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{0, 0}
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};
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static driver_t ichss_pci_driver = {
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"ichss_pci", ichss_pci_methods, 0
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};
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static devclass_t ichss_pci_devclass;
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DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0);
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#if 0
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#define DPRINT(x...) printf(x)
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#else
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#define DPRINT(x...)
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#endif
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/*
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* We detect the chipset by looking for its LPC bus ID during the PCI
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* scan and reading its config registers during the probe. However,
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* we add the ichss child under the cpu device since even though the
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* chipset provides the control, it really affects the cpu only.
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*
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* XXX This approach does not work if the module is loaded after boot.
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*/
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static int
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ichss_pci_probe(device_t dev)
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{
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device_t child, parent;
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uint32_t pmbase;
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uint16_t ss_en;
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/*
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* TODO: add a quirk to disable if we see the 82815_MC along
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* with the 82801BA and revision < 5.
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*/
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if (pci_get_vendor(dev) != PCI_VENDOR_INTEL ||
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(pci_get_device(dev) != PCI_DEV_82801BA &&
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pci_get_device(dev) != PCI_DEV_82801CA &&
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pci_get_device(dev) != PCI_DEV_82801DB))
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return (ENXIO);
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/* Only one CPU is supported for this hardware. */
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if (devclass_get_device(ichss_devclass, 0))
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return (ENXIO);
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/* Add a child under the CPU parent. */
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parent = devclass_get_device(devclass_find("cpu"), 0);
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KASSERT(parent != NULL, ("cpu parent is NULL"));
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child = BUS_ADD_CHILD(parent, 0, "ichss", 0);
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if (child == NULL) {
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device_printf(parent, "add SpeedStep child failed\n");
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return (ENXIO);
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}
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/* Find the PMBASE register from our PCI config header. */
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pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase));
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if ((pmbase & ICHSS_IO_REG) == 0) {
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printf("ichss: invalid PMBASE memory type\n");
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return (ENXIO);
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}
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pmbase &= ICHSS_PMBASE_MASK;
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if (pmbase == 0) {
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printf("ichss: invalid zero PMBASE address\n");
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return (ENXIO);
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}
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DPRINT("ichss: PMBASE is %#x\n", pmbase);
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/* Add the bus master arbitration and control registers. */
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bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET,
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1);
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bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET,
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1);
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/* Activate SpeedStep control if not already enabled. */
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ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
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if ((ss_en & ICHSS_ENABLE) == 0) {
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printf("ichss: enabling SpeedStep support\n");
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pci_write_config(dev, ICHSS_PMCFG_OFFSET,
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ss_en | ICHSS_ENABLE, sizeof(ss_en));
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}
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/* Attach the new CPU child now. */
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device_probe_and_attach(child);
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return (ENXIO);
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}
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static int
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ichss_probe(device_t dev)
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{
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device_t perf_dev;
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/* If the ACPI perf driver has attached, let it manage things. */
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perf_dev = devclass_get_device(devclass_find("acpi_perf"), 0);
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if (perf_dev && device_is_attached(perf_dev))
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return (ENXIO);
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device_set_desc(dev, "SpeedStep ICH");
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return (-1000);
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}
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static int
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ichss_attach(device_t dev)
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{
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struct ichss_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->bm_rid = 0;
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sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
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RF_ACTIVE);
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if (sc->bm_reg == NULL) {
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device_printf(dev, "failed to alloc BM arb register\n");
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return (ENXIO);
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}
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sc->ctrl_rid = 1;
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sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&sc->ctrl_rid, RF_ACTIVE);
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if (sc->ctrl_reg == NULL) {
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device_printf(dev, "failed to alloc control register\n");
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bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
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sc->bm_reg);
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return (ENXIO);
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}
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/* Setup some defaults for our exported settings. */
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sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].lat = 1000;
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sc->sets[0].dev = dev;
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sc->sets[1] = sc->sets[0];
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cpufreq_register(dev);
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return (0);
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}
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static int
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ichss_detach(device_t dev)
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{
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/* TODO: teardown BM and CTRL registers. */
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return (ENXIO);
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}
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static int
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ichss_settings(device_t dev, struct cf_setting *sets, int *count, int *type)
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{
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struct ichss_softc *sc;
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struct cf_setting set;
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int first, i;
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < 2) {
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*count = 2;
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return (E2BIG);
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}
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sc = device_get_softc(dev);
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/*
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* Estimate frequencies for both levels, temporarily switching to
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* the other one if we haven't calibrated it yet.
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*/
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ichss_get(dev, &set);
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for (i = 0; i < 2; i++) {
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if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
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first = (i == 0) ? 1 : 0;
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ichss_set(dev, &sc->sets[i]);
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ichss_set(dev, &sc->sets[first]);
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}
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}
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bcopy(sc->sets, sets, sizeof(sc->sets));
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*count = 2;
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*type = CPUFREQ_TYPE_ABSOLUTE;
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return (0);
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}
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static int
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ichss_set(device_t dev, const struct cf_setting *set)
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{
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struct ichss_softc *sc;
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uint8_t bmval, new_val, old_val, req_val;
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uint64_t rate;
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/* Look up appropriate bit value based on frequency. */
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sc = device_get_softc(dev);
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if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
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req_val = 0;
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else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
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req_val = ICHSS_CTRL_BIT;
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else
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return (EINVAL);
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DPRINT("ichss: requested setting %d\n", req_val);
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/* Disable interrupts and get the other register contents. */
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disable_intr();
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old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
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/*
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* Disable bus master arbitration, write the new value to the control
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* register, and then re-enable bus master arbitration.
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*/
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bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;
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ICH_SET_REG(sc->bm_reg, bmval);
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ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
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ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);
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/* Get the new value and re-enable interrupts. */
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new_val = ICH_GET_REG(sc->ctrl_reg);
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enable_intr();
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/* Check if the desired state was indeed selected. */
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if (req_val != (new_val & ICHSS_CTRL_BIT)) {
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device_printf(sc->dev, "transition to %d failed\n", req_val);
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return (ENXIO);
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}
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/* Re-initialize our cycle counter if we don't know this new state. */
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if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {
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cpu_est_clockrate(0, &rate);
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sc->sets[req_val].freq = rate / 1000000;
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DPRINT("ichss: set calibrated new rate of %d\n",
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sc->sets[req_val].freq);
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}
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return (0);
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}
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static int
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ichss_get(device_t dev, struct cf_setting *set)
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{
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struct ichss_softc *sc;
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uint64_t rate;
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uint8_t state;
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sc = device_get_softc(dev);
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state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
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/* If we haven't changed settings yet, estimate the current value. */
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if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
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cpu_est_clockrate(0, &rate);
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sc->sets[state].freq = rate / 1000000;
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DPRINT("ichss: get calibrated new rate of %d\n",
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sc->sets[state].freq);
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}
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*set = sc->sets[state];
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return (0);
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}
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