amd64: Issue MFENCE on context switch on AMD CPUs when reusing address space.
On some AMD CPUs, in particular, machines that do not implement CLFLUSHOPT but do provide CLFLUSH, the CLFLUSH instruction is only synchronized with MFENCE. Code using CLFLUSH typicall needs to brace it with MFENCE both before and after flush, see for instance pmap_invalidate_cache_range(). If context switch occurs while inside the protected region, we need to ensure visibility of flushes done on the old CPU, to new CPU. For all other machines, locked operation done to lock switched thread, should be enough. For case of different address spaces, reload of %cr3 is serializing. Reviewed by: cem, jhb, scottph Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D22007
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=354630
@ -8810,8 +8810,11 @@ pmap_activate_sw(struct thread *td)
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oldpmap = PCPU_GET(curpmap);
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pmap = vmspace_pmap(td->td_proc->p_vmspace);
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if (oldpmap == pmap)
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if (oldpmap == pmap) {
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if (cpu_vendor_id != CPU_VENDOR_INTEL)
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mfence();
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return;
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}
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cpuid = PCPU_GET(cpuid);
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#ifdef SMP
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CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
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