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amd64: Issue MFENCE on context switch on AMD CPUs when reusing address space.

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On some AMD CPUs, in particular, machines that do not implement
CLFLUSHOPT but do provide CLFLUSH, the CLFLUSH instruction is only
synchronized with MFENCE.

Code using CLFLUSH typicall needs to brace it with MFENCE both before
and after flush, see for instance pmap_invalidate_cache_range().  If
context switch occurs while inside the protected region, we need to
ensure visibility of flushes done on the old CPU, to new CPU.

For all other machines, locked operation done to lock switched thread,
should be enough.  For case of different address spaces, reload of
%cr3 is serializing.

Reviewed by:	cem, jhb, scottph
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D22007
This commit is contained in:
Konstantin Belousov 2019-11-11 21:59:20 +00:00
parent 1cbfe73da5
commit 6cd492bcd4
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=354630
1 changed files with 4 additions and 1 deletions
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5
sys/amd64/amd64/pmap.c
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@ -8810,8 +8810,11 @@ pmap_activate_sw(struct thread *td)
oldpmap = PCPU_GET(curpmap);
pmap = vmspace_pmap(td->td_proc->p_vmspace);
if (oldpmap == pmap)
if (oldpmap == pmap) {
if (cpu_vendor_id != CPU_VENDOR_INTEL)
mfence();
return;
}
cpuid = PCPU_GET(cpuid);
#ifdef SMP
CPU_SET_ATOMIC(cpuid, &pmap->pm_active);