arch.7: Drop most mentions of MIPS.
Only keep MIPS in the list of deprecated architectures. Reviewed by: emaste Differential Revision: https://reviews.freebsd.org/D38970
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@ -26,7 +26,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd September 15, 2022
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.Dd March 8, 2023
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.Dt ARCH 7
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.Os
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.Sh NAME
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@ -158,7 +158,6 @@ Examples are:
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.It Sy LP64 Ta Sy ILP32 counterpart
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.It Dv amd64 Ta Dv i386
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.It Dv powerpc64 Ta Dv powerpc
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.It Dv mips64* Ta Dv mips*
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.It Dv aarch64 Ta Dv armv6/armv7
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.El
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.Pp
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@ -201,15 +200,6 @@ Machine-dependent type sizes:
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.It armv6 Ta 4 Ta 8 Ta 8
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.It armv7 Ta 4 Ta 8 Ta 8
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.It i386 Ta 4 Ta 12 Ta 4
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.It mips Ta 4 Ta 8 Ta 8
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.It mipsel Ta 4 Ta 8 Ta 8
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.It mipselhf Ta 4 Ta 8 Ta 8
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.It mipshf Ta 4 Ta 8 Ta 8
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.It mipsn32 Ta 4 Ta 8 Ta 8
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.It mips64 Ta 8 Ta 8 Ta 8
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.It mips64el Ta 8 Ta 8 Ta 8
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.It mips64elhf Ta 8 Ta 8 Ta 8
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.It mips64hf Ta 8 Ta 8 Ta 8
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.It powerpc Ta 4 Ta 8 Ta 8
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.It powerpcspe Ta 4 Ta 8 Ta 8
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.It powerpc64 Ta 8 Ta 8 Ta 8
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@ -228,15 +218,6 @@ is 8 bytes on all supported architectures except i386.
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.It armv6 Ta little Ta unsigned
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.It armv7 Ta little Ta unsigned
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.It i386 Ta little Ta signed
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.It mips Ta big Ta signed
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.It mipsel Ta little Ta signed
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.It mipselhf Ta little Ta signed
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.It mipshf Ta big Ta signed
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.It mipsn32 Ta big Ta signed
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.It mips64 Ta big Ta signed
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.It mips64el Ta little Ta signed
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.It mips64elhf Ta little Ta signed
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.It mips64hf Ta big Ta signed
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.It powerpc Ta big Ta unsigned
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.It powerpcspe Ta big Ta unsigned
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.It powerpc64 Ta big Ta unsigned
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@ -252,15 +233,6 @@ is 8 bytes on all supported architectures except i386.
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.It armv6 Ta 4K, 1M
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.It armv7 Ta 4K, 1M
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.It i386 Ta 4K, 2M (PAE), 4M
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.It mips Ta 4K
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.It mipsel Ta 4K
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.It mipselhf Ta 4K
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.It mipshf Ta 4K
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.It mipsn32 Ta 4K
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.It mips64 Ta 4K
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.It mips64el Ta 4K
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.It mips64elhf Ta 4K
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.It mips64hf Ta 4K
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.It powerpc Ta 4K
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.It powerpcspe Ta 4K
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.It powerpc64 Ta 4K
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@ -276,15 +248,6 @@ is 8 bytes on all supported architectures except i386.
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.It armv6 Ta hard Ta hard, double precision
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.It armv7 Ta hard Ta hard, double precision
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.It i386 Ta hard Ta hard, 80 bit
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.It mips Ta soft Ta identical to double
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.It mipsel Ta soft Ta identical to double
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.It mipselhf Ta hard Ta identical to double
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.It mipshf Ta hard Ta identical to double
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.It mipsn32 Ta soft Ta identical to double
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.It mips64 Ta soft Ta identical to double
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.It mips64el Ta soft Ta identical to double
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.It mips64elhf Ta hard Ta identical to double
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.It mips64hf Ta hard Ta identical to double
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.It powerpc Ta hard Ta hard, double precision
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.It powerpcspe Ta hard Ta hard, double precision
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.It powerpc64 Ta hard Ta hard, double precision
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@ -321,7 +284,6 @@ or similar things like boot sequences.
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.It amd64 Ta amd64 Ta amd64
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.It arm Ta arm Ta armv6, armv7
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.It i386 Ta i386 Ta i386
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.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
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.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le
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.It riscv Ta riscv Ta riscv64, riscv64sf
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.El
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@ -355,15 +317,6 @@ Architecture-specific macros:
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.It armv6 Ta Dv __arm__ , Dv __ARM_ARCH >= 6
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.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7
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.It i386 Ta Dv __i386__
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.It mips Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32
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.It mipsel Ta Dv __mips__ , Dv __mips_o32
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.It mipselhf Ta Dv __mips__ , Dv __mips_o32
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.It mipshf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32
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.It mipsn32 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n32
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.It mips64 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64
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.It mips64el Ta Dv __mips__ , Dv __mips_n64
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.It mips64elhf Ta Dv __mips__ , Dv __mips_n64
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.It mips64hf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64
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.It powerpc Ta Dv __powerpc__
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.It powerpcspe Ta Dv __powerpc__ , Dv __SPE__
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.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__
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@ -431,17 +384,13 @@ It may also encode a variation in the size of the integer or pointer.
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It may also encode a ISA revision.
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It may also encode hard versus soft floating point ABI and usage.
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It may also encode a variant ABI when the other factors do not
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uniquely define the ABI (e.g., MIPS' n32 ABI).
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uniquely define the ABI.
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It, along with
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.Dv MACHINE ,
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defines the ABI used by the system.
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For example, the MIPS CPU processor family supports 9 different
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combinations encoding pointer size, endian and hard versus soft float (for
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8 combinations) as well as N32 (which only ever had one variation of
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all these).
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Generally, the plain CPU name specifies the most common (or at least
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first) variant of the CPU.
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This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7'
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This is why powerpc and powerpc64 imply 'big endian' while 'armv6' and 'armv7'
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imply little endian.
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If we ever were to support the so-called x32 ABI (using 32-bit
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pointers on the amd64 architecture), it would most likely be encoded
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@ -455,10 +404,6 @@ Represents the source location for a given
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.Dv MACHINE_ARCH .
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It is generally the common prefix for all the MACHINE_ARCH that
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share the same implementation, though 'riscv' breaks this rule.
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For example,
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.Dv MACHINE_CPUARCH
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is defined to be mips for all the flavors of mips that we support
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since we support them all with a shared set of sources.
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While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
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for them.
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The
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