Clean up uhci_intr. Avoid acknowledging mutliple interrupts with
multiple writes.
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94002a7568
commit
6dd24aec32
@ -654,48 +654,49 @@ uhci_remove_bulk(sc, sqh)
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}
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int
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uhci_intr(p)
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void *p;
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uhci_intr(priv)
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void *priv;
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{
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uhci_softc_t *sc = p;
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int status, ret;
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uhci_softc_t *sc = priv;
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int status;
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int ack = 0;
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uhci_intr_info_t *ii;
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sc->sc_intrs++;
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#if defined(UHCI_DEBUG)
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if (uhcidebug > 9) {
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DPRINTF(("uhci_intr %p\n", sc));
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printf("%s: uhci_intr\n", USBDEVNAME(sc->sc_bus.bdev));
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uhci_dumpregs(sc);
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}
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#endif
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status = UREAD2(sc, UHCI_STS);
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ret = 0;
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if (status & UHCI_STS_USBINT) {
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UWRITE2(sc, UHCI_STS, UHCI_STS_USBINT); /* acknowledge */
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ret = 1;
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}
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if (status & UHCI_STS_USBEI) {
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UWRITE2(sc, UHCI_STS, UHCI_STS_USBEI); /* acknowledge */
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ret = 1;
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}
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if (status & UHCI_STS_USBINT)
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ack |= UHCI_STS_USBINT;
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if (status & UHCI_STS_USBEI)
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ack |= UHCI_STS_USBEI;
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if (status & UHCI_STS_RD) {
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UWRITE2(sc, UHCI_STS, UHCI_STS_RD); /* acknowledge */
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DPRINTF(("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)));
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ret = 1;
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ack |= UHCI_STS_RD;
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printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev));
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}
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if (status & UHCI_STS_HSE) {
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UWRITE2(sc, UHCI_STS, UHCI_STS_HSE); /* acknowledge */
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DPRINTF(("%s: Host System Error\n", USBDEVNAME(sc->sc_bus.bdev)));
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ret = 1;
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ack |= UHCI_STS_HSE;
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printf("%s: Host Controller Process Error\n", USBDEVNAME(sc->sc_bus.bdev));
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}
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if (status & UHCI_STS_HCPE) {
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UWRITE2(sc, UHCI_STS, UHCI_STS_HCPE); /* acknowledge */
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DPRINTF(("%s: Host System Error\n", USBDEVNAME(sc->sc_bus.bdev)));
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ret = 1;
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ack |= UHCI_STS_HCPE;
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printf("%s: Host System Error\n", USBDEVNAME(sc->sc_bus.bdev));
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}
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if (status & UHCI_STS_HCH)
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DPRINTF(("%s: controller halted\n", USBDEVNAME(sc->sc_bus.bdev)));
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if (!ret)
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if (status & UHCI_STS_HCH) {
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/* no acknowledge needed */
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printf("%s: controller halted\n", USBDEVNAME(sc->sc_bus.bdev));
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}
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if (ack) /* acknowledge the ints */
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UWRITE2(sc, UHCI_STS, ack);
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else /* nothing to acknowledge */
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return 0;
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/*
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