arm64: Hyper-V: vPCI: Adding Hyper-V PCI protocol 1.4
This is enabling the PCI protocol 1.4 and corresponding structures in order to support arm64 Hyper-V. This is the 2nd of the three patches to enable Hyper-V vPCI support in arm64. Reviewed by: whu Tested by: Souradeep Chakrabarti <schakrabarti@microsoft.com> Obtained from: Souradeep Chakrabarti <schakrabarti@microsoft.com> Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D37780
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@ -28,6 +28,7 @@
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__FBSDID("$FreeBSD$");
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#ifdef NEW_PCIB
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -50,6 +51,9 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_kern.h>
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#include <vm/pmap.h>
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#if defined(__aarch64__)
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#include <arm64/include/intr.h>
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#endif
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#include <machine/atomic.h>
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#include <machine/bus.h>
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#include <machine/frame.h>
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@ -62,10 +66,16 @@ __FBSDID("$FreeBSD$");
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#include <dev/pci/pci_private.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#if defined(__i386__) || defined(__amd64__)
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#include <machine/intr_machdep.h>
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#include <x86/apicreg.h>
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#endif
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#if defined(__aarch64__)
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/acpica/acpi_pcibvar.h>
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#endif
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#include <dev/hyperv/include/hyperv.h>
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#include <dev/hyperv/include/hyperv_busdma.h>
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#include <dev/hyperv/include/vmbus_xact.h>
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@ -142,7 +152,7 @@ wait_for_completion_timeout(struct completion *c, int timeout)
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return (ret);
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}
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#define PCI_MAKE_VERSION(major, minor) ((uint32_t)(((major) << 16) | (major)))
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#define PCI_MAKE_VERSION(major, minor) ((uint32_t)(((major) << 16) | (minor)))
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enum {
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PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1),
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@ -182,6 +192,12 @@ enum pci_message_type {
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PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
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PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
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PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
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PCI_RESOURCES_ASSIGNED2 = PCI_MESSAGE_BASE + 0x16,
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PCI_CREATE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x17,
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PCI_DELETE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x18, /* unused */
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PCI_BUS_RELATIONS2 = PCI_MESSAGE_BASE + 0x19,
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PCI_RESOURCES_ASSIGNED3 = PCI_MESSAGE_BASE + 0x1A,
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PCI_CREATE_INTERRUPT_MESSAGE3 = PCI_MESSAGE_BASE + 0x1B,
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PCI_MESSAGE_MAXIMUM
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};
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@ -223,6 +239,22 @@ struct pci_func_desc {
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uint32_t ser; /* serial number */
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} __packed;
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struct pci_func_desc2 {
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uint16_t v_id; /* vendor ID */
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uint16_t d_id; /* device ID */
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uint8_t rev;
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uint8_t prog_intf;
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uint8_t subclass;
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uint8_t base_class;
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uint32_t subsystem_id;
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union win_slot_encoding wslot;
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uint32_t ser; /* serial number */
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uint32_t flags;
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uint16_t virtual_numa_node;
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uint16_t reserved;
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} __packed;
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struct hv_msi_desc {
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uint8_t vector;
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uint8_t delivery_mode;
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@ -231,6 +263,15 @@ struct hv_msi_desc {
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uint64_t cpu_mask;
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} __packed;
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struct hv_msi_desc3 {
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uint32_t vector;
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uint8_t delivery_mode;
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uint8_t reserved;
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uint16_t vector_count;
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uint16_t processor_count;
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uint16_t processor_array[32];
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} __packed;
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struct tran_int_desc {
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uint16_t reserved;
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uint16_t vector_count;
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@ -288,6 +329,12 @@ struct pci_bus_relations {
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struct pci_func_desc func[0];
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} __packed;
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struct pci_bus_relations2 {
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struct pci_incoming_message incoming;
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uint32_t device_count;
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struct pci_func_desc2 func[0];
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} __packed;
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#define MAX_NUM_BARS (PCIR_MAX_BAR_0 + 1)
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struct pci_q_res_req_response {
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struct vmbus_chanpkt_hdr hdr;
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@ -303,12 +350,26 @@ struct pci_resources_assigned {
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uint32_t reserved[4];
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} __packed;
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struct pci_resources_assigned2 {
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struct pci_message message_type;
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union win_slot_encoding wslot;
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uint8_t memory_range[0x14][6]; /* not used here */
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uint32_t msi_descriptor_count;
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uint8_t reserved[70];
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} __packed;
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struct pci_create_interrupt {
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struct pci_message message_type;
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union win_slot_encoding wslot;
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struct hv_msi_desc int_desc;
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} __packed;
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struct pci_create_interrupt3 {
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struct pci_message message_type;
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union win_slot_encoding wslot;
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struct hv_msi_desc3 int_desc;
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} __packed;
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struct pci_create_int_response {
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struct pci_response response;
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uint32_t reserved;
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@ -356,12 +417,28 @@ struct hv_pcibus {
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struct mtx config_lock; /* Avoid two threads writing index page */
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struct mtx device_list_lock; /* Protect lists below */
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uint32_t protocol_version;
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TAILQ_HEAD(, hv_pci_dev) children;
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TAILQ_HEAD(, hv_dr_state) dr_list;
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volatile int detaching;
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};
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struct hv_pcidev_desc {
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uint16_t v_id; /* vendor ID */
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uint16_t d_id; /* device ID */
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uint8_t rev;
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uint8_t prog_intf;
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uint8_t subclass;
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uint8_t base_class;
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uint32_t subsystem_id;
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union win_slot_encoding wslot;
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uint32_t ser; /* serial number */
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uint32_t flags;
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uint16_t virtual_numa_node;
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} __packed;
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struct hv_pci_dev {
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TAILQ_ENTRY(hv_pci_dev) link;
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