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Intel DMAR: remove parsing of 6-level paging capability

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Early versions of the VT-d spec mentioned 6-level paging support as a
possible value for the SAGAW capability, but later versions removed it
and SAGAW=0x10 is currently listed as a reserved value.

The 6-level (agaw=64) entry in sagaw_bits is furthermore problematic
with clang15 because the attempted comparison against 1ULL << 64 in
dmar_maxaddr2mgaw() causes the compiler to elide the last iteration
of the initial loop, which bypasses the subsequent logic to find the
greatest HW-supported address width.  This results in 5-level paging
always being selected regardless of whether the hardware supports it,
which can result address translation failure due to invalid context-
entry programming.

Reviewed by:	kib
MFC after:	3 days
Differential Revision: https://reviews.freebsd.org/D39896
This commit is contained in:
Jason A. Harmening 2023-05-01 11:22:39 -05:00
parent 42f722e721
commit 6f378116e9
1 changed files with 8 additions and 3 deletions
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11
sys/x86/iommu/intel_utils.c
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@ -99,9 +99,14 @@ static const struct sagaw_bits_tag {
{.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
.pglvl = 4},
{.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
.pglvl = 5},
{.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
.pglvl = 6}
.pglvl = 5}
/*
* 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any
* current VT-d hardware and its SAGAW field value is listed as
* reserved in the VT-d spec. If support is added in the future,
* this structure and the logic in dmar_maxaddr2mgaw() will need
* to change to avoid attempted comparison against 1ULL << 64.
*/
};
bool