Add FPGA manager driver for Intel Arria 10.
With this driver we able to program FPGA core from FreeBSD system running on ARM core. Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
609a6315b7
commit
6fd86cf752
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=314600
@ -11,6 +11,9 @@ arm/altera/socfpga/socfpga_gpio.c optional gpio
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dev/mmc/host/dwmmc.c optional dwmmc
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# Arria 10
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arm/altera/socfpga/socfpga_a10_manager.c standard
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# BERI specific
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dev/beri/beri_ring.c optional beri_ring
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dev/beri/beri_mem.c optional beri_mem
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444
sys/arm/altera/socfpga/socfpga_a10_manager.c
Normal file
444
sys/arm/altera/socfpga/socfpga_a10_manager.c
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@ -0,0 +1,444 @@
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/*-
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* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Intel Arria 10 FPGA Manager.
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* Chapter 4, Arria 10 Hard Processor System Technical Reference Manual.
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* Chapter A, FPGA Reconfiguration.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/conf.h>
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#include <sys/uio.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/altera/socfpga/socfpga_common.h>
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#define FPGAMGR_DCLKCNT 0x8 /* DCLK Count Register */
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#define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */
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#define FPGAMGR_GPO 0x10 /* General-Purpose Output Register */
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#define FPGAMGR_GPI 0x14 /* General-Purpose Input Register */
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#define FPGAMGR_MISCI 0x18 /* Miscellaneous Input Register */
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#define IMGCFG_CTRL_00 0x70
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#define S2F_CONDONE_OE (1 << 24)
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#define S2F_NSTATUS_OE (1 << 16)
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#define CTRL_00_NCONFIG (1 << 8)
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#define CTRL_00_NENABLE_CONDONE (1 << 2)
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#define CTRL_00_NENABLE_NSTATUS (1 << 1)
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#define CTRL_00_NENABLE_NCONFIG (1 << 0)
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#define IMGCFG_CTRL_01 0x74
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#define CTRL_01_S2F_NCE (1 << 24)
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#define CTRL_01_S2F_PR_REQUEST (1 << 16)
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#define CTRL_01_S2F_NENABLE_CONFIG (1 << 0)
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#define IMGCFG_CTRL_02 0x78
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#define CTRL_02_CDRATIO_S 16
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#define CTRL_02_CDRATIO_M (0x3 << CTRL_02_CDRATIO_S)
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#define CTRL_02_CFGWIDTH_16 (0 << 24)
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#define CTRL_02_CFGWIDTH_32 (1 << 24)
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#define CTRL_02_EN_CFG_DATA (1 << 8)
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#define CTRL_02_EN_CFG_CTRL (1 << 0)
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#define IMGCFG_STAT 0x80
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#define F2S_PR_ERROR (1 << 11)
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#define F2S_PR_DONE (1 << 10)
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#define F2S_PR_READY (1 << 9)
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#define F2S_MSEL_S 16
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#define F2S_MSEL_M (0x7 << F2S_MSEL_S)
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#define MSEL_PASSIVE_FAST 0
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#define MSEL_PASSIVE_SLOW 1
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#define F2S_NCONFIG_PIN (1 << 12)
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#define F2S_CONDONE_OE (1 << 7)
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#define F2S_NSTATUS_PIN (1 << 4)
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#define F2S_CONDONE_PIN (1 << 6)
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#define F2S_USERMODE (1 << 2)
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struct fpgamgr_a10_softc {
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struct resource *res[2];
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bus_space_tag_t bst_data;
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bus_space_handle_t bsh_data;
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struct cdev *mgr_cdev;
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device_t dev;
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};
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static struct resource_spec fpgamgr_a10_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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fpga_wait_dclk_pulses(struct fpgamgr_a10_softc *sc, int npulses)
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{
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int tout;
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/* Clear done bit, if any */
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if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
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WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
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/* Request DCLK pulses */
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WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
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/* Wait finish */
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tout = 1000;
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while (tout > 0) {
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if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
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WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
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break;
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}
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tout--;
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DELAY(10);
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}
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if (tout == 0) {
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device_printf(sc->dev,
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"Error: dclkpulses wait timeout\n");
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return (1);
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}
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return (0);
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}
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static int
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fpga_open(struct cdev *dev, int flags __unused,
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int fmt __unused, struct thread *td __unused)
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{
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struct fpgamgr_a10_softc *sc;
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int tout;
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int msel;
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int reg;
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sc = dev->si_drv1;
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/* Step 1 */
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reg = READ4(sc, IMGCFG_STAT);
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if ((reg & F2S_USERMODE) == 0) {
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device_printf(sc->dev, "Error: invalid mode\n");
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return (ENXIO);
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};
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/* Step 2 */
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reg = READ4(sc, IMGCFG_STAT);
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msel = (reg & F2S_MSEL_M) >> F2S_MSEL_S;
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if ((msel != MSEL_PASSIVE_FAST) && \
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(msel != MSEL_PASSIVE_SLOW)) {
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device_printf(sc->dev,
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"Error: invalid msel %d\n", msel);
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return (ENXIO);
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};
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/*
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* Step 3.
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* TODO: add support for compressed, encrypted images.
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*/
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reg = READ4(sc, IMGCFG_CTRL_02);
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reg &= ~(CTRL_02_CDRATIO_M);
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WRITE4(sc, IMGCFG_CTRL_02, reg);
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reg = READ4(sc, IMGCFG_CTRL_02);
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reg &= ~CTRL_02_CFGWIDTH_32;
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WRITE4(sc, IMGCFG_CTRL_02, reg);
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/* Step 4. a */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg &= ~CTRL_01_S2F_PR_REQUEST;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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reg = READ4(sc, IMGCFG_CTRL_00);
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reg |= CTRL_00_NCONFIG;
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WRITE4(sc, IMGCFG_CTRL_00, reg);
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/* b */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg &= ~CTRL_01_S2F_NCE;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* c */
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reg = READ4(sc, IMGCFG_CTRL_02);
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reg |= CTRL_02_EN_CFG_CTRL;
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WRITE4(sc, IMGCFG_CTRL_02, reg);
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/* d */
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reg = READ4(sc, IMGCFG_CTRL_00);
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reg &= ~S2F_CONDONE_OE;
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reg &= ~S2F_NSTATUS_OE;
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reg |= CTRL_00_NCONFIG;
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reg |= CTRL_00_NENABLE_NSTATUS;
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reg |= CTRL_00_NENABLE_CONDONE;
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reg &= ~CTRL_00_NENABLE_NCONFIG;
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WRITE4(sc, IMGCFG_CTRL_00, reg);
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/* Step 5 */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg &= ~CTRL_01_S2F_NENABLE_CONFIG;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* Step 6 */
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fpga_wait_dclk_pulses(sc, 0x100);
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/* Step 7. a */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg |= CTRL_01_S2F_PR_REQUEST;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* b, c */
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fpga_wait_dclk_pulses(sc, 0x7ff);
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/* Step 8 */
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tout = 10;
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while (tout--) {
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reg = READ4(sc, IMGCFG_STAT);
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if (reg & F2S_PR_ERROR) {
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device_printf(sc->dev,
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"Error: PR failed on open.\n");
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return (ENXIO);
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}
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if (reg & F2S_PR_READY) {
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break;
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}
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}
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if (tout == 0) {
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device_printf(sc->dev,
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"Error: Timeout waiting PR ready bit.\n");
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return (ENXIO);
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}
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return (0);
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}
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static int
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fpga_close(struct cdev *dev, int flags __unused,
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int fmt __unused, struct thread *td __unused)
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{
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struct fpgamgr_a10_softc *sc;
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int tout;
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int reg;
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sc = dev->si_drv1;
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/* Step 10 */
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tout = 10;
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while (tout--) {
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reg = READ4(sc, IMGCFG_STAT);
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if (reg & F2S_PR_ERROR) {
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device_printf(sc->dev,
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"Error: PR failed.\n");
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return (ENXIO);
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}
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if (reg & F2S_PR_DONE) {
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break;
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}
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}
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/* Step 11 */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg &= ~CTRL_01_S2F_PR_REQUEST;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* Step 12, 13 */
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fpga_wait_dclk_pulses(sc, 0x100);
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/* Step 14 */
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reg = READ4(sc, IMGCFG_CTRL_02);
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reg &= ~CTRL_02_EN_CFG_CTRL;
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WRITE4(sc, IMGCFG_CTRL_02, reg);
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/* Step 15 */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg |= CTRL_01_S2F_NCE;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* Step 16 */
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reg = READ4(sc, IMGCFG_CTRL_01);
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reg |= CTRL_01_S2F_NENABLE_CONFIG;
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WRITE4(sc, IMGCFG_CTRL_01, reg);
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/* Step 17 */
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reg = READ4(sc, IMGCFG_STAT);
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if ((reg & F2S_USERMODE) == 0) {
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device_printf(sc->dev,
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"Error: invalid mode\n");
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return (ENXIO);
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};
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if ((reg & F2S_CONDONE_PIN) == 0) {
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device_printf(sc->dev,
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"Error: configuration not done\n");
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return (ENXIO);
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};
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if ((reg & F2S_NSTATUS_PIN) == 0) {
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device_printf(sc->dev,
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"Error: nstatus pin\n");
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return (ENXIO);
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};
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return (0);
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}
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static int
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fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
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{
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struct fpgamgr_a10_softc *sc;
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uint32_t buffer;
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sc = dev->si_drv1;
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/*
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* Step 9.
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* Device supports 4-byte writes only.
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*/
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while (uio->uio_resid >= 4) {
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uiomove(&buffer, 4, uio);
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bus_space_write_4(sc->bst_data, sc->bsh_data,
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0x0, buffer);
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}
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switch (uio->uio_resid) {
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case 3:
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uiomove(&buffer, 3, uio);
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buffer &= 0xffffff;
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bus_space_write_4(sc->bst_data, sc->bsh_data,
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0x0, buffer);
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break;
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case 2:
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uiomove(&buffer, 2, uio);
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buffer &= 0xffff;
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bus_space_write_4(sc->bst_data, sc->bsh_data,
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0x0, buffer);
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break;
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case 1:
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uiomove(&buffer, 1, uio);
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buffer &= 0xff;
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bus_space_write_4(sc->bst_data, sc->bsh_data,
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0x0, buffer);
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break;
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default:
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break;
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};
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return (0);
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}
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static int
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fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
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struct thread *td)
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{
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return (0);
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}
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static struct cdevsw fpga_cdevsw = {
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.d_version = D_VERSION,
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.d_open = fpga_open,
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.d_close = fpga_close,
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.d_write = fpga_write,
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.d_ioctl = fpga_ioctl,
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.d_name = "FPGA Manager",
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};
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static int
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fpgamgr_a10_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "altr,socfpga-a10-fpga-mgr"))
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return (ENXIO);
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device_set_desc(dev, "Arria 10 FPGA Manager");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fpgamgr_a10_attach(device_t dev)
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{
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struct fpgamgr_a10_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, fpgamgr_a10_spec, sc->res)) {
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device_printf(dev, "Could not allocate resources.\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst_data = rman_get_bustag(sc->res[1]);
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sc->bsh_data = rman_get_bushandle(sc->res[1]);
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sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
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0600, "fpga%d", device_get_unit(sc->dev));
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if (sc->mgr_cdev == NULL) {
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device_printf(dev, "Failed to create character device.\n");
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return (ENXIO);
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}
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sc->mgr_cdev->si_drv1 = sc;
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return (0);
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}
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static device_method_t fpgamgr_a10_methods[] = {
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DEVMETHOD(device_probe, fpgamgr_a10_probe),
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DEVMETHOD(device_attach, fpgamgr_a10_attach),
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{ 0, 0 }
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};
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static driver_t fpgamgr_a10_driver = {
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"fpgamgr_a10",
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fpgamgr_a10_methods,
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sizeof(struct fpgamgr_a10_softc),
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};
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static devclass_t fpgamgr_a10_devclass;
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DRIVER_MODULE(fpgamgr_a10, simplebus, fpgamgr_a10_driver,
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fpgamgr_a10_devclass, 0, 0);
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