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Tentatively apply https://reviews.llvm.org/D78877 (by Dave Green):

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[ARM] Only produce qadd8b under hasV6Ops

  When compiling for a arm5te cpu from clang, the +dsp attribute is
  set. This meant we could try and generate qadd8 instructions where we
  would end up having no pattern. I've changed the condition here to be
  hasV6Ops && hasDSP, which is what other parts of ARMISelLowering seem
  to use for similar instructions.

  Fixed PR45677.

This fixes "fatal error: error in backend: Cannot select: t37: i32 =
ARMISD::QADD8b t43, t44" when compiling sys/dev/sound/pcm/feeder_mixer.c
for armv5. For some reason we do not encounter this on head, but this
error popped up while building universes for stable/12.

MFC after:	3 days
This commit is contained in:
Dimitry Andric 2020-04-26 19:17:45 +00:00
parent 55f57ca9ac
commit 702995b2a5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=360350
1 changed files with 1 additions and 1 deletions
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2
contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -4549,7 +4549,7 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
EVT VT = Op.getValueType();
if (!Subtarget->hasDSP())
if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
return SDValue();
if (!VT.isSimple())
return SDValue();