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amd64: Define and decode new AMD64 feature bits

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These are documented in revisions 3.32 of the public AMD64 Vol. 2 and
revision 3.28 of Vol. 3, published October and September 2019, respectively.
This commit is contained in:
Conrad Meyer 2019-10-30 01:41:14 +00:00
parent a4d5fcadd8
commit 706bc29b7b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=354162
2 changed files with 9 additions and 1 deletions
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5
sys/x86/include/specialreg.h
View File

@ -71,6 +71,7 @@
#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
#define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
#define CR4_PCIDE 0x00020000 /* Enable Context ID */
@ -90,6 +91,7 @@
#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
#define EFER_TCE 0x000008000 /* Translation Cache Extension */
#define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */
/*
* Intel Extended Features registers
@ -384,6 +386,9 @@
#define AMDFEID_CLZERO 0x00000001
#define AMDFEID_IRPERF 0x00000002
#define AMDFEID_XSAVEERPTR 0x00000004
#define AMDFEID_RDPRU 0x00000004
#define AMDFEID_MCOMMIT 0x00000100
#define AMDFEID_WBNOINVD 0x00000200
#define AMDFEID_IBPB 0x00001000
#define AMDFEID_IBRS 0x00004000
#define AMDFEID_STIBP 0x00008000

5
sys/x86/x86/identcpu.c
View File

@ -1067,6 +1067,9 @@ printcpuinfo(void)
"\001CLZERO"
"\002IRPerf"
"\003XSaveErPtr"
"\005RDPRU"
"\011MCOMMIT"
"\012WBNOINVD"
"\015IBPB"
"\017IBRS"
"\020STIBP"
@ -2355,7 +2358,7 @@ print_svm_info(void)
"\017<b14>"
"\020V_VMSAVE_VMLOAD"
"\021vGIF"
"\022<b17>"
"\022GMET" /* Guest Mode Execute Trap */
"\023<b18>"
"\024<b19>"
"\025<b20>"