Preparation work for supporting the AR91xx and AR724x.

* Implement a SoC probe function, from Linux, which determines the
  SoC family, type and revision. This only probes the AR71xx series
  SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
  system frequencies) into using the cpuops introduced in an earlier commit.
  Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
  Ethernet PLL setup, other things I've likely missed) will be introduced in
  subsequent commits.

Reviewed by:	imp@
Obtained from:	(partially) Linux

sys/mips/atheros/ar71xx_chip.c

@@ -0,0 +1,180 @@
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <machine/cpuregs.h>
+
+#include <mips/sentry5/s5reg.h>
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+ 
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+ 
+#include <net/ethernet.h>
+ 
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+ 
+#include <mips/atheros/ar71xxreg.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+/* XXX these should replace the current definitions in ar71xxreg.h */
+/* XXX perhaps an ar71xx_chip.h header file? */
+#define AR71XX_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG       AR71XX_PLL_CPU_BASE + 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x14
+
+#define AR71XX_PLL_DIV_SHIFT            3
+#define AR71XX_PLL_DIV_MASK             0x1f
+#define AR71XX_CPU_DIV_SHIFT            16
+#define AR71XX_CPU_DIV_MASK             0x3
+#define AR71XX_DDR_DIV_SHIFT            18
+#define AR71XX_DDR_DIV_MASK             0x3
+#define AR71XX_AHB_DIV_SHIFT            20
+#define AR71XX_AHB_DIV_MASK             0x7
+
+#define AR71XX_ETH0_PLL_SHIFT           17
+#define AR71XX_ETH1_PLL_SHIFT           19
+
+/* XXX these shouldn't be in here - this file is a per-chip file */
+/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
+uint32_t u_ar71xx_cpu_freq;
+uint32_t u_ar71xx_ahb_freq;
+uint32_t u_ar71xx_ddr_freq;
+
+static void
+ar71xx_chip_detect_mem_size(void)
+{
+}
+
+static void
+ar71xx_chip_detect_sys_frequency(void)
+{
+	uint32_t pll;
+	uint32_t freq;
+	uint32_t div;
+
+	pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
+
+	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
+	freq = div * AR71XX_BASE_FREQ;
+
+	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
+	u_ar71xx_cpu_freq = freq / div;
+
+	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
+	u_ar71xx_ddr_freq = freq / div;
+
+	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
+	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+}
+
+/*
+ * This does not lock the CPU whilst doing the work!
+ */
+static void
+ar71xx_chip_device_stop(uint32_t mask)
+{
+	uint32_t reg;
+
+	reg = ATH_READ_REG(AR71XX_RST_RESET);
+	ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
+}
+
+static void
+ar71xx_chip_device_start(uint32_t mask)
+{
+	uint32_t reg;
+
+	reg = ATH_READ_REG(AR71XX_RST_RESET);
+	ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
+}
+
+static int
+ar71xx_chip_device_stopped(uint32_t mask)
+{
+	uint32_t reg;
+
+	reg = ATH_READ_REG(AR71XX_RST_RESET);
+        return ((reg & mask) == mask);
+}
+
+static void
+ar71xx_chip_set_pll_ge0(int speed)
+{
+}
+
+static void
+ar71xx_chip_set_pll_ge1(int speed)
+{
+}
+
+static void
+ar71xx_chip_ddr_flush_ge0(void)
+{
+	ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
+}
+
+static void
+ar71xx_chip_ddr_flush_ge1(void)
+{
+	ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
+}
+
+static uint32_t
+ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
+{
+	return 0;
+}
+
+static void
+ar71xx_chip_init_usb_peripheral(void)
+{
+	ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+	DELAY(1000);
+
+	ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+	DELAY(1000);
+
+	ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
+	    USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
+	    USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
+
+	ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
+	    (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
+
+	DELAY(1000);
+}
+
+struct ar71xx_cpu_def ar71xx_chip_def = {
+	&ar71xx_chip_detect_mem_size,
+	&ar71xx_chip_detect_sys_frequency,
+	&ar71xx_chip_device_stop,
+	&ar71xx_chip_device_start,
+	&ar71xx_chip_device_stopped,
+	&ar71xx_chip_set_pll_ge0,
+	&ar71xx_chip_set_pll_ge1,
+	&ar71xx_chip_ddr_flush_ge0,
+	&ar71xx_chip_ddr_flush_ge1,
+	&ar71xx_chip_get_eth_pll,
+	NULL,
+	&ar71xx_chip_init_usb_peripheral,
+};

sys/mips/atheros/ar71xx_chip.h

@@ -0,0 +1,34 @@
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef	__AR71XX_CHIP_H__
+#define	__AR71XX_CHIP_H__
+
+extern struct ar71xx_cpu_def ar71xx_chip_def;
+
+#endif

sys/mips/atheros/ar71xx_machdep.c

@@ -57,6 +57,9 @@ __FBSDID("$FreeBSD$");
 
 #include <mips/atheros/ar71xxreg.h>
 
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
 extern char edata[], end[];
 
 uint32_t ar711_base_mac[ETHER_ADDR_LEN];
@@ -202,11 +205,21 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused,
 	 * should be called first.
 	 */
 	init_param1();
+
+	/* Detect the system type - this is needed for subsequent chipset-specific calls */
+	ar71xx_detect_sys_type();
+	ar71xx_detect_sys_frequency();
+
 	platform_counter_freq = ar71xx_cpu_freq();
 	mips_timer_init_params(platform_counter_freq, 1);
 	cninit();
 	init_static_kenv(boot1_env, sizeof(boot1_env));
 
+	printf("CPU platform: %s\n", ar71xx_get_system_type());
+	printf("CPU Frequency=%d MHz\n", u_ar71xx_cpu_freq / 1000000);
+	printf("CPU DDR Frequency=%d MHz\n", u_ar71xx_ddr_freq / 1000000);
+	printf("CPU AHB Frequency=%d MHz\n", u_ar71xx_ahb_freq / 1000000); 
+
 	printf("platform frequency: %lld\n", platform_counter_freq);
 	printf("arguments: \n");
 	printf("  a0 = %08x\n", a0);

sys/mips/atheros/ar71xx_setup.c

@@ -0,0 +1,119 @@
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <machine/cpuregs.h>
+
+#include <mips/sentry5/s5reg.h>
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+ 
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+ 
+#include <net/ethernet.h>
+ 
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+ 
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_setup.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+
+#define	AR71XX_SYS_TYPE_LEN		128
+
+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
+enum ar71xx_soc_type ar71xx_soc;
+struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
+
+void
+ar71xx_detect_sys_type(void)
+{
+	char *chip = "????";
+	uint32_t id;
+	uint32_t major;
+	uint32_t minor;
+	uint32_t rev = 0;
+
+	id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		ar71xx_cpu_ops	= &ar71xx_chip_def;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			ar71xx_soc = AR71XX_SOC_AR7130;
+			chip = "7130";
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			ar71xx_soc = AR71XX_SOC_AR7141;
+			chip = "7141";
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			ar71xx_soc = AR71XX_SOC_AR7161;
+			chip = "7161";
+			break;
+		}
+		break;
+
+	default:
+		panic("ar71xx: unknown chip id:0x%08x\n", id);
+	}
+
+	sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
+}
+
+const char *
+ar71xx_get_system_type(void)
+{
+	return ar71xx_sys_type;
+}
+

sys/mips/atheros/ar71xx_setup.h

@@ -0,0 +1,48 @@
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef	__AR71XX_SETUP_H__
+#define	__AR71XX_SETUP_H__
+
+enum ar71xx_soc_type {
+	AR71XX_SOC_UNKNOWN,
+	AR71XX_SOC_AR7130,
+	AR71XX_SOC_AR7141,
+	AR71XX_SOC_AR7161,
+	AR71XX_SOC_AR7240,
+	AR71XX_SOC_AR7241,
+	AR71XX_SOC_AR7242,
+	AR71XX_SOC_AR9130,
+	AR71XX_SOC_AR9132
+};
+extern enum ar71xx_soc_type ar71xx_soc;   
+
+extern void ar71xx_detect_sys_type(void);
+extern const char *ar71xx_get_system_type(void);
+
+#endif

sys/mips/atheros/ar71xx_wdog.c

@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/sysctl.h>
 
 #include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
 
 struct ar71xx_wdog_softc {
 	device_t dev;

sys/mips/atheros/ar71xxreg.h

@@ -161,6 +161,7 @@
 #define			GPIO_FUNC_USB_CLK_EN    (0)
 
 #define	AR71XX_BASE_FREQ		40000000
+#define	AR71XX_PLL_CPU_BASE		0x18050000
 #define	AR71XX_PLL_CPU_CONFIG		0x18050000
 #define		PLL_SW_UPDATE			(1 << 31)
 #define		PLL_LOCKED			(1 << 30)
@@ -235,6 +236,23 @@
 #define		RST_RESET_PCI_BUS	(1 <<  1)
 #define		RST_RESET_PCI_CORE	(1 <<  0)
 
+/* Chipset revision details */
+#define	AR71XX_RST_RESET_REG_REV_ID	0x18060090
+#define		REV_ID_MAJOR_MASK	0xfff0
+#define		REV_ID_MAJOR_AR71XX	0x00a0
+#define		REV_ID_MAJOR_AR913X	0x00b0
+#define		REV_ID_MAJOR_AR7240	0x00c0
+#define		REV_ID_MAJOR_AR7241	0x0100
+#define		REV_ID_MAJOR_AR7242	0x1100
+
+/* AR71XX chipset revision details */
+#define		AR71XX_REV_ID_MINOR_MASK	0x3
+#define		AR71XX_REV_ID_MINOR_AR7130	0x0
+#define		AR71XX_REV_ID_MINOR_AR7141	0x1
+#define		AR71XX_REV_ID_MINOR_AR7161	0x2
+#define		AR71XX_REV_ID_REVISION_MASK	0x3
+#define		AR71XX_REV_ID_REVISION_SHIFT	2
+
 /*
  * GigE adapters region
  */
@@ -459,38 +477,6 @@
 #define ATH_WRITE_REG(reg, val) \
     *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
 
-static inline uint64_t
-ar71xx_cpu_freq(void)
-{
-        uint32_t pll_config, div;
-        uint64_t freq;
-
-        /* PLL freq */
-        pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG);
-        div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1;
-        freq = div * AR71XX_BASE_FREQ;
-        /* CPU freq */
-        div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK)
-            + 1;
-        freq = freq / div;
-
-	return (freq);
-}
-
-static inline uint64_t
-ar71xx_ahb_freq(void)
-{
-        uint32_t pll_config, div;
-        uint64_t freq;
-
-        /* PLL freq */
-        pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG);
-        /* AHB freq */
-        div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2;
-        freq = ar71xx_cpu_freq() / div;
-	return (freq);
-}
-
 static inline void
 ar71xx_ddr_flush(uint32_t reg)
 { 

sys/mips/atheros/files.ar71xx

@@ -15,3 +15,5 @@ mips/atheros/uart_cpu_ar71xx.c	optional uart
 mips/atheros/ar71xx_bus_space_reversed.c	standard
 mips/mips/intr_machdep.c        standard
 mips/mips/tick.c		standard
+mips/atheros/ar71xx_setup.c	standard
+mips/atheros/ar71xx_chip.c	standard

sys/mips/atheros/uart_bus_ar71xx.c

@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/uart/uart_bus.h>
 
 #include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
 
 #include "uart_if.h"
 

sys/mips/atheros/uart_cpu_ar71xx.c

@@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/uart/uart_cpu.h>
 
 #include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
 #include <mips/atheros/ar71xx_bus_space_reversed.h>
 
 bus_space_tag_t uart_bus_space_io;