Add hardware MAC statistics support. This statistics could be
extracted from dev.vge.%d.stats sysctl node.
This commit is contained in:
Pyun YongHyeon
parent
84bc0aa3b0
commit
7129fb20d6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=200615
@ -93,6 +93,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/module.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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@ -131,6 +132,13 @@ MODULE_DEPEND(vge, miibus, 1, 1, 1);
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static int msi_disable = 0;
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TUNABLE_INT("hw.vge.msi_disable", &msi_disable);
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/*
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* The SQE error counter of MIB seems to report bogus value.
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* Vendor's workaround does not seem to work on PCIe based
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* controllers. Disable it until we find better workaround.
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*/
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#undef VGE_ENABLE_SQEERR
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/*
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* Various supported device vendors/types and their names.
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*/
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@ -183,7 +191,10 @@ static void vge_rxfilter(struct vge_softc *);
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static void vge_setvlan(struct vge_softc *);
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static void vge_start(struct ifnet *);
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static void vge_start_locked(struct ifnet *);
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static void vge_stats_clear(struct vge_softc *);
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static void vge_stats_update(struct vge_softc *);
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static void vge_stop(struct vge_softc *);
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static void vge_sysctl_node(struct vge_softc *);
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static int vge_tx_list_init(struct vge_softc *);
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static void vge_txeof(struct vge_softc *);
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static void vge_watchdog(void *);
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@ -1057,6 +1068,7 @@ vge_attach(device_t dev)
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else
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sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
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VGE_MIICFG_PHYADDR;
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vge_sysctl_node(sc);
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error = vge_dma_alloc(sc);
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if (error)
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goto fail;
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@ -1698,7 +1710,6 @@ vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
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if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
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vge_rxeof(sc, count);
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ifp->if_ierrors++;
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CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
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CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
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}
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@ -2034,7 +2045,8 @@ vge_init_locked(struct vge_softc *sc)
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return;
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}
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vge_tx_list_init(sc);
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/* Clear MAC statistics. */
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vge_stats_clear(sc);
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/* Set our station address */
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]);
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@ -2358,6 +2370,7 @@ vge_watchdog(void *arg)
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sc = arg;
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VGE_LOCK_ASSERT(sc);
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vge_stats_update(sc);
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callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
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if (sc->vge_timer == 0 || --sc->vge_timer > 0)
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return;
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@ -2396,6 +2409,7 @@ vge_stop(struct vge_softc *sc)
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CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
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CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
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vge_stats_update(sc);
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VGE_CHAIN_RESET(sc);
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vge_txeof(sc);
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vge_freebufs(sc);
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@ -2469,3 +2483,223 @@ vge_shutdown(device_t dev)
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return (0);
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}
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#define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
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SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
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static void
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vge_sysctl_node(struct vge_softc *sc)
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{
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid_list *child, *parent;
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struct sysctl_oid *tree;
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struct vge_hw_stats *stats;
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stats = &sc->vge_stats;
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ctx = device_get_sysctl_ctx(sc->vge_dev);
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child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev));
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tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
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NULL, "VGE statistics");
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parent = SYSCTL_CHILDREN(tree);
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/* Rx statistics. */
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tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
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NULL, "RX MAC statistics");
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child = SYSCTL_CHILDREN(tree);
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames",
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&stats->rx_frames, "frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
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&stats->rx_good_frames, "Good frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
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&stats->rx_fifo_oflows, "FIFO overflows");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "runts",
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&stats->rx_runts, "Too short frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs",
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&stats->rx_runts_errs, "Too short frames with errors");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
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&stats->rx_pkts_64, "64 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
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&stats->rx_pkts_65_127, "65 to 127 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
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&stats->rx_pkts_128_255, "128 to 255 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
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&stats->rx_pkts_256_511, "256 to 511 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
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&stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
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&stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
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&stats->rx_pkts_1519_max, "1519 to max frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs",
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&stats->rx_pkts_1519_max_errs, "1519 to max frames with error");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo",
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&stats->rx_jumbos, "Jumbo frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs",
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&stats->rx_crcerrs, "CRC errors");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
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&stats->rx_pause_frames, "CRC errors");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
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&stats->rx_alignerrs, "Alignment errors");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs",
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&stats->rx_nobufs, "Frames with no buffer event");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs",
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&stats->rx_symerrs, "Frames with symbol errors");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
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&stats->rx_lenerrs, "Frames with length mismatched");
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/* Tx statistics. */
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tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
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NULL, "TX MAC statistics");
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child = SYSCTL_CHILDREN(tree);
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VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
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&stats->tx_good_frames, "Good frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
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&stats->tx_pkts_64, "64 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
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&stats->tx_pkts_65_127, "65 to 127 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
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&stats->tx_pkts_128_255, "128 to 255 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
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&stats->tx_pkts_256_511, "256 to 511 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
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&stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
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&stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo",
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&stats->tx_jumbos, "Jumbo frames");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "colls",
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&stats->tx_colls, "Collisions");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
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&stats->tx_latecolls, "Late collisions");
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VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
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&stats->tx_pause, "Pause frames");
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#ifdef VGE_ENABLE_SQEERR
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VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs",
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&stats->tx_sqeerrs, "SQE errors");
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#endif
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/* Clear MAC statistics. */
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vge_stats_clear(sc);
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}
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#undef VGE_SYSCTL_STAT_ADD32
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static void
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vge_stats_clear(struct vge_softc *sc)
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{
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int i;
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VGE_LOCK_ASSERT(sc);
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CSR_WRITE_1(sc, VGE_MIBCSR,
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CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE);
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CSR_WRITE_1(sc, VGE_MIBCSR,
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CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR);
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for (i = VGE_TIMEOUT; i > 0; i--) {
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DELAY(1);
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if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0)
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break;
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}
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if (i == 0)
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device_printf(sc->vge_dev, "MIB clear timed out!\n");
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CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &
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~VGE_MIBCSR_FREEZE);
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}
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static void
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vge_stats_update(struct vge_softc *sc)
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{
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struct vge_hw_stats *stats;
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struct ifnet *ifp;
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uint32_t mib[VGE_MIB_CNT], val;
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int i;
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VGE_LOCK_ASSERT(sc);
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stats = &sc->vge_stats;
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ifp = sc->vge_ifp;
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CSR_WRITE_1(sc, VGE_MIBCSR,
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CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH);
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for (i = VGE_TIMEOUT; i > 0; i--) {
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DELAY(1);
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if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0)
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break;
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}
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if (i == 0) {
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device_printf(sc->vge_dev, "MIB counter dump timed out!\n");
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vge_stats_clear(sc);
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return;
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}
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bzero(mib, sizeof(mib));
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reset_idx:
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/* Set MIB read index to 0. */
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CSR_WRITE_1(sc, VGE_MIBCSR,
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CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI);
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for (i = 0; i < VGE_MIB_CNT; i++) {
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val = CSR_READ_4(sc, VGE_MIBDATA);
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if (i != VGE_MIB_DATA_IDX(val)) {
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/* Reading interrupted. */
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goto reset_idx;
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}
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mib[i] = val & VGE_MIB_DATA_MASK;
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}
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/* Rx stats. */
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stats->rx_frames += mib[VGE_MIB_RX_FRAMES];
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stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES];
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stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS];
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stats->rx_runts += mib[VGE_MIB_RX_RUNTS];
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stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS];
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stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64];
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stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127];
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stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255];
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stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511];
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stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023];
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stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518];
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stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX];
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stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS];
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stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS];
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stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS];
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stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE];
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stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS];
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stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS];
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stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS];
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stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS];
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/* Tx stats. */
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stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES];
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stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64];
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stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127];
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stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255];
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stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511];
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stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023];
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stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518];
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stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS];
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stats->tx_colls += mib[VGE_MIB_TX_COLLS];
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stats->tx_pause += mib[VGE_MIB_TX_PAUSE];
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#ifdef VGE_ENABLE_SQEERR
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stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS];
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#endif
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stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS];
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/* Update counters in ifnet. */
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ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES];
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ifp->if_collisions += mib[VGE_MIB_TX_COLLS] +
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mib[VGE_MIB_TX_LATECOLLS];
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ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] +
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mib[VGE_MIB_TX_LATECOLLS];
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ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES];
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ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] +
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mib[VGE_MIB_RX_RUNTS] +
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mib[VGE_MIB_RX_RUNTS_ERRS] +
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mib[VGE_MIB_RX_CRCERRS] +
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mib[VGE_MIB_RX_ALIGNERRS] +
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mib[VGE_MIB_RX_NOBUFS] +
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mib[VGE_MIB_RX_SYMERRS] +
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mib[VGE_MIB_RX_LENERRS];
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}
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@ -301,7 +301,7 @@
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VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \
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VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \
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VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \
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VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0)
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VGE_ISR_TIMER0)
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/* Interrupt mask register */
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@ -543,6 +543,54 @@
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#define VGE_TXBLOCK_128PKTS 0x08
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#define VGE_TXBLOCK_8PKTS 0x0C
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/* MIB control/status register */
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#define VGE_MIBCSR_CLR 0x01
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#define VGE_MIBCSR_RINI 0x02
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#define VGE_MIBCSR_FLUSH 0x04
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#define VGE_MIBCSR_FREEZE 0x08
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#define VGE_MIBCSR_HI_80 0x00
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#define VGE_MIBCSR_HI_C0 0x10
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#define VGE_MIBCSR_BISTGO 0x40
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#define VGE_MIBCSR_BISTOK 0x80
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/* MIB data index. */
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#define VGE_MIB_RX_FRAMES 0
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#define VGE_MIB_RX_GOOD_FRAMES 1
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#define VGE_MIB_TX_GOOD_FRAMES 2
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#define VGE_MIB_RX_FIFO_OVERRUNS 3
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#define VGE_MIB_RX_RUNTS 4
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#define VGE_MIB_RX_RUNTS_ERRS 5
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#define VGE_MIB_RX_PKTS_64 6
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#define VGE_MIB_TX_PKTS_64 7
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#define VGE_MIB_RX_PKTS_65_127 8
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#define VGE_MIB_TX_PKTS_65_127 9
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#define VGE_MIB_RX_PKTS_128_255 10
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#define VGE_MIB_TX_PKTS_128_255 11
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#define VGE_MIB_RX_PKTS_256_511 12
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#define VGE_MIB_TX_PKTS_256_511 13
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#define VGE_MIB_RX_PKTS_512_1023 14
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#define VGE_MIB_TX_PKTS_512_1023 15
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#define VGE_MIB_RX_PKTS_1024_1518 16
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#define VGE_MIB_TX_PKTS_1024_1518 17
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#define VGE_MIB_TX_COLLS 18
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#define VGE_MIB_RX_CRCERRS 19
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#define VGE_MIB_RX_JUMBOS 20
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#define VGE_MIB_TX_JUMBOS 21
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#define VGE_MIB_RX_PAUSE 22
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#define VGE_MIB_TX_PAUSE 23
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#define VGE_MIB_RX_ALIGNERRS 24
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#define VGE_MIB_RX_PKTS_1519_MAX 25
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#define VGE_MIB_RX_PKTS_1519_MAX_ERRS 26
|
||||
#define VGE_MIB_TX_SQEERRS 27
|
||||
#define VGE_MIB_RX_NOBUFS 28
|
||||
#define VGE_MIB_RX_SYMERRS 29
|
||||
#define VGE_MIB_RX_LENERRS 30
|
||||
#define VGE_MIB_TX_LATECOLLS 31
|
||||
|
||||
#define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
|
||||
#define VGE_MIB_DATA_MASK 0x00FFFFFF
|
||||
#define VGE_MIB_DATA_IDX(x) ((x) >> 24)
|
||||
|
||||
/* EEPROM control/status register */
|
||||
|
||||
#define VGE_EECSR_EDO 0x01 /* data out pin */
|
||||
|
||||
@ -130,6 +130,42 @@ struct vge_ring_data {
|
||||
bus_addr_t vge_rx_ring_paddr;
|
||||
};
|
||||
|
||||
struct vge_hw_stats {
|
||||
uint32_t rx_frames;
|
||||
uint32_t rx_good_frames;
|
||||
uint32_t rx_fifo_oflows;
|
||||
uint32_t rx_runts;
|
||||
uint32_t rx_runts_errs;
|
||||
uint32_t rx_pkts_64;
|
||||
uint32_t rx_pkts_65_127;
|
||||
uint32_t rx_pkts_128_255;
|
||||
uint32_t rx_pkts_256_511;
|
||||
uint32_t rx_pkts_512_1023;
|
||||
uint32_t rx_pkts_1024_1518;
|
||||
uint32_t rx_pkts_1519_max;
|
||||
uint32_t rx_pkts_1519_max_errs;
|
||||
uint32_t rx_jumbos;
|
||||
uint32_t rx_crcerrs;
|
||||
uint32_t rx_pause_frames;
|
||||
uint32_t rx_alignerrs;
|
||||
uint32_t rx_nobufs;
|
||||
uint32_t rx_symerrs;
|
||||
uint32_t rx_lenerrs;
|
||||
|
||||
uint32_t tx_good_frames;
|
||||
uint32_t tx_pkts_64;
|
||||
uint32_t tx_pkts_65_127;
|
||||
uint32_t tx_pkts_128_255;
|
||||
uint32_t tx_pkts_256_511;
|
||||
uint32_t tx_pkts_512_1023;
|
||||
uint32_t tx_pkts_1024_1518;
|
||||
uint32_t tx_jumbos;
|
||||
uint32_t tx_colls;
|
||||
uint32_t tx_pause;
|
||||
uint32_t tx_sqeerrs;
|
||||
uint32_t tx_latecolls;
|
||||
};
|
||||
|
||||
struct vge_softc {
|
||||
struct ifnet *vge_ifp; /* interface info */
|
||||
device_t vge_dev;
|
||||
@ -152,6 +188,7 @@ struct vge_softc {
|
||||
|
||||
struct vge_chain_data vge_cdata;
|
||||
struct vge_ring_data vge_rdata;
|
||||
struct vge_hw_stats vge_stats;
|
||||
|
||||
int suspended; /* 0 = normal 1 = suspended */
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user