These files are unused, so remove them for now. If they turn out to
be needed later, they can be restored.
This commit is contained in:
Warner Losh
parent
4788234366
commit
71a36ddcef
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=178745
@ -1,310 +0,0 @@
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/*-
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* Copyright (c) 2001, 2005, Juniper Networks, Inc.
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* All rights reserved.
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*
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* Truman Joe, March 2001.
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*
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* cp0.h -- MIPS coprocessor 0 defines.
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*
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* JNPR: cp0.h,v 1.4 2006/12/02 09:53:40 katta
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* $FreeBSD$
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*/
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/*
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* This header file is updated from:
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* pfe/include/mips/cp0.h
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*/
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/*
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* Note: Registers and bit descriptions that do NOT adhere to
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* the MIPS64 descriptions as defined in the "MIPS64
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* Architecture for Programmers, Volume III: The MIPS64
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* Privileged Resource Architecture" document (doc # MD00091)
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* are considered to be processor specific and must have the
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* processor type included in the constant name.
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*/
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#ifndef _MACHINE_CP0_H_
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#define _MACHINE_CP0_H_
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#ifndef ASMINCLUDE
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/* Coprocessor 0 set 0 */
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#define C0_INDEX 0
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#define C0_RANDOM 1
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#define C0_ENTRYLO0 2
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#define C0_ENTRYLO1 3
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#define C0_CONTEXT 4
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#define C0_PAGEMASK 5
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#define C0_WIRED 6
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#define R7K_C0_INFO 7
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#define R9K_C0_INFO 7
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#define C0_BADVADDR 8
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#define C0_COUNT 9
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#define C0_ENTRYHI 10
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#define C0_COMPARE 11
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#define C0_STATUS 12
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#define C0_CAUSE 13
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#define C0_EPC 14
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#define C0_PRID 15
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#define C0_CONFIG 16
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#define C0_LLADDR 17
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#define C0_WATCH1 18
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#define C0_WATCH2 19
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#define C0_XCONTEXT 20
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#define R7K_C0_PERFCTL 22
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#define C0_DEBUG 23
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#define R9K_C0_JTAG_DEBUG 23
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#define R7K_C0_WATCHMASK 24
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#define R9K_C0_JTAG_DEPC 24
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#define C0_PERFCOUNT 25
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#define C0_ECC 26
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#define C0_CACHEERR 27
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#define C0_TAGLO 28
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#define C0_TAGHI 29
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#define C0_ERROREPC 30
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#define R9K_C0_JTAG_DESAV 31
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/* Coprocessor 0 Set 1 */
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#define R7K_C0_1_IPLLO 18
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#define R7K_C0_1_IPLHI 19
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#define R7K_C0_1_INTCTL 20
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#define R9K_C0_1_TBCTL 22
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#define R9K_C0_1_TBIDX 24
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#define R9K_C0_1_TBOUT 25
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#define R7K_C0_1_DERRADDR0 26
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#define R7K_C0_1_DERRADDR1 27
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#else /* ASMINCLUDE */
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/* Coprocessor 0 set 0 */
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#define C0_INDEX $0
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#define C0_RANDOM $1
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#define C0_ENTRYLO0 $2
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#define C0_ENTRYLO1 $3
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#define C0_CONTEXT $4
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#define C0_PAGEMASK $5
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#define C0_WIRED $6
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#define C0_INFO $7
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#define C0_BADVADDR $8
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#define C0_COUNT $9
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#define C0_ENTRYHI $10
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#define C0_COMPARE $11
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#define C0_STATUS $12
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#define C0_CAUSE $13
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#define C0_EPC $14
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#define C0_PRID $15
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#define C0_CONFIG $16
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#define C0_LLADDR $17
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#define C0_WATCH1 $18
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#define C0_WATCH2 $19
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#define C0_XCONTEXT $20
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#define R7K_C0_PERFCTL $22
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#define C0_DEBUG $23
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#define R9K_C0_JTAG_DEBUG $23
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#define R7K_C0_WATCHMASK $24
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#define R9K_C0_JTAG_DEPC $24
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#define C0_PERFCOUNT $25
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#define C0_ECC $26
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#define C0_CACHEERR $27
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#define C0_TAGLO $28
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#define C0_TAGHI $29
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#define C0_ERROREPC $30
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#define R9K_C0_JTAG_DESAV $31
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/* Coprocessor 0 Set 1 */
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#define R7K_C0_1_IPLLO $18
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#define R7K_C0_1_IPLHI $19
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#define R7K_C0_1_INTCTL $20
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#define R7K_C0_1_DERRADDR0 $26
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#define R7K_C0_1_DERRADDR1 $27
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#endif /* ASMINCLUDE */
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/* CACHE INSTR OPERATIONS */
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#define CACHE_I 0
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#define CACHE_D 1
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#define CACHE_T 2
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#define CACHE_S 3
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#define INDEX_INVL_I ((0 << 2) | CACHE_I)
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#define INDEX_WB_INVL_D ((0 << 2) | CACHE_D)
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#define FLASH_INVL_T ((0 << 2) | CACHE_T)
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#define INDEX_WB_INVL_S ((0 << 2) | CACHE_S)
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#define INDEX_LD_TAG_I ((1 << 2) | CACHE_I)
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#define INDEX_LD_TAG_D ((1 << 2) | CACHE_D)
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#define INDEX_LD_TAG_T ((1 << 2) | CACHE_T)
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#define INDEX_LD_TAG_S ((1 << 2) | CACHE_S)
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#define INDEX_ST_TAG_I ((2 << 2) | CACHE_I)
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#define INDEX_ST_TAG_D ((2 << 2) | CACHE_D)
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#define INDEX_ST_TAG_T ((2 << 2) | CACHE_T)
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#define INDEX_ST_TAG_S ((2 << 2) | CACHE_S)
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#define CREATE_DRTY_EXCL_D ((3 << 2) | CACHE_D)
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#define HIT_INVL_I ((4 << 2) | CACHE_I)
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#define HIT_INVL_D ((4 << 2) | CACHE_D)
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#define HIT_INVL_S ((4 << 2) | CACHE_S)
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#define HIT_WB_INVL_D ((5 << 2) | CACHE_D)
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#define FILL_I ((5 << 2) | CACHE_I)
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#define HIT_WB_INVL_S ((5 << 2) | CACHE_S)
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#define PAGE_INVL_T ((5 << 2) | CACHE_T)
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#define HIT_WB_D ((6 << 2) | CACHE_D)
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#define HIT_WB_I ((6 << 2) | CACHE_I)
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#define HIT_WB_S ((6 << 2) | CACHE_S)
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/* CO_CONFIG bit definitions */
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#define R7K_CFG_TE (0x1 << 12) /* diff from MIPS64 standard */
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#define R7K_CFG_SE (0x1 << 3) /* diff from MIPS64 standard */
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#define R9K_CFG_SE (0x1 << 3) /* diff from MIPS64 standard */
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#define R9K_CFG_SC (0x1 << 31) /* diff from MIPS64 standard */
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#define CFG_K0_MASK (0x7 << 0)
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#define CFG_K0_UNC (0x2 << 0)
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#define CFG_K0_WB (0x3 << 0)
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#define R9K_CFG_K0_WT 0x0 /* Write thru */
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#define R9K_CFG_K0_WTWA 0x1 /* Write thru with write alloc */
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#define R9K_CFG_K0_UNCB 0x2 /* Uncached, blocking */
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#define R9K_CFG_K0_WB 0x3 /* Write Back */
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#define R9K_CFG_K0_CWBEA 0x4 /* Coherent WB wih exclusive alloc */
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#define R9K_CFG_K0_CWB 0x5 /* Coherent WB */
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#define R9K_CFG_K0_UNCNB 0x6 /* Uncached, nonblocking */
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#define R9K_CFG_K0_FPC 0x7 /* Fast Packet Cache (bypass 2nd cache) */
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/* Special C0_INFO bit descriptions for the R9K processor */
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#define R9K_INFO_AE (1 << 0) /* atomic SR_IE for R9K */
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#define R9K_INFO_64_TLB (1 << 29)/* R9K C0_INFO bit - chip has 64 TLB entries */
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/* CO_PAGEMASK bit definitions */
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/*
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* These look wierd because the 'size' used is twice what you
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* think it is, but remember that the MIPs TLB maps even odd
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* pages so that you need to acount for the 2x page size
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* R9K supports 256M pages (it has a 16 bit Mask field in the
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* PageMask register).
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*/
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#define PAGEMASK_256M ((0x20000000 - 1) & ~0x1fff) /* R9K only */
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#define PAGEMASK_64M ((0x08000000 - 1) & ~0x1fff) /* R9K only */
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#define PAGEMASK_16M ((0x02000000 - 1) & ~0x1fff)
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#define PAGEMASK_4M ((0x00800000 - 1) & ~0x1fff)
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#define PAGEMASK_1M ((0x00200000 - 1) & ~0x1fff)
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#define PAGEMASK_256K ((0x00080000 - 1) & ~0x1fff)
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#define PAGEMASK_64K ((0x00020000 - 1) & ~0x1fff)
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#define PAGEMASK_16K ((0x00008000 - 1) & ~0x1fff)
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#define PAGEMASK_4K ((0x00002000 - 1) & ~0x1fff)
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#define R9K_PAGEMASK 0xffff /* R9K has a 16 bit of PageMask reg */
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#define PAGEMASK_SHIFT 13
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/*
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* Cache Coherency Attributes
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* These are different for R7K and R9K
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*/
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#define R7K_TLB_COHERENCY_WTNA 0x0
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#define R7K_TLB_COHERENCY_WTWA 0x1
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#define R7K_TLB_COHERENCY_UNCBLK 0x2
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#define R7K_TLB_COHERENCY_WB 0x3
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#define R7K_TLB_COHERENCY_UNCNBLK 0x6
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#define R7K_TLB_COHERENCY_BYPASS 0x7
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#define ENTRYHI_ASID_MASK 0xff
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#define R9K_ENTRYHI_ASID_MASK 0xfff
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#define R7K_ENTRYHI_VPNMASK 0x7ffffff
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#define ENTRYHI_VPNSHIFT 13
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#define ENTRYHI_R_SHIFT 62
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#define R7K_ENTRYLO_PFNMASK 0xffffff
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#define ENTRYLO_PFNSHIFT 6
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#define ENTRYLO_C_SHIFT 3
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#define R9K_ENTRYHI_VPNMASK 0x7ffffff /* same as r7k */
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#define R9K_ENTRYLO_PFNMASK 0xffffff /* same as r7k */
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#define R9K_ENTRYLO_C_WTNWA (0x0 << 3) /* Cache NonCoher WriteThru No Alloc */
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#define R9K_ENTRYLO_C_WTWA (0x1 << 3) /* Cache NonCoher WriteThru Wr Alloc */
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#define R9K_ENTRYLO_C_UNCACHED (0x2 << 3) /* Uncached, blocking */
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#define R9K_ENTRYLO_C_CNONC_WB (0x3 << 3) /* Cacheable NonCoherent WriteBack */
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#define R9K_ENTRYLO_C_CCEXCLU (0x4 << 3) /* Cacheable Coherent Exclusive */
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#define R9K_ENTRYLO_C_CC_WB (0x5 << 3) /* Cacheable Coherent Write Back */
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#define R9K_ENTRYLO_C_UNCNBLK (0x6 << 3) /* Uncached, Nonblocking */
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#define R9K_ENTRYLO_C_FPC (0x7 << 3) /* Fast Packet Cache */
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#define R7K_ENTRYLO_C_WB (R7K_TLB_COHERENCY_WB << 3)
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#define R7K_ENTRYLO_C_UNCBLK (R7K_TLB_COHERENCY_UNCBLK << 3)
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#define R7K_ENTRYLO_C_UNCNBLK (R7K_TLB_COHERENCY_UNCNBLK << 3)
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#define R7K_ENTRYLO_C_BYPASS (R7K_TLB_COHERENCY_BYPASS << 3)
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#define ENTRYLO_D (0x1 << 2)
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#define ENTRYLO_V (0x1 << 1)
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#define ENTRYLO_G (0x1 << 0)
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/* C0_CAUSE bit definitions */
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#define CAUSE_BD (0x1 << 31)
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#define CAUSE_CE_SHIFT 28
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#define CAUSE_CE_MASK 3
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#define R7K_CAUSE_IV (0x1 << 24) /* different from MIPS64 standard */
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#define R9K_CAUSE_IV (0x1 << 24) /* different from MIPS64 standard */
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#define R9K_CAUSE_W1 (0x1 << 25) /* different from MIPS64 standard */
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#define R9K_CAUSE_W2 (0x1 << 26) /* different from MIPS64 standard */
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#define CAUSE_IV (0x1 << 23)
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#define CAUSE_WP (0x1 << 22)
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#define CAUSE_EXCCODE_MASK 0x1f
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#define CAUSE_EXCCODE_SHIFT 2
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#define CAUSE_IP_MASK 0xff
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#define R7K_CAUSE_IP_MASK 0xffff /* different from MIPS64 standard */
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#define R9K_CAUSE_IP_MASK 0xffff /* different from MIPS64 standard */
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#define CAUSE_IP_SHIFT 8
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#define CAUSE_IP(num) (0x1 << ((num) + CAUSE_IP_SHIFT))
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#define CAUSE_EXCCODE_INT (0 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_MOD (1 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_TLBL (2 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_TLBS (3 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_ADEL (4 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_ADES (5 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_IBE (6 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_DBE (7 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_SYS (8 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_BP (9 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_RI (10 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_CPU (11 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_OV (12 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_TR (13 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_FPE (15 << CAUSE_EXCCODE_SHIFT)
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#define R7K_CAUSE_EXCCODE_IWE (16 << CAUSE_EXCCODE_SHIFT) /* r7k implementation */
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#define CAUSE_EXCCODE_C2E (18 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_MDMX (22 << CAUSE_EXCCODE_SHIFT)
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#define R7K_CAUSE_EXCCODE_DWE (23 << CAUSE_EXCCODE_SHIFT) /* diff from standard */
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#define CAUSE_EXCCODE_WATCH (23 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_MACH_CHK (24 << CAUSE_EXCCODE_SHIFT)
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#define CAUSE_EXCCODE_CACHE_ERR (30 << CAUSE_EXCCODE_SHIFT)
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/* C0_PRID bit definitions */
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#define PRID_GET_REV(val) ((val) & 0xff)
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#define PRID_GET_RPID(val) (((val) >> 8) & 0xff)
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#define R9K_PRID_GET_IMP(val) (((val) >> 8) & 0xff)
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#define PRID_GET_CID(val) (((val) >> 16) & 0xff)
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#define PRID_GET_OPT(val) (((val) >> 24) & 0xff)
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/* C0_PRID bit definitions for R9K multiprocessor */
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#define R9K_PRID_GET_PNUM(val) (((val) >> 24) & 0x07) /* only 0 & 1 are valid */
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/* C0_1_INTCTL bit definitions for R7K and R9K */
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#define R7K_INTCTL_VS_MASK 0x1f
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#define R7K_INTCTL_VS_SHIFT 0
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#define R7K_INTCTL_IMASK 0xff00
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/* C0_Watch bit definitions */
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#define WATCHLO_STORE 0x00000001 /* watch stores */
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#define WATCHLO_LOAD 0x00000002 /* watch loads */
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#define WATCHLO_FETCH 0x00000003 /* watch loads */
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#define WATCHLO_PADDR0_MASK 0xfffffff8 /* bits 31:3 of the paddr */
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#define WATCHHI_GLOBAL_BIT (1 << 30)
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#endif /* __MACHINE_CP0_H__ */
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/* end of file */
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@ -1,48 +0,0 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/cp0.h>
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static void
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mips_setwatchlo(u_int32_t watchlo)
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{
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__asm __volatile ("mtc0 %0, $18, 0" : : "r" (watchlo));
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}
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static void
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mips_setwatchhi(u_int32_t watchhi)
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{
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__asm __volatile ("mtc0 %0, $19, 0" : : "r" (watchhi));
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}
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/*
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* mips_watchpoint -- set/clear a watchpoint
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*/
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void mips_watchpoint(void *addr, int access);//XXX kludge
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void
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mips_watchpoint(void *addr, int access)
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{
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u_int32_t watchlo = 0;
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u_int32_t watchhi = 0;
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if (addr != NULL) {
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/*
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* Set a new watchpoint.
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* Parameter addr points to the address we'd like to monitor.
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*/
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watchhi = WATCHHI_GLOBAL_BIT;
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watchlo = (u_int32_t)addr & WATCHLO_PADDR0_MASK;
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access &= WATCHLO_STORE | WATCHLO_LOAD | WATCHLO_FETCH;
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watchlo |= access;
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}
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mips_setwatchlo(watchlo);
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mips_setwatchhi(watchhi);
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}
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