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An early Christmas present: add driver support for a whole bunch of

Browse Source 
PCI fast ethernet adapters, plus man pages.

if_pn.c: Netgear FA310TX model D1, LinkSys LNE100TX, Matrox FastNIC 10/100,
         various other PNIC devices

if_mx.c: NDC Communications SOHOware SFA100 (Macronix 98713A), various
         other boards based on the Macronix 98713, 98713A, 98715, 98715A
         and 98725 chips

if_vr.c: D-Link DFE530-TX, other boards based on the VIA Rhine and
         Rhine II chips (note: the D-Link and certain other cards
         that actually use a Rhine II chip still return the PCI
         device ID of the Rhine I. I don't know why, and it doesn't
         really matter since the driver treats both chips the same
         anyway.)

if_wb.c: Trendware TE100-PCIE and various other cards based on the
         Winbond W89C840F chip (the Trendware card is identical to
         the sample boards Winbond sent me, so who knows how many
         clones there are running around)

All drivers include support for ifmedia, BPF and hardware multicast
filtering.

Also updated GENERIC, LINT, RELNOTES.TXT, userconfig and
sysinstall device list.

I also have a driver for the ASIX AX88140A in the works.
This commit is contained in:
Bill Paul 1998-12-04 18:01:24 +00:00
parent c31c6a9cce
commit 726ff6a158
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=41502
32 changed files with 14914 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
release/sysinstall/devices.c
View File

@ -4,7 +4,7 @@
* This is probably the last program in the `sysinstall' line - the next
* generation being essentially a complete rewrite.
*
* $Id: devices.c,v 1.85 1998/10/18 16:24:20 wpaul Exp $
* $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $
*
* Copyright (c) 1995
* Jordan Hubbard. All rights reserved.
@ -95,10 +95,14 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "tx", "SMC 9432TX ethernet card" },
{ DEVICE_TYPE_NETWORK, "tl", "Texas Instruments ThunderLAN PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vr", "VIA VT3043/VT86C100A Rhine PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vx", "3COM 3c590 / 3c595 ethernet card" },
{ DEVICE_TYPE_NETWORK, "wb", "Winbond W89C840F PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "xl", "3COM 3c90x / 3c90xB PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ze", "IBM/National Semiconductor PCMCIA ethernet card" },
{ DEVICE_TYPE_NETWORK, "zp", "3Com Etherlink III PCMCIA ethernet card" },

36
release/texts/RELNOTES.TXT
View File

@ -51,6 +51,22 @@ specifically marked as [MERGED] features.
1.1. KERNEL CHANGES
-------------------
Added driver support for fast ethernet adapters based on the
RealTek 8129/8139 and Accton MPX 5030/5038 chips.
Added driver support for Lite-On PNIC-based fast ethernet cards
including the LinkSys LNE100TX, NetGear FA310TX Rev. D1 and
Matrox FastNIC 10.100.
Added driver support for fast ethernet adapters based on the
Macronix 98713, 98713A, 98715, 98715A and 98725 chips.
Added driver support for fast ethernet adapters based on the
Winbond W89C840F chip.
Added driver support for fast ethernet adapters based on the
VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" chips.
1.2. SECURITY FIXES
-------------------
@ -187,12 +203,32 @@ based clones. SMC Elite Ultra. SMC Etherpower II.
RealTek 8129/8139 fast ethernet NICs including the following:
Allied Telesyn AT2550
Allied Telesyn AT2500TX
Genius GF100TXR (RTL8139)
NDC Communications NE100TX-E
OvisLink LEF-8129TX
OvisLink LEF-8139TX
Netronix Inc. EA-1210 NetEther 10/100
KTX-9130TX 10/100 Fast Ethernet
Accton "Cheetah" EN1027D (MPX 5030/5038; RealTek 8139 clone?)
Lite-On 82c168/82c169 PNIC fast ethernet NICs including the following:
LinkSys EtherFast LNE100TX
NetGear FA310-TX Rev. D1
Matrox FastNIC 10/100
Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs
NDC Communications SFA100A (98713A)
CNet Pro120A (98713 or 98713A)
CNet Pro120B (98715)
Winbond W89C840F fast ethernet NICs including the following:
Trendware TE100-PCIE
VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" fast ethernet
NICs including the following:
Hawking Technologies PN102TX
D-Link DFE530TX
Texas Instruments ThunderLAN PCI NICs, including the following:
Compaq Netelligent 10, 10/100, 10/100 Proliant, 10/100 Dual-Port

36
release/texts/i386/RELNOTES.TXT
View File

@ -51,6 +51,22 @@ specifically marked as [MERGED] features.
1.1. KERNEL CHANGES
-------------------
Added driver support for fast ethernet adapters based on the
RealTek 8129/8139 and Accton MPX 5030/5038 chips.
Added driver support for Lite-On PNIC-based fast ethernet cards
including the LinkSys LNE100TX, NetGear FA310TX Rev. D1 and
Matrox FastNIC 10.100.
Added driver support for fast ethernet adapters based on the
Macronix 98713, 98713A, 98715, 98715A and 98725 chips.
Added driver support for fast ethernet adapters based on the
Winbond W89C840F chip.
Added driver support for fast ethernet adapters based on the
VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" chips.
1.2. SECURITY FIXES
-------------------
@ -187,12 +203,32 @@ based clones. SMC Elite Ultra. SMC Etherpower II.
RealTek 8129/8139 fast ethernet NICs including the following:
Allied Telesyn AT2550
Allied Telesyn AT2500TX
Genius GF100TXR (RTL8139)
NDC Communications NE100TX-E
OvisLink LEF-8129TX
OvisLink LEF-8139TX
Netronix Inc. EA-1210 NetEther 10/100
KTX-9130TX 10/100 Fast Ethernet
Accton "Cheetah" EN1027D (MPX 5030/5038; RealTek 8139 clone?)
Lite-On 82c168/82c169 PNIC fast ethernet NICs including the following:
LinkSys EtherFast LNE100TX
NetGear FA310-TX Rev. D1
Matrox FastNIC 10/100
Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs
NDC Communications SFA100A (98713A)
CNet Pro120A (98713 or 98713A)
CNet Pro120B (98715)
Winbond W89C840F fast ethernet NICs including the following:
Trendware TE100-PCIE
VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" fast ethernet
NICs including the following:
Hawking Technologies PN102TX
D-Link DFE530TX
Texas Instruments ThunderLAN PCI NICs, including the following:
Compaq Netelligent 10, 10/100, 10/100 Proliant, 10/100 Dual-Port

14
share/man/man4/man4.i386/Makefile
View File

@ -1,14 +1,14 @@
# $Id: Makefile,v 1.86 1998/10/29 09:57:40 bde Exp $
# $Id: Makefile,v 1.87 1998/11/07 17:40:18 wpaul Exp $
MAN4= adv.4 adw.4 aha.4 ahb.4 ahc.4 aic.4 alog.4 apm.4 ar.4 asc.4 bktr.4 \
bt.4 cs.4 cx.4 cy.4 de.4 \
dgb.4 dpt.4 ed.4 eg.4 el.4 en.4 ep.4 ex.4 fdc.4 fe.4 fxp.4 gsc.4 ie.4 \
io.4 joy.4 keyboard.4 labpc.4 le.4 lnc.4 lp.4 lpt.4 matcd.4 mcd.4 \
mem.4 meteor.4 mouse.4 mse.4 mtio.4 nca.4 ncr.4 npx.4 \
pcf.4 pcm.4 pcvt.4 perfmon.4 pnp.4 ppc.4 psm.4 \
mem.4 meteor.4 mouse.4 mse.4 mtio.4 mx.4 nca.4 ncr.4 npx.4 \
pcf.4 pcm.4 pcvt.4 perfmon.4 pn.4 pnp.4 ppc.4 psm.4 \
rl.4 sb.4 scd.4 screen.4 sea.4 si.4 sio.4 \
spkr.4 sr.4 sysmouse.4 tl.4 tw.4 tx.4 uha.4 vx.4 \
wd.4 wfd.4 wl.4 wt.4 xl.4 ze.4 zp.4
spkr.4 sr.4 sysmouse.4 tl.4 tw.4 tx.4 uha.4 vr.4 vx.4 \
wb.4 wd.4 wfd.4 wl.4 wt.4 xl.4 ze.4 zp.4
MLINKS= adv.4 ../adv.4
MLINKS+= adw.4 ../adw.4
@ -54,6 +54,7 @@ MLINKS+= meteor.4 ../meteor.4
MLINKS+= mouse.4 ../mouse.4
MLINKS+= mse.4 ../mse.4
MLINKS+= mtio.4 ../mtio.4
MLINKS+= mx.4 ../mx.4
MLINKS+= nca.4 ../nca.4
MLINKS+= ncr.4 ../ncr.4
MLINKS+= npx.4 ../npx.4
@ -61,6 +62,7 @@ MLINKS+= pcf.4 ../pcf.4
MLINKS+= pcm.4 ../pcm.4
MLINKS+= pcvt.4 vt.4 pcvt.4 ../pcvt.4 pcvt.4 ../vt.4
MLINKS+= perfmon.4 ../perfmon.4
MLINKS+= pn.4 ../pn.4
MLINKS+= pnp.4 ../pnp.4
MLINKS+= ppc.4 ../ppc.4
MLINKS+= psm.4 ../psm.4
@ -78,7 +80,9 @@ MLINKS+= tl.4 ../tl.4
MLINKS+= tw.4 ../tw.4
MLINKS+= tx.4 ../tx.4
MLINKS+= uha.4 ../uha.4
MLINKS+= vr.4 ../vr.4
MLINKS+= vx.4 ../vx.4
MLINKS+= wb.4 ../wb.4
MLINKS+= wd.4 ../wd.4
MLINKS+= wfd.4 ../wfd.4
MLINKS+= wl.4 ../wl.4

167
share/man/man4/man4.i386/mx.4 Normal file
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@ -0,0 +1,167 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: mx.4,v 1.4 1998/11/08 16:03:44 wpaul Exp $
.\"
.Dd November 5, 1998
.Dt MX 4 i386
.Os FreeBSD
.Sh NAME
.Nm mx
.Nd
Macronix 98713/98715/98725 fast ethernet device driver
.Sh SYNOPSIS
.Cd "device mx0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Macronix 98713, 98713A, 98715, 98715A and
98725 fast ethernet controller chips. This includes the NDC
Communications SOHOware SFA110, the SVEC PN102-TX
fast ethernet card, and various other adapters.
.Pp
The Macronix chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. The original 98713 had an MII bus for
controlling an external PHY, however the 98713A and up use an
internal transceiver with NWAY support. The Macronix parts are
advertised as being register compatible with the DEC 21x4x
controllers. All of the Macronix controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "mx%d: couldn't map memory"
A fatal initialization error has occurred.
.It "mx%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "mx%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "mx%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "mx%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "mx%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T Macronix 98713/A, 98715/A and 98725 data sheets
.%O http://www.macronix.com
.Re
.Rs
.%T Macronix 98713/A and 98715/A app notes
.%O http://www.macronix.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The Macronix application notes claim that in order to put the
chips in normal operation, the driver must write a certian magic
number into the CSR16 register. The numbers are documented in
the app notes, but the exact meaning of the bits is not.
.Pp
The 98713A seems to have a problem with 10Mbps full duplex mode.
The transmitter works but the receiver tends to produce many
unexplained errors leading to very poor overall performance. The
98715A does not exhibit this problem. All other modes on the
98713A seem to work correctly.

161
share/man/man4/man4.i386/pn.4 Normal file
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@ -0,0 +1,161 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: pn.4,v 1.3 1998/11/08 05:23:37 wpaul Exp $
.\"
.Dd November 7, 1998
.Dt MX 4 i386
.Os FreeBSD
.Sh NAME
.Nm pn
.Nd
Lite-On 82c168/82c169 PNIC fast ethernet device driver
.Sh SYNOPSIS
.Cd "device pn0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Lite-On 82c168 and 82c169 fast ethernet
controller chips. This includes the LinkSys LNE100TX, the
Bay Networks Netgear FA310TX revision D1, the Matrox Networks
FastNIC 10/100, certain adapters manufactured by D-Link and
Trendware, and various other commodity fast ethernet cards.
.Pp
The Lite-On chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. Many vendors that formerly based their
designs around the DEC 21x4x devices are now using the PNIC
instead. The chips support both an internal transceiver
and external transceivers via an MII bus. The Lite-On parts are
advertised as being register compatible with the DEC 21x4x
controllers, however there are some differences in the way the
EEPROM and MII access is done. The PNIC controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "pn%d: couldn't map memory"
A fatal initialization error has occurred.
.It "pn%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "pn%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "pn%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "pn%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "pn%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The
.Nm
driver currently only supports cards with external transceivers
connected to the PNIC controller via its MII bus. This is because
the author had no boards available for testing which made use of the
internal transceiver. Most of the PNIC implementations on the market
today use an external PHY, so hopefully this will not present any
serious problems. Code to support the internal transceiver may be
added later if hardware becomes available.

164
share/man/man4/man4.i386/vr.4 Normal file
View File

@ -0,0 +1,164 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: vr.4,v 1.1 1998/11/22 18:36:02 wpaul Exp $
.\"
.Dd November 22, 1998
.Dt VR 4 i386
.Os FreeBSD
.Sh NAME
.Nm vr
.Nd
VIA Technologies VT3043 and VT86C100A ethernet device driver
.Sh SYNOPSIS
.Cd "device vr0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the VIA Technologies VT3043 Rhine I and
VT86C100A Rhine II fast ethernet controller chips. This includes
the D-Link DFE530-TX and various other commodity fast ethernet
cards.
.Pp
The VIA Rhine chips use bus master DMA and have a software interface
designed to resemble that of the DEC 21x4x "tulip" chips. The major
differences are that the receive filter in the Rhine chips is
much simpler and is programmed through registers rather than by
downloading a special setup frame through the transmit DMA engine,
and that transmit and receive DMA buffers must be longword
aligned. The Rhine chips are meant to be interfaced with external
physical layer devices via an MII bus. They support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "vr%d: couldn't map memory"
A fatal initialization error has occurred.
.It "vr%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "vr%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "vr%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "vr%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "vr%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T The VIA Technologies VT86C100A data sheet
.%O http://www.via.com.tw
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The
.Nm
driver always copies transmit mbuf chains into longword-aligned
buffers prior to transmission in order to pacify the Rhine chips.
If buffers are not aligned correctly, the chip will round the
supplied buffer address and begin DMAing from the wrong location.
This buffer copying impairs transmit performance on slower systems but can't
be avoided. On faster machines (e.g. a Pentium II), the performance
impact is much less noticable.

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.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: wb.4,v 1.6 1998/11/07 18:01:43 wpaul Exp $
.\"
.Dd November 4, 1998
.Dt WB 4 i386
.Os FreeBSD
.Sh NAME
.Nm wb
.Nd
Winbond W89C840F fast ethernet device driver
.Sh SYNOPSIS
.Cd "device wb0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Winbond W89C840F fast ethernet controller
chip. This includes the Trendware TE100-PCIE and various other cheap
boards. The 840F should not be confused with the 940F, which is
an NE2000 clone and only supports 10Mbps speeds.
.Pp
The Winbond controller uses bus master DMA and is designed to be
a DEC 'tulip' workalike. It differs from the standard DEC design
in several ways: the control and status registers are spaced 4
bytes apart instead of 8, and the receive filter is programmed through
registers rather than by downloading a special setup frame via
the transmit DMA engine. Using an external PHY, the Winbond chip
supports both 10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options. This is only
supported if the PHY chip attached to the Winbond controller
supports NWAY autonegotiation. The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "wb%d: couldn't map memory"
A fatal initialization error has occurred.
.It "wb%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "wb%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "wb%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "wb%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "wb%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The Winbond chip seems to behave strangely in some cases when the
link partner switches modes. If for example both sides are set to
10Mbps half-duplex, and the other end is changed to 100Mbps
full-duplex, the Winbond's receiver suddenly starts writing trash
all over the RX descriptors. The
.Nm
driver handles this by forcing a reset of both the controller
chip and attached PHY. This is drastic, but it appears to be the
only way to recover properly from this condition.

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.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: mx.4,v 1.4 1998/11/08 16:03:44 wpaul Exp $
.\"
.Dd November 5, 1998
.Dt MX 4 i386
.Os FreeBSD
.Sh NAME
.Nm mx
.Nd
Macronix 98713/98715/98725 fast ethernet device driver
.Sh SYNOPSIS
.Cd "device mx0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Macronix 98713, 98713A, 98715, 98715A and
98725 fast ethernet controller chips. This includes the NDC
Communications SOHOware SFA110, the SVEC PN102-TX
fast ethernet card, and various other adapters.
.Pp
The Macronix chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. The original 98713 had an MII bus for
controlling an external PHY, however the 98713A and up use an
internal transceiver with NWAY support. The Macronix parts are
advertised as being register compatible with the DEC 21x4x
controllers. All of the Macronix controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "mx%d: couldn't map memory"
A fatal initialization error has occurred.
.It "mx%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "mx%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "mx%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "mx%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "mx%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T Macronix 98713/A, 98715/A and 98725 data sheets
.%O http://www.macronix.com
.Re
.Rs
.%T Macronix 98713/A and 98715/A app notes
.%O http://www.macronix.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The Macronix application notes claim that in order to put the
chips in normal operation, the driver must write a certian magic
number into the CSR16 register. The numbers are documented in
the app notes, but the exact meaning of the bits is not.
.Pp
The 98713A seems to have a problem with 10Mbps full duplex mode.
The transmitter works but the receiver tends to produce many
unexplained errors leading to very poor overall performance. The
98715A does not exhibit this problem. All other modes on the
98713A seem to work correctly.

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.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: pn.4,v 1.3 1998/11/08 05:23:37 wpaul Exp $
.\"
.Dd November 7, 1998
.Dt MX 4 i386
.Os FreeBSD
.Sh NAME
.Nm pn
.Nd
Lite-On 82c168/82c169 PNIC fast ethernet device driver
.Sh SYNOPSIS
.Cd "device pn0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Lite-On 82c168 and 82c169 fast ethernet
controller chips. This includes the LinkSys LNE100TX, the
Bay Networks Netgear FA310TX revision D1, the Matrox Networks
FastNIC 10/100, certain adapters manufactured by D-Link and
Trendware, and various other commodity fast ethernet cards.
.Pp
The Lite-On chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. Many vendors that formerly based their
designs around the DEC 21x4x devices are now using the PNIC
instead. The chips support both an internal transceiver
and external transceivers via an MII bus. The Lite-On parts are
advertised as being register compatible with the DEC 21x4x
controllers, however there are some differences in the way the
EEPROM and MII access is done. The PNIC controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "pn%d: couldn't map memory"
A fatal initialization error has occurred.
.It "pn%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "pn%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "pn%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "pn%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "pn%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The
.Nm
driver currently only supports cards with external transceivers
connected to the PNIC controller via its MII bus. This is because
the author had no boards available for testing which made use of the
internal transceiver. Most of the PNIC implementations on the market
today use an external PHY, so hopefully this will not present any
serious problems. Code to support the internal transceiver may be
added later if hardware becomes available.

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.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: vr.4,v 1.1 1998/11/22 18:36:02 wpaul Exp $
.\"
.Dd November 22, 1998
.Dt VR 4 i386
.Os FreeBSD
.Sh NAME
.Nm vr
.Nd
VIA Technologies VT3043 and VT86C100A ethernet device driver
.Sh SYNOPSIS
.Cd "device vr0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the VIA Technologies VT3043 Rhine I and
VT86C100A Rhine II fast ethernet controller chips. This includes
the D-Link DFE530-TX and various other commodity fast ethernet
cards.
.Pp
The VIA Rhine chips use bus master DMA and have a software interface
designed to resemble that of the DEC 21x4x "tulip" chips. The major
differences are that the receive filter in the Rhine chips is
much simpler and is programmed through registers rather than by
downloading a special setup frame through the transmit DMA engine,
and that transmit and receive DMA buffers must be longword
aligned. The Rhine chips are meant to be interfaced with external
physical layer devices via an MII bus. They support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "vr%d: couldn't map memory"
A fatal initialization error has occurred.
.It "vr%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "vr%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "vr%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "vr%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "vr%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T The VIA Technologies VT86C100A data sheet
.%O http://www.via.com.tw
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The
.Nm
driver always copies transmit mbuf chains into longword-aligned
buffers prior to transmission in order to pacify the Rhine chips.
If buffers are not aligned correctly, the chip will round the
supplied buffer address and begin DMAing from the wrong location.
This buffer copying impairs transmit performance on slower systems but can't
be avoided. On faster machines (e.g. a Pentium II), the performance
impact is much less noticable.

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@ -0,0 +1,159 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $Id: wb.4,v 1.6 1998/11/07 18:01:43 wpaul Exp $
.\"
.Dd November 4, 1998
.Dt WB 4 i386
.Os FreeBSD
.Sh NAME
.Nm wb
.Nd
Winbond W89C840F fast ethernet device driver
.Sh SYNOPSIS
.Cd "device wb0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Winbond W89C840F fast ethernet controller
chip. This includes the Trendware TE100-PCIE and various other cheap
boards. The 840F should not be confused with the 940F, which is
an NE2000 clone and only supports 10Mbps speeds.
.Pp
The Winbond controller uses bus master DMA and is designed to be
a DEC 'tulip' workalike. It differs from the standard DEC design
in several ways: the control and status registers are spaced 4
bytes apart instead of 8, and the receive filter is programmed through
registers rather than by downloading a special setup frame via
the transmit DMA engine. Using an external PHY, the Winbond chip
supports both 10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options. This is only
supported if the PHY chip attached to the Winbond controller
supports NWAY autonegotiation. The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "wb%d: couldn't map memory"
A fatal initialization error has occurred.
.It "wb%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "wb%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "wb%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "wb%d: no memory for tx list"
The driver fauled to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "wb%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHOR
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The Winbond chip seems to behave strangely in some cases when the
link partner switches modes. If for example both sides are set to
10Mbps half-duplex, and the other end is changed to 100Mbps
full-duplex, the Winbond's receiver suddenly starts writing trash
all over the RX descriptors. The
.Nm
driver handles this by forcing a reset of both the controller
chip and attached PHY. This is drastic, but it appears to be the
only way to recover properly from this condition.

6
sys/amd64/conf/GENERIC
View File

@ -11,7 +11,7 @@
# device lines is present in the ./LINT configuration file. If you are
# in doubt as to the purpose or necessity of a line, check first in LINT.
#
# $Id: GENERIC,v 1.131 1998/11/12 11:29:28 obrien Exp $
# $Id: GENERIC,v 1.132 1998/11/26 23:13:11 n_hibma Exp $
machine "i386"
cpu "I386_CPU"
@ -140,10 +140,14 @@ device psm0 at isa? port IO_KBD conflicts tty irq 12
# revision 1.20 of this file.
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device ed0 at isa? port 0x280 net irq 10 iomem 0xd8000

29
sys/conf/NOTES
View File

@ -2,7 +2,7 @@
# LINT -- config file for checking all the sources, tries to pull in
# as much of the source tree as it can.
#
# $Id: LINT,v 1.505 1998/11/23 09:59:02 phk Exp $
# $Id: LINT,v 1.506 1998/12/03 20:06:00 dillon Exp $
#
# NB: You probably don't want to try running a kernel built from this
# file. Instead, you should start from GENERIC, and add options from
@ -1435,10 +1435,21 @@ options "EISA_SLOTS=12"
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 ans 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to useing programmed I/O to do register accesses because memory mapped
# mode seems to cause severe lockups on SMP hardware.
# mode seems to cause severe lockups on SMP hardware. This driver also
# supports the Accton EN1207D `Cheetah' adapter, which uses a chip called
# the MPX 5030/5038, which is either a RealTek in disguise or a RealTek
# workalike.
#
# The 'tl' device provides support for the Texas Instruments TNETE100
# series 'ThunderLAN' cards and integrated ethernet controllers. This
@ -1449,10 +1460,18 @@ options "EISA_SLOTS=12"
#
# The `tx' device provides support for the SMC 9432TX cards.
#
# The `vr' device provides support for various fast ethernet adapters
# based on the VIA Technologies VT3043 `Rhine I' and VT86C100A `Rhine II'
# chips, including the D-Link DFE530TX.
#
# The `vx' device provides support for the 3Com 3C590 and 3C595
# early support
#
# The `xl' driver provides support for the 3Com 3c900, 3c905 and
# The `wb' device provides support for various fast ethernet adapters
# based on the Winbond W89C840F chip. Note: this is not the same as
# the Winbond W89C940F, which is an NE2000 clone.
#
# The `xl' device provides support for the 3Com 3c900, 3c905 and
# 3c905B (Fast) Etherlink XL cards and integrated controllers. This
# includes the integrated 3c905B-TX chips in certain Dell Optiplex and
# Dell Precision desktop machines and the integrated 3c905-TX chips
@ -1499,10 +1518,14 @@ controller ncr0
controller isp0
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device fpa0
device meteor0

4
sys/conf/files
View File

@ -536,12 +536,16 @@ pci/if_ed_p.c optional ed device-driver
pci/if_en_pci.c optional en device-driver
pci/if_fxp.c optional fxp device-driver
pci/if_lnc_p.c optional lnc device-driver
pci/if_mx.c optional mx device-driver
pci/if_pn.c optional pn device-driver
pci/if_fpa.c optional fpa device-driver
pci/if_rl.c optional rl device-driver
pci/if_sr_p.c optional sr device-driver
pci/if_tl.c optional tl device-driver
pci/if_tx.c optional tx device-driver
pci/if_vr.c optional vr device-driver
pci/if_vx_pci.c optional vx device-driver
pci/if_wb.c optional wb device-driver
pci/if_xl.c optional xl device-driver
pci/isp_pci.c optional isp device-driver
pci/meteor.c optional meteor device-driver

1962
sys/dev/vr/if_vr.c Normal file
View File

File diff suppressed because it is too large Load Diff

615
sys/dev/vr/if_vrreg.h Normal file
View File

@ -0,0 +1,615 @@
/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_vrreg.h,v 1.8 1998/12/01 22:08:11 wpaul Exp $
*/
/*
* Rhine register definitions.
*/
#define VR_PAR0 0x00 /* node address 0 to 4 */
#define VR_PAR1 0x04 /* node address 2 to 6 */
#define VR_RXCFG 0x06 /* receiver config register */
#define VR_TXCFG 0x07 /* transmit config register */
#define VR_COMMAND 0x08 /* command register */
#define VR_ISR 0x0C /* interrupt/status register */
#define VR_IMR 0x0E /* interrupt mask register */
#define VR_MAR0 0x10 /* multicast hash 0 */
#define VR_MAR1 0x14 /* multicast hash 1 */
#define VR_RXADDR 0x18 /* rx descriptor list start addr */
#define VR_TXADDR 0x1C /* tx descriptor list start addr */
#define VR_CURRXDESC0 0x20
#define VR_CURRXDESC1 0x24
#define VR_CURRXDESC2 0x28
#define VR_CURRXDESC3 0x2C
#define VR_NEXTRXDESC0 0x30
#define VR_NEXTRXDESC1 0x34
#define VR_NEXTRXDESC2 0x38
#define VR_NEXTRXDESC3 0x3C
#define VR_CURTXDESC0 0x40
#define VR_CURTXDESC1 0x44
#define VR_CURTXDESC2 0x48
#define VR_CURTXDESC3 0x4C
#define VR_NEXTTXDESC0 0x50
#define VR_NEXTTXDESC1 0x54
#define VR_NEXTTXDESC2 0x58
#define VR_NEXTTXDESC3 0x5C
#define VR_CURRXDMA 0x60 /* current RX DMA address */
#define VR_CURTXDMA 0x64 /* current TX DMA address */
#define VR_TALLYCNT 0x68 /* tally counter test register */
#define VR_PHYADDR 0x6C
#define VR_MIISTAT 0x6D
#define VR_BCR0 0x6E
#define VR_BCR1 0x6F
#define VR_MIICMD 0x70
#define VR_MIIADDR 0x71
#define VR_MIIDATA 0x72
#define VR_EECSR 0x74
#define VR_TEST 0x75
#define VR_GPIO 0x76
#define VR_CONFIG 0x78
#define VR_MPA_CNT 0x7C
#define VR_CRC_CNT 0x7E
/*
* RX config bits.
*/
#define VR_RXCFG_RX_ERRPKTS 0x01
#define VR_RXCFG_RX_RUNT 0x02
#define VR_RXCFG_RX_MULTI 0x04
#define VR_RXCFG_RX_BROAD 0x08
#define VR_RXCFG_RX_PROMISC 0x10
#define VR_RXCFG_RX_THRESH 0xE0
#define VR_RXTHRESH_32BYTES 0x00
#define VR_RXTHRESH_64BYTES 0x20
#define VR_RXTHRESH_128BYTES 0x40
#define VR_RXTHRESH_256BYTES 0x60
#define VR_RXTHRESH_512BYTES 0x80
#define VR_RXTHRESH_768BYTES 0xA0
#define VR_RXTHRESH_1024BYTES 0xC0
#define VR_RXTHRESH_STORENFWD 0xE0
/*
* TX config bits.
*/
#define VR_TXCFG_RSVD0 0x01
#define VR_TXCFG_LOOPBKMODE 0x06
#define VR_TXCFG_BACKOFF 0x08
#define VR_TXCFG_RSVD1 0x10
#define VR_TXCFG_TX_THRESH 0xE0
#define VR_TXTHRESH_32BYTES 0x00
#define VR_TXTHRESH_64BYTES 0x20
#define VR_TXTHRESH_128BYTES 0x40
#define VR_TXTHRESH_256BYTES 0x60
#define VR_TXTHRESH_512BYTES 0x80
#define VR_TXTHRESH_768BYTES 0xA0
#define VR_TXTHRESH_1024BYTES 0xC0
#define VR_TXTHRESH_STORENFWD 0xE0
/*
* Command register bits.
*/
#define VR_CMD_INIT 0x0001
#define VR_CMD_START 0x0002
#define VR_CMD_STOP 0x0004
#define VR_CMD_RX_ON 0x0008
#define VR_CMD_TX_ON 0x0010
#define VR_CMD_TX_GO 0x0020
#define VR_CMD_RX_GO 0x0040
#define VR_CMD_RSVD 0x0080
#define VR_CMD_RX_EARLY 0x0100
#define VR_CMD_TX_EARLY 0x0200
#define VR_CMD_FULLDUPLEX 0x0400
#define VR_CMD_TX_NOPOLL 0x0800
#define VR_CMD_RESET 0x8000
/*
* Interrupt status bits.
*/
#define VR_ISR_RX_OK 0x0001 /* packet rx ok */
#define VR_ISR_TX_OK 0x0002 /* packet tx ok */
#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_ISR_BUSERR 0x0040 /* PCI bus error */
#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_ISR_RX_EARLY 0x0100 /* rx early */
#define VR_ISR_LINKSTAT 0x0200 /* MII status change */
#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_ISR_RX_DROPPED 0x0800
#define VR_ISR_RX_NOBUF2 0x1000
#define VR_ISR_TX_ABRT2 0x2000
#define VR_ISR_LINKSTAT2 0x4000
#define VR_ISR_MAGICPACKET 0x8000
/*
* Interrupt mask bits.
*/
#define VR_IMR_RX_OK 0x0001 /* packet rx ok */
#define VR_IMR_TX_OK 0x0002 /* packet tx ok */
#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_IMR_BUSERR 0x0040 /* PCI bus error */
#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_IMR_RX_EARLY 0x0100 /* rx early */
#define VR_IMR_LINKSTAT 0x0200 /* MII status change */
#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_IMR_RX_DROPPED 0x0800
#define VR_IMR_RX_NOBUF2 0x1000
#define VR_IMR_TX_ABRT2 0x2000
#define VR_IMR_LINKSTAT2 0x4000
#define VR_IMR_MAGICPACKET 0x8000
#define VR_INTRS \
(VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
/*
* MII status register.
*/
#define VR_MIISTAT_SPEED 0x01
#define VR_MIISTAT_LINKFAULT 0x02
#define VR_MIISTAT_MGTREADERR 0x04
#define VR_MIISTAT_MIIERR 0x08
#define VR_MIISTAT_PHYOPT 0x10
#define VR_MIISTAT_MDC_SPEED 0x20
#define VR_MIISTAT_RSVD 0x40
#define VR_MIISTAT_GPIO1POLL 0x80
/*
* MII command register bits.
*/
#define VR_MIICMD_CLK 0x01
#define VR_MIICMD_DATAOUT 0x02
#define VR_MIICMD_DATAIN 0x04
#define VR_MIICMD_DIR 0x08
#define VR_MIICMD_DIRECTPGM 0x10
#define VR_MIICMD_WRITE_ENB 0x20
#define VR_MIICMD_READ_ENB 0x40
#define VR_MIICMD_AUTOPOLL 0x80
/*
* EEPROM control bits.
*/
#define VR_EECSR_DATAIN 0x01 /* data out */
#define VR_EECSR_DATAOUT 0x02 /* data in */
#define VR_EECSR_CLK 0x04 /* clock */
#define VR_EECSR_CS 0x08 /* chip select */
#define VR_EECSR_DPM 0x10
#define VR_EECSR_LOAD 0x20
#define VR_EECSR_EMBP 0x40
#define VR_EECSR_EEPR 0x80
#define VR_EECMD_WRITE 0x140
#define VR_EECMD_READ 0x180
#define VR_EECMD_ERASE 0x1c0
/*
* Test register bits.
*/
#define VR_TEST_TEST0 0x01
#define VR_TEST_TEST1 0x02
#define VR_TEST_TEST2 0x04
#define VR_TEST_TSTUD 0x08
#define VR_TEST_TSTOV 0x10
#define VR_TEST_BKOFF 0x20
#define VR_TEST_FCOL 0x40
#define VR_TEST_HBDES 0x80
/*
* Config register bits.
*/
#define VR_CFG_GPIO2OUTENB 0x00000001
#define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */
#define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */
#define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */
#define VR_CFG_MIIOPT 0x00000010
#define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */
#define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */
#define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */
#define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */
#define VR_CFG_MRREADWAIT 0x00000200
#define VR_CFG_MRWRITEWAIT 0x00000400
#define VR_CFG_RX_ARB 0x00000800
#define VR_CFG_TX_ARB 0x00001000
#define VR_CFG_READMULTI 0x00002000
#define VR_CFG_TX_PACE 0x00004000
#define VR_CFG_TX_QDIS 0x00008000
#define VR_CFG_ROMSEL0 0x00010000
#define VR_CFG_ROMSEL1 0x00020000
#define VR_CFG_ROMSEL2 0x00040000
#define VR_CFG_ROMTIMESEL 0x00080000
#define VR_CFG_RSVD0 0x00100000
#define VR_CFG_ROMDLY 0x00200000
#define VR_CFG_ROMOPT 0x00400000
#define VR_CFG_RSVD1 0x00800000
#define VR_CFG_BACKOFFOPT 0x01000000
#define VR_CFG_BACKOFFMOD 0x02000000
#define VR_CFG_CAPEFFECT 0x04000000
#define VR_CFG_BACKOFFRAND 0x08000000
#define VR_CFG_MAGICKPACKET 0x10000000
#define VR_CFG_PCIREADLINE 0x20000000
#define VR_CFG_DIAG 0x40000000
#define VR_CFG_GPIOEN 0x80000000
/*
* Rhine TX/RX list structure.
*/
struct vr_desc {
u_int32_t vr_status;
u_int32_t vr_ctl;
u_int32_t vr_ptr1;
u_int32_t vr_ptr2;
};
#define vr_data vr_ptr1
#define vr_next vr_ptr2
#define VR_RXSTAT_RXERR 0x00000001
#define VR_RXSTAT_CRCERR 0x00000002
#define VR_RXSTAT_FRAMEALIGNERR 0x00000004
#define VR_RXSTAT_FIFOOFLOW 0x00000008
#define VR_RXSTAT_GIANT 0x00000010
#define VR_RXSTAT_RUNT 0x00000020
#define VR_RXSTAT_BUSERR 0x00000040
#define VR_RXSTAT_BUFFERR 0x00000080
#define VR_RXSTAT_LASTFRAG 0x00000100
#define VR_RXSTAT_FIRSTFRAG 0x00000200
#define VR_RXSTAT_RLINK 0x00000400
#define VR_RXSTAT_RX_PHYS 0x00000800
#define VR_RXSTAT_RX_BROAD 0x00001000
#define VR_RXSTAT_RX_MULTI 0x00002000
#define VR_RXSTAT_RX_OK 0x00004000
#define VR_RXSTAT_RXLEN 0x07FF0000
#define VR_RXSTAT_RXLEN_EXT 0x78000000
#define VR_RXSTAT_OWN 0x80000000
#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
#define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN)
#define VR_RXCTL_BUFLEN 0x000007FF
#define VR_RXCTL_BUFLEN_EXT 0x00007800
#define VR_RXCTL_CHAIN 0x00008000
#define VR_RXCTL_RX_INTR 0x00800000
#define VR_TXSTAT_DEFER 0x00000001
#define VR_TXSTAT_UNDERRUN 0x00000002
#define VR_TXSTAT_COLLCNT 0x00000078
#define VR_TXSTAT_SQE 0x00000080
#define VR_TXSTAT_ABRT 0x00000100
#define VR_TXSTAT_LATECOLL 0x00000200
#define VR_TXSTAT_CARRLOST 0x00000400
#define VR_TXSTAT_BUSERR 0x00002000
#define VR_TXSTAT_JABTIMEO 0x00004000
#define VR_TXSTAT_ERRSUM 0x00008000
#define VR_TXSTAT_OWN 0x80000000
#define VR_TXCTL_BUFLEN 0x000007FF
#define VR_TXCTL_BUFLEN_EXT 0x00007800
#define VR_TXCTL_TLINK 0x00008000
#define VR_TXCTL_FIRSTFRAG 0x00200000
#define VR_TXCTL_LASTFRAG 0x00400000
#define VR_TXCTL_FINT 0x00800000
#define VR_MAXFRAGS 16
#define VR_RX_LIST_CNT 64
#define VR_TX_LIST_CNT 64
#define VR_MIN_FRAMELEN 60
#define VR_FRAMELEN 1536
#define VR_TXOWN(x) x->vr_ptr->vr_status
#define VR_UNSENT 0x12341234
struct vr_list_data {
struct vr_desc vr_rx_list[VR_RX_LIST_CNT];
struct vr_desc vr_tx_list[VR_TX_LIST_CNT];
};
struct vr_chain {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain *vr_nextdesc;
};
struct vr_chain_onefrag {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain_onefrag *vr_nextdesc;
};
struct vr_chain_data {
struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT];
struct vr_chain vr_tx_chain[VR_TX_LIST_CNT];
struct vr_chain_onefrag *vr_rx_head;
struct vr_chain *vr_tx_head;
struct vr_chain *vr_tx_tail;
struct vr_chain *vr_tx_free;
};
struct vr_type {
u_int16_t vr_vid;
u_int16_t vr_did;
char *vr_name;
};
struct vr_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define VR_MII_STARTDELIM 0x01
#define VR_MII_READOP 0x02
#define VR_MII_WRITEOP 0x01
#define VR_MII_TURNAROUND 0x02
#define VR_FLAG_FORCEDELAY 1
#define VR_FLAG_SCHEDDELAY 2
#define VR_FLAG_DELAYTIMEO 3
struct vr_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t vr_bhandle; /* bus space handle */
bus_space_tag_t vr_btag; /* bus space tag */
struct vr_type *vr_info; /* Rhine adapter info */
struct vr_type *vr_pinfo; /* phy info */
u_int8_t vr_unit; /* interface number */
u_int8_t vr_type;
u_int8_t vr_phy_addr; /* PHY address */
u_int8_t vr_tx_pend; /* TX pending */
u_int8_t vr_want_auto;
u_int8_t vr_autoneg;
caddr_t vr_ldata_ptr;
struct vr_list_data *vr_ldata;
struct vr_chain_data vr_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
#define VR_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* VIA vendor ID
*/
#define VIA_VENDORID 0x1106
/*
* VIA Rhine device IDs.
*/
#define VIA_DEVICEID_RHINE 0x3043
#define VIA_DEVICEID_RHINE_II 0x6100
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define VR_PCI_VENDOR_ID 0x00
#define VR_PCI_DEVICE_ID 0x02
#define VR_PCI_COMMAND 0x04
#define VR_PCI_STATUS 0x06
#define VR_PCI_CLASSCODE 0x09
#define VR_PCI_LATENCY_TIMER 0x0D
#define VR_PCI_HEADER_TYPE 0x0E
#define VR_PCI_LOIO 0x10
#define VR_PCI_LOMEM 0x14
#define VR_PCI_BIOSROM 0x30
#define VR_PCI_INTLINE 0x3C
#define VR_PCI_INTPIN 0x3D
#define VR_PCI_MINGNT 0x3E
#define VR_PCI_MINLAT 0x0F
#define VR_PCI_RESETOPT 0x48
#define VR_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define VR_PCI_CAPID 0xDC /* 8 bits */
#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define VR_PSTATE_MASK 0x0003
#define VR_PSTATE_D0 0x0000
#define VR_PSTATE_D1 0x0002
#define VR_PSTATE_D2 0x0002
#define VR_PSTATE_D3 0x0003
#define VR_PME_EN 0x0010
#define VR_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define VR_PHYADDR_MIN 0x00
#define VR_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001

6
sys/i386/conf/GENERIC
View File

@ -11,7 +11,7 @@
# device lines is present in the ./LINT configuration file. If you are
# in doubt as to the purpose or necessity of a line, check first in LINT.
#
# $Id: GENERIC,v 1.131 1998/11/12 11:29:28 obrien Exp $
# $Id: GENERIC,v 1.132 1998/11/26 23:13:11 n_hibma Exp $
machine "i386"
cpu "I386_CPU"
@ -140,10 +140,14 @@ device psm0 at isa? port IO_KBD conflicts tty irq 12
# revision 1.20 of this file.
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device ed0 at isa? port 0x280 net irq 10 iomem 0xd8000

29
sys/i386/conf/LINT
View File

@ -2,7 +2,7 @@
# LINT -- config file for checking all the sources, tries to pull in
# as much of the source tree as it can.
#
# $Id: LINT,v 1.505 1998/11/23 09:59:02 phk Exp $
# $Id: LINT,v 1.506 1998/12/03 20:06:00 dillon Exp $
#
# NB: You probably don't want to try running a kernel built from this
# file. Instead, you should start from GENERIC, and add options from
@ -1435,10 +1435,21 @@ options "EISA_SLOTS=12"
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 ans 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to useing programmed I/O to do register accesses because memory mapped
# mode seems to cause severe lockups on SMP hardware.
# mode seems to cause severe lockups on SMP hardware. This driver also
# supports the Accton EN1207D `Cheetah' adapter, which uses a chip called
# the MPX 5030/5038, which is either a RealTek in disguise or a RealTek
# workalike.
#
# The 'tl' device provides support for the Texas Instruments TNETE100
# series 'ThunderLAN' cards and integrated ethernet controllers. This
@ -1449,10 +1460,18 @@ options "EISA_SLOTS=12"
#
# The `tx' device provides support for the SMC 9432TX cards.
#
# The `vr' device provides support for various fast ethernet adapters
# based on the VIA Technologies VT3043 `Rhine I' and VT86C100A `Rhine II'
# chips, including the D-Link DFE530TX.
#
# The `vx' device provides support for the 3Com 3C590 and 3C595
# early support
#
# The `xl' driver provides support for the 3Com 3c900, 3c905 and
# The `wb' device provides support for various fast ethernet adapters
# based on the Winbond W89C840F chip. Note: this is not the same as
# the Winbond W89C940F, which is an NE2000 clone.
#
# The `xl' device provides support for the 3Com 3c900, 3c905 and
# 3c905B (Fast) Etherlink XL cards and integrated controllers. This
# includes the integrated 3c905B-TX chips in certain Dell Optiplex and
# Dell Precision desktop machines and the integrated 3c905-TX chips
@ -1499,10 +1518,14 @@ controller ncr0
controller isp0
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device fpa0
device meteor0

29
sys/i386/conf/NOTES
View File

@ -2,7 +2,7 @@
# LINT -- config file for checking all the sources, tries to pull in
# as much of the source tree as it can.
#
# $Id: LINT,v 1.505 1998/11/23 09:59:02 phk Exp $
# $Id: LINT,v 1.506 1998/12/03 20:06:00 dillon Exp $
#
# NB: You probably don't want to try running a kernel built from this
# file. Instead, you should start from GENERIC, and add options from
@ -1435,10 +1435,21 @@ options "EISA_SLOTS=12"
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 ans 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to useing programmed I/O to do register accesses because memory mapped
# mode seems to cause severe lockups on SMP hardware.
# mode seems to cause severe lockups on SMP hardware. This driver also
# supports the Accton EN1207D `Cheetah' adapter, which uses a chip called
# the MPX 5030/5038, which is either a RealTek in disguise or a RealTek
# workalike.
#
# The 'tl' device provides support for the Texas Instruments TNETE100
# series 'ThunderLAN' cards and integrated ethernet controllers. This
@ -1449,10 +1460,18 @@ options "EISA_SLOTS=12"
#
# The `tx' device provides support for the SMC 9432TX cards.
#
# The `vr' device provides support for various fast ethernet adapters
# based on the VIA Technologies VT3043 `Rhine I' and VT86C100A `Rhine II'
# chips, including the D-Link DFE530TX.
#
# The `vx' device provides support for the 3Com 3C590 and 3C595
# early support
#
# The `xl' driver provides support for the 3Com 3c900, 3c905 and
# The `wb' device provides support for various fast ethernet adapters
# based on the Winbond W89C840F chip. Note: this is not the same as
# the Winbond W89C940F, which is an NE2000 clone.
#
# The `xl' device provides support for the 3Com 3c900, 3c905 and
# 3c905B (Fast) Etherlink XL cards and integrated controllers. This
# includes the integrated 3c905B-TX chips in certain Dell Optiplex and
# Dell Precision desktop machines and the integrated 3c905-TX chips
@ -1499,10 +1518,14 @@ controller ncr0
controller isp0
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device fpa0
device meteor0

6
sys/i386/conf/SMP-GENERIC
View File

@ -11,7 +11,7 @@
# device lines is present in the ./LINT configuration file. If you are
# in doubt as to the purpose or necessity of a line, check first in LINT.
#
# $Id: SMP-GENERIC,v 1.21 1998/11/03 21:12:20 des Exp $
# $Id: SMP-GENERIC,v 1.22 1998/11/03 22:01:22 des Exp $
machine "i386"
# SMP does NOT support 386/486 CPUs.
@ -161,10 +161,14 @@ device psm0 at isa? port IO_KBD conflicts tty irq 12
# revision 1.20 of this file.
device de0
device fxp0
device mx0
device pn0
device rl0
device tl0
device tx0
device vr0
device vx0
device wb0
device xl0
device ed0 at isa? port 0x280 net irq 10 iomem 0xd8000

8
sys/i386/i386/userconfig.c
View File

@ -46,7 +46,7 @@
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** $Id: userconfig.c,v 1.114 1998/11/03 21:07:51 msmith Exp $
** $Id: userconfig.c,v 1.115 1998/11/04 13:37:43 peter Exp $
**/
/**
@ -340,7 +340,11 @@ static DEV_INFO device_info[] = {
{"de", "DEC DC21040 Ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"fpa", "DEC DEFPA PCI FDDI adapter", FLG_FIXED, CLS_NETWORK},
{"rl", "RealTek 8129/8139 ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"mx", "Macronix PMAC ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"pn", "Lite-On 82c168/82c169 PNIC adapter", FLG_FIXED, CLS_NETWORK},
{"tl", "Texas Instruments ThunderLAN ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"vr", "VIA Rhine/Rhine II ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"wb", "Winbond W89C840F ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"xl", "3COM 3C90x PCI FDDI adapter", FLG_FIXED, CLS_NETWORK},
{"sio", "8250/16450/16550 Serial port", 0, CLS_COMMS},
@ -2454,7 +2458,7 @@ visuserconfig(void)
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: userconfig.c,v 1.114 1998/11/03 21:07:51 msmith Exp $
* $Id: userconfig.c,v 1.115 1998/11/04 13:37:43 peter Exp $
*/
#include "scbus.h"

2403
sys/pci/if_mx.c Normal file
View File

File diff suppressed because it is too large Load Diff

695
sys/pci/if_mxreg.h Normal file
View File

@ -0,0 +1,695 @@
/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_mxreg.h,v 1.11 1998/12/01 15:55:20 wpaul Exp $
*/
/*
* Macronix register definitions.
*/
#define MX_BUSCTL 0x00 /* bus control */
#define MX_TXSTART 0x08 /* tx start demand */
#define MX_RXSTART 0x10 /* rx start demand */
#define MX_RXADDR 0x18 /* rx descriptor list start addr */
#define MX_TXADDR 0x20 /* tx descriptor list start addr */
#define MX_ISR 0x28 /* interrupt status register */
#define MX_NETCFG 0x30 /* network config register */
#define MX_IMR 0x38 /* interrupt mask */
#define MX_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define MX_SIO 0x48 /* MII and ROM/EEPROM access */
#define MX_RESERVED 0x50
#define MX_TIMER 0x58 /* general timer */
#define MX_10BTSTAT 0x60
#define MX_SIARESET 0x68
#define MX_10BTCTRL 0x70
#define MX_WATCHDOG 0x78
#define MX_MAGICPACKET 0x80
#define MX_NWAYSTAT 0xA0
/*
* These are magic values that must be written into CSR16
* (MX_MAGICPACKET) in order to put the chip into proper
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
#define MX_MAGIC_98713 0x0F370000
#define MX_MAGIC_98713A 0x0B3C0000
#define MX_MAGIC_98715 0x0B3C0000
#define MX_MAGIC_98725 0x0B3C0000
#define MX_REVISION_98713 0x10
#define MX_REVISION_98715 0x20
#define MX_REVISION_98725 0x30
/*
* As far as the driver is concerned, there are two 'types' of
* chips to be concerned with. One is a 98713 with an external
* PHY on the MII. The other covers pretty much everything else,
* since all the other Macronix chips have built-in transceivers.
* This type setting governs what which mode selection routines
* we use (MII or built-in). It also govers which of the 'magic'
* numbers we write into CSR16.
*/
#define MX_TYPE_98713 0x1
#define MX_TYPE_987x5 0x2
/*
* Bus control bits.
*/
#define MX_BUSCTL_RESET 0x00000001
#define MX_BUSCTL_ARBITRATION 0x00000002
#define MX_BUSCTL_SKIPLEN 0x0000007C
#define MX_BUSCTL_BUF_BIGENDIAN 0x00000080
#define MX_BUSCTL_BURSTLEN 0x00003F00
#define MX_BUSCTL_CACHEALIGN 0x0000C000
#define MX_BUSCTL_XMITPOLL 0x00060000
#define MX_SKIPLEN_1LONG 0x00000004
#define MX_SKIPLEN_2LONG 0x00000008
#define MX_SKIPLEN_3LONG 0x00000010
#define MX_SKIPLEN_4LONG 0x00000020
#define MX_SKIPLEN_5LONG 0x00000040
#define MX_CACHEALIGN_8LONG 0x00004000
#define MX_CACHEALIGN_16LONG 0x00008000
#define MX_CACHEALIGN_32LONG 0x0000C000
#define MX_BURSTLEN_USECA 0x00000000
#define MX_BURSTLEN_1LONG 0x00000100
#define MX_BURSTLEN_2LONG 0x00000200
#define MX_BURSTLEN_4LONG 0x00000400
#define MX_BURSTLEN_8LONG 0x00000800
#define MX_BURSTLEN_16LONG 0x00001000
#define MX_BURSTLEN_32LONG 0x00002000
#define MX_TXPOLL_OFF 0x00000000
#define MX_TXPOLL_200U 0x00020000
#define MX_TXPOLL_800U 0x00040000
#define MX_TXPOLL_1600U 0x00060000
#define MX_BUSCTL_CONFIG (MX_BUSCTL_ARBITRATION|MX_CACHEALIGN_8LONG| \
MX_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define MX_ISR_TX_OK 0x00000001
#define MX_ISR_TX_IDLE 0x00000002
#define MX_ISR_TX_NOBUF 0x00000004
#define MX_ISR_TX_JABBERTIMEO 0x00000008
#define MX_ISR_LINKGOOD 0x00000010
#define MX_ISR_TX_UNDERRUN 0x00000020
#define MX_ISR_RX_OK 0x00000040
#define MX_ISR_RX_NOBUF 0x00000080
#define MX_ISR_RX_READ 0x00000100
#define MX_ISR_RX_WATDOGTIMEO 0x00000200
#define MX_ISR_TX_EARLY 0x00000400
#define MX_ISR_TIMER_EXPIRED 0x00000800
#define MX_ISR_LINKFAIL 0x00001000
#define MX_ISR_BUS_ERR 0x00002000
#define MX_ISR_RX_EARLY 0x00004000
#define MX_ISR_ABNORMAL 0x00008000
#define MX_ISR_NORMAL 0x00010000
#define MX_ISR_RX_STATE 0x000E0000
#define MX_ISR_TX_STATE 0x00700000
#define MX_ISR_BUSERRTYPE 0x03800000
#define MX_ISR_100MBPSLINK 0x08000000
#define MX_ISR_MAGICKPACK 0x10000000
#define MX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define MX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define MX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define MX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define MX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define MX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define MX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define MX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define MX_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define MX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define MX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define MX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define MX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define MX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define MX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define MX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define MX_NETCFG_RX_HASHPERF 0x00000001
#define MX_NETCFG_RX_ON 0x00000002
#define MX_NETCFG_RX_HASHONLY 0x00000004
#define MX_NETCFG_RX_BADFRAMES 0x00000008
#define MX_NETCFG_RX_INVFILT 0x00000010
#define MX_NETCFG_BACKOFFCNT 0x00000020
#define MX_NETCFG_RX_PROMISC 0x00000040
#define MX_NETCFG_RX_ALLMULTI 0x00000080
#define MX_NETCFG_FULLDUPLEX 0x00000200
#define MX_NETCFG_LOOPBACK 0x00000C00
#define MX_NETCFG_FORCECOLL 0x00001000
#define MX_NETCFG_TX_ON 0x00002000
#define MX_NETCFG_TX_THRESH 0x0000C000
#define MX_NETCFG_TX_BACKOFF 0x00020000
#define MX_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
#define MX_NETCFG_HEARTBEAT 0x00080000
#define MX_NETCFG_STORENFWD 0x00200000
#define MX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define MX_NETCFG_PCS 0x00800000
#define MX_NETCFG_SCRAMBLER 0x01000000
#define MX_NETCFG_NO_RXCRC 0x02000000
#define MX_OPMODE_NORM 0x00000000
#define MX_OPMODE_INTLOOP 0x00000400
#define MX_OPMODE_EXTLOOP 0x00000800
#define MX_TXTHRESH_72BYTES 0x00000000
#define MX_TXTHRESH_96BYTES 0x00004000
#define MX_TXTHRESH_128BYTES 0x00008000
#define MX_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define MX_IMR_TX_OK 0x00000001
#define MX_IMR_TX_IDLE 0x00000002
#define MX_IMR_TX_NOBUF 0x00000004
#define MX_IMR_TX_JABBERTIMEO 0x00000008
#define MX_IMR_LINKGOOD 0x00000010
#define MX_IMR_TX_UNDERRUN 0x00000020
#define MX_IMR_RX_OK 0x00000040
#define MX_IMR_RX_NOBUF 0x00000080
#define MX_IMR_RX_READ 0x00000100
#define MX_IMR_RX_WATDOGTIMEO 0x00000200
#define MX_IMR_TX_EARLY 0x00000400
#define MX_IMR_TIMER_EXPIRED 0x00000800
#define MX_IMR_LINKFAIL 0x00001000
#define MX_IMR_BUS_ERR 0x00002000
#define MX_IMR_RX_EARLY 0x00004000
#define MX_IMR_ABNORMAL 0x00008000
#define MX_IMR_NORMAL 0x00010000
#define MX_IMR_100MBPSLINK 0x08000000
#define MX_IMR_MAGICKPACK 0x10000000
#define MX_INTRS \
(MX_IMR_RX_OK|MX_IMR_TX_OK|MX_IMR_RX_NOBUF|MX_IMR_RX_WATDOGTIMEO|\
MX_IMR_TX_NOBUF|MX_IMR_TX_UNDERRUN|MX_IMR_BUS_ERR| \
MX_IMR_ABNORMAL|MX_IMR_NORMAL/*|MX_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define MX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define MX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define MX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define MX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define MX_SIO_ROMDATA4 0x00000010
#define MX_SIO_ROMDATA5 0x00000020
#define MX_SIO_ROMDATA6 0x00000040
#define MX_SIO_ROMDATA7 0x00000080
#define MX_SIO_EESEL 0x00000800
#define MX_SIO_ROMSEL 0x00001000
#define MX_SIO_ROMCTL_WRITE 0x00002000
#define MX_SIO_ROMCTL_READ 0x00004000
#define MX_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define MX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define MX_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define MX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define MX_EECMD_WRITE 0x140
#define MX_EECMD_READ 0x180
#define MX_EECMD_ERASE 0x1c0
#define MX_EE_NODEADDR_OFFSET 0x70
#define MX_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define MX_TIMER_VALUE 0x0000FFFF
#define MX_TIMER_CONTINUUS 0x00010000
/*
* 10baseT status register
*/
#define MX_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
#define MX_TSTAT_LS10 0x00000004 /* link status of 10baseT */
#define MX_TSTAT_AUTOPOLARITY 0x00000008
#define MX_TSTAT_REMFAULT 0x00000800
#define MX_TSTAT_ANEGSTAT 0x00007000
#define MX_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
#define MX_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
#define MX_ASTAT_DISABLE 0x00000000
#define MX_ASTAT_TXDISABLE 0x00001000
#define MX_ASTAT_ABDETECT 0x00002000
#define MX_ASTAT_ACKDETECT 0x00003000
#define MX_ASTAT_CMPACKDETECT 0x00004000
#define MX_ASTAT_AUTONEGCMP 0x00005000
#define MX_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
#define MX_SIA_RESET_NWAY 0x00000001
#define MX_SIA_RESET_100TX 0x00000002
/*
* 10baseT control register
*/
#define MX_TCTL_LOOPBACK 0x00000002
#define MX_TCTL_POWERDOWN 0x00000004
#define MX_TCTL_HALFDUPLEX 0x00000040
#define MX_TCTL_AUTONEGENBL 0x00000080
#define MX_TCTL_RX_SQUELCH 0x00000100
#define MX_TCTL_LINKTEST 0x00001000
#define MX_TCTL_100BTXHALF 0x00010000
#define MX_TCTL_100BTXFULL 0x00020000
#define MX_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
#define MX_WDOG_JABBERDIS 0x00000001
#define MX_WDOG_HOSTUNJAB 0x00000002
#define MX_WDOG_JABBERCLK 0x00000004
#define MX_WDOG_RXWDOGDIS 0x00000010
#define MX_WDOG_RXWDOGCLK 0x00000020
#define MX_WDOG_MUSTBEZERO 0x00000100
/*
* Magic packet register
*/
#define MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
#define MX_NWAY_10BTHALF 0x08000000
#define MX_NWAY_10BTFULL 0x10000000
#define MX_NWAY_100BTHALF 0x20000000
#define MX_NWAY_100BTFULL 0x40000000
#define MX_NWAY_100BT4 0x80000000
/*
* Size of a setup frame.
*/
#define MX_SFRAME_LEN 192
/*
* Macronix TX/RX list structure.
*/
struct mx_desc {
volatile u_int32_t mx_status;
volatile u_int32_t mx_ctl;
volatile u_int32_t mx_ptr1;
volatile u_int32_t mx_ptr2;
};
#define mx_data mx_ptr1
#define mx_next mx_ptr2
#define MX_RXSTAT_FIFOOFLOW 0x00000001
#define MX_RXSTAT_CRCERR 0x00000002
#define MX_RXSTAT_DRIBBLE 0x00000004
#define MX_RXSTAT_WATCHDOG 0x00000010
#define MX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define MX_RXSTAT_COLLSEEN 0x00000040
#define MX_RXSTAT_GIANT 0x00000080
#define MX_RXSTAT_LASTFRAG 0x00000100
#define MX_RXSTAT_FIRSTFRAG 0x00000200
#define MX_RXSTAT_MULTICAST 0x00000400
#define MX_RXSTAT_RUNT 0x00000800
#define MX_RXSTAT_RXTYPE 0x00003000
#define MX_RXSTAT_RXERR 0x00008000
#define MX_RXSTAT_RXLEN 0x3FFF0000
#define MX_RXSTAT_OWN 0x80000000
#define MX_RXBYTES(x) ((x & MX_RXSTAT_RXLEN) >> 16)
#define MX_RXSTAT (MX_RXSTAT_FIRSTFRAG|MX_RXSTAT_LASTFRAG|MX_RXSTAT_OWN)
#define MX_RXCTL_BUFLEN1 0x00000FFF
#define MX_RXCTL_BUFLEN2 0x00FFF000
#define MX_RXCTL_RLINK 0x01000000
#define MX_RXCTL_RLAST 0x02000000
#define MX_TXSTAT_DEFER 0x00000001
#define MX_TXSTAT_UNDERRUN 0x00000002
#define MX_TXSTAT_LINKFAIl 0x00000003
#define MX_TXSTAT_COLLCNT 0x00000078
#define MX_TXSTAT_SQE 0x00000080
#define MX_TXSTAT_EXCESSCOLL 0x00000100
#define MX_TXSTAT_LATECOLL 0x00000200
#define MX_TXSTAT_NOCARRIER 0x00000400
#define MX_TXSTAT_CARRLOST 0x00000800
#define MX_TXSTAT_JABTIMEO 0x00004000
#define MX_TXSTAT_ERRSUM 0x00008000
#define MX_TXSTAT_OWN 0x80000000
#define MX_TXCTL_BUFLEN1 0x000007FF
#define MX_TXCTL_BUFLEN2 0x003FF800
#define MX_TXCTL_FILTTYPE0 0x00400000
#define MX_TXCTL_PAD 0x00800000
#define MX_TXCTL_TLINK 0x01000000
#define MX_TXCTL_TLAST 0x02000000
#define MX_TXCTL_NOCRC 0x04000000
#define MX_TXCTL_SETUP 0x08000000
#define MX_TXCTL_FILTTYPE1 0x10000000
#define MX_TXCTL_FIRSTFRAG 0x20000000
#define MX_TXCTL_LASTFRAG 0x40000000
#define MX_TXCTL_FINT 0x80000000
#define MX_FILTER_PERFECT 0x00000000
#define MX_FILTER_HASHPERF 0x00400000
#define MX_FILTER_INVERSE 0x10000000
#define MX_FILTER_HASHONLY 0x10400000
#define MX_MAXFRAGS 16
#define MX_RX_LIST_CNT 64
#define MX_TX_LIST_CNT 64
#define MX_MIN_FRAMELEN 60
/*
* A tx 'super descriptor' is actually 16 regular descriptors
* back to back.
*/
struct mx_txdesc {
volatile struct mx_desc mx_frag[MX_MAXFRAGS];
};
#define MX_TXNEXT(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_next
#define MX_TXSTATUS(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_status
#define MX_TXCTL(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_ctl
#define MX_TXDATA(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_data
#define MX_TXOWN(x) x->mx_ptr->mx_frag[0].mx_status
#define MX_UNSENT 0x12341234
struct mx_list_data {
volatile struct mx_desc mx_rx_list[MX_RX_LIST_CNT];
volatile struct mx_txdesc mx_tx_list[MX_TX_LIST_CNT];
};
struct mx_chain {
volatile struct mx_txdesc *mx_ptr;
struct mbuf *mx_mbuf;
struct mx_chain *mx_nextdesc;
u_int8_t mx_lastdesc;
};
struct mx_chain_onefrag {
volatile struct mx_desc *mx_ptr;
struct mbuf *mx_mbuf;
struct mx_chain_onefrag *mx_nextdesc;
};
struct mx_chain_data {
struct mx_desc mx_sframe;
u_int32_t mx_sbuf[MX_SFRAME_LEN/sizeof(u_int32_t)];
u_int8_t mx_pad[MX_MIN_FRAMELEN];
struct mx_chain_onefrag mx_rx_chain[MX_RX_LIST_CNT];
struct mx_chain mx_tx_chain[MX_TX_LIST_CNT];
struct mx_chain_onefrag *mx_rx_head;
struct mx_chain *mx_tx_head;
struct mx_chain *mx_tx_tail;
struct mx_chain *mx_tx_free;
};
struct mx_type {
u_int16_t mx_vid;
u_int16_t mx_did;
char *mx_name;
};
struct mx_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define MX_MII_STARTDELIM 0x01
#define MX_MII_READOP 0x02
#define MX_MII_WRITEOP 0x01
#define MX_MII_TURNAROUND 0x02
#define MX_FLAG_FORCEDELAY 1
#define MX_FLAG_SCHEDDELAY 2
#define MX_FLAG_DELAYTIMEO 3
struct mx_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t mx_bhandle; /* bus space handle */
bus_space_tag_t mx_btag; /* bus space tag */
struct mx_type *mx_info; /* Macronix adapter info */
struct mx_type *mx_pinfo; /* phy info */
u_int8_t mx_unit; /* interface number */
u_int8_t mx_type;
u_int8_t mx_phy_addr; /* PHY address */
u_int8_t mx_tx_pend; /* TX pending */
u_int8_t mx_want_auto;
u_int8_t mx_autoneg;
u_int8_t mx_singlebuf;
caddr_t mx_ldata_ptr;
struct mx_list_data *mx_ldata;
struct mx_chain_data mx_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->mx_btag, sc->mx_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->mx_btag, sc->mx_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->mx_btag, sc->mx_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->mx_btag, sc->mx_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->mx_btag, sc->mx_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->mx_btag, sc->mx_bhandle, reg)
#define MX_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* Macronix PCI vendor ID
*/
#define MX_VENDORID 0x10D9
/*
* Macronix PMAC device IDs.
*/
#define MX_DEVICEID_98713 0x0512
#define MX_DEVICEID_987x5 0x0531
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define MX_PCI_VENDOR_ID 0x00
#define MX_PCI_DEVICE_ID 0x02
#define MX_PCI_COMMAND 0x04
#define MX_PCI_STATUS 0x06
#define MX_PCI_REVID 0x08
#define MX_PCI_CLASSCODE 0x09
#define MX_PCI_LATENCY_TIMER 0x0D
#define MX_PCI_HEADER_TYPE 0x0E
#define MX_PCI_LOIO 0x10
#define MX_PCI_LOMEM 0x14
#define MX_PCI_BIOSROM 0x30
#define MX_PCI_INTLINE 0x3C
#define MX_PCI_INTPIN 0x3D
#define MX_PCI_MINGNT 0x3E
#define MX_PCI_MINLAT 0x0F
#define MX_PCI_RESETOPT 0x48
#define MX_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define MX_PCI_CAPID 0x44 /* 8 bits */
#define MX_PCI_NEXTPTR 0x45 /* 8 bits */
#define MX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
#define MX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
#define MX_PSTATE_MASK 0x0003
#define MX_PSTATE_D0 0x0000
#define MX_PSTATE_D1 0x0001
#define MX_PSTATE_D2 0x0002
#define MX_PSTATE_D3 0x0003
#define MX_PME_EN 0x0010
#define MX_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define MX_PHYADDR_MIN 0x00
#define MX_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001

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/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_pnreg.h,v 1.12 1998/11/23 16:53:26 wpaul Exp $
*/
/*
* PNIC register definitions.
*/
#define PN_BUSCTL 0x00 /* bus control */
#define PN_TXSTART 0x08 /* tx start demand */
#define PN_RXSTART 0x10 /* rx start demand */
#define PN_RXADDR 0x18 /* rx descriptor list start addr */
#define PN_TXADDR 0x20 /* tx descriptor list start addr */
#define PN_ISR 0x28 /* interrupt status register */
#define PN_NETCFG 0x30 /* network config register */
#define PN_IMR 0x38 /* interrupt mask */
#define PN_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define PN_SIO 0x48 /* MII and ROM/EEPROM access */
#define PN_GEN 0x60 /* general purpose register */
#define PN_ENDEC 0x78 /* ENDEC general register */
#define PN_SIOPWR 0x90 /* serial eeprom power up */
#define PN_SIOCTL 0x98 /* EEPROM control register */
#define PN_MII 0xA0 /* MII access register */
#define PN_NWAY 0xB8 /* Internal NWAY register */
/*
* Bus control bits.
*/
#define PN_BUSCTL_RESET 0x00000001
#define PN_BUSCTL_ARBITRATION 0x00000002
#define PN_BUSCTL_SKIPLEN 0x0000007C
#define PN_BUSCTL_BUF_BIGENDIAN 0x00000080
#define PN_BUSCTL_BURSTLEN 0x00003F00
#define PN_BUSCTL_CACHEALIGN 0x0000C000
#define PN_BUSCTL_TXPOLL 0x000E0000
#define PN_SKIPLEN_1LONG 0x00000004
#define PN_SKIPLEN_2LONG 0x00000008
#define PN_SKIPLEN_3LONG 0x00000010
#define PN_SKIPLEN_4LONG 0x00000020
#define PN_SKIPLEN_5LONG 0x00000040
#define PN_CACHEALIGN_8LONG 0x00004000
#define PN_CACHEALIGN_16LONG 0x00008000
#define PN_CACHEALIGN_32LONG 0x0000C000
#define PN_BURSTLEN_USECA 0x00000000
#define PN_BURSTLEN_1LONG 0x00000100
#define PN_BURSTLEN_2LONG 0x00000200
#define PN_BURSTLEN_4LONG 0x00000400
#define PN_BURSTLEN_8LONG 0x00000800
#define PN_BURSTLEN_16LONG 0x00001000
#define PN_BURSTLEN_32LONG 0x00002000
#define PN_TXPOLL_OFF 0x00000000
#define PN_TXPOLL_200U 0x00020000
#define PN_TXPOLL_800U 0x00040000
#define PN_TXPOLL_1600U 0x00060000
#define PN_TXPOLL_12_8M 0x00080000
#define PN_TXPOLL_25_6M 0x000A0000
#define PN_TXPOLL_51_2M 0x000C0000
#define PN_TXPOLL_102_4M 0x000E0000
#define PN_BUSCTL_CONFIG \
(PN_CACHEALIGN_8LONG|PN_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define PN_ISR_TX_OK 0x00000001 /* packet tx ok */
#define PN_ISR_TX_IDLE 0x00000002 /* tx stopped */
#define PN_ISR_TX_NOBUF 0x00000004 /* no tx buffer available */
#define PN_ISR_TX_JABTIMEO 0x00000008 /* jabber timeout */
#define PN_ISR_LINKPASS 0x00000010 /* link test pass */
#define PN_ISR_TX_UNDERRUN 0x00000020 /* transmit underrun */
#define PN_ISR_RX_OK 0x00000040 /* packet rx ok */
#define PN_ISR_RX_NOBUF 0x00000080 /* rx buffer unavailable */
#define PN_ISR_RX_IDLE 0x00000100 /* rx stopped */
#define PN_ISR_RX_WATCHDOG 0x00000200 /* rx watchdog timeo */
#define PN_ISR_TX_EARLY 0x00000400 /* rx watchdog timeo */
#define PN_ISR_BUS_ERR 0x00002000
#define PN_ISR_ABNORMAL 0x00008000
#define PN_ISR_NORMAL 0x00010000
#define PN_ISR_RX_STATE 0x000E0000
#define PN_ISR_TX_STATE 0x00700000
#define PN_ISR_BUSERRTYPE 0x03800000
#define PN_ISR_TXABORT 0x04000000 /* tx abort */
#define PN_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define PN_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define PN_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define PN_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define PN_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define PN_RXSTATE_CLOSE 0x000A0000 /* 101 - close rx desc */
#define PN_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define PN_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define PN_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define PN_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define PN_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define PN_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define PN_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define PN_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define PN_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define PN_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
#define PN_BUSERR_PARITY 0x00000000
#define PN_BUSERR_MASTABRT 0x00800000
#define PN_BUSERR_TGTABRT 0x01000000
#define PN_BUSERR_RSVD1 0x01800000
#define PN_BUSERR_RSVD2 0x02000000
/*
* Network config bits.
*/
#define PN_NETCFG_HASHPERF 0x00000001 /* 0 == perf, 1 == hash */
#define PN_NETCFG_RX_ON 0x00000002
#define PN_NETCFG_HASHONLY 0x00000004 /* 1 == allhash */
#define PN_NETCFG_RX_PASSERR 0x00000008
#define PN_NETCFG_INVERSFILT 0x00000010
#define PN_NETCFG_BACKOFF 0x00000020
#define PN_NETCFG_RX_PROMISC 0x00000040
#define PN_NETCFG_RX_ALLMULTI 0x00000080
#define PN_NETCFG_FLAKYOSC 0x00000100
#define PN_NETCFG_FULLDUPLEX 0x00000200
#define PN_NETCFG_OPERMODE 0x00000C00
#define PN_NETCFG_FORCECOLL 0x00001000
#define PN_NETCFG_TX_ON 0x00002000
#define PN_NETCFG_TX_THRESH 0x0000C000
#define PN_NETCFG_TX_BACKOFF 0x00020000
#define PN_NETCFG_MIIENB 0x00040000 /* 1 == MII, 0 == internal */
#define PN_NETCFG_HEARTBEAT 0x00080000 /* 1 == disabled */
#define PN_NETCFG_TX_IMMEDIATE 0x00100000
#define PN_NETCFG_STORENFWD 0x00200000
#define PN_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10Mbps 0 == 100Mbps */
#define PN_NETCFG_PCS 0x00800000 /* 1 == 100baseTX */
#define PN_NETCFG_NO_RXCRC 0x02000000
#define PN_NETCFG_EXT_ENDEC 0x40000000 /* 1 == ext, 0 == int PHY */
#define PN_OPMODE_NORM 0x00000000
#define PN_OPMODE_INTLOOP 0x00000400
#define PN_OPMODE_EXTLOOP 0x00000800
#define PN_TXTHRESH_72BYTES 0x00000000
#define PN_TXTHRESH_96BYTES 0x00004000
#define PN_TXTHRESH_128BYTES 0x00008000
#define PN_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define PN_IMR_TX_OK 0x00000001 /* packet tx ok */
#define PN_IMR_TX_IDLE 0x00000002 /* tx stopped */
#define PN_IMR_TX_NOBUF 0x00000004 /* no tx buffer available */
#define PN_IMR_TX_JABTIMEO 0x00000008 /* jabber timeout */
#define PN_IMR_LINKPASS 0x00000010 /* link test pass */
#define PN_IMR_TX_UNDERRUN 0x00000020 /* transmit underrun */
#define PN_IMR_RX_OK 0x00000040 /* packet rx ok */
#define PN_IMR_RX_NOBUF 0x00000080 /* rx buffer unavailable */
#define PN_IMR_RX_IDLE 0x00000100 /* rx stopped */
#define PN_IMR_RX_WATCHDOG 0x00000200 /* rx watchdog timeo */
#define PN_IMR_TX_EARLY 0x00000400 /* rx watchdog timeo */
#define PN_IMR_BUS_ERR 0x00002000
#define PN_IMR_ABNORMAL 0x00008000
#define PN_IMR_NORMAL 0x00010000
#define PN_ISR_TXABORT 0x04000000 /* tx abort */
#define PN_INTRS \
(PN_IMR_RX_OK|PN_IMR_TX_OK|PN_IMR_RX_NOBUF| \
PN_IMR_TX_NOBUF|PN_IMR_TX_UNDERRUN|PN_IMR_BUS_ERR| \
PN_IMR_ABNORMAL|PN_IMR_NORMAL)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define PN_SIO_DATA 0x0000003F
#define PN_SIO_OPCODE 0x00000300
#define PN_SIO_BUSY 0x80000000
/*
* SIOCTL/EEPROM bits
*/
#define PN_EE_READ 0x600
/*
* General purpose register bits.
*/
#define PN_GEN_CTL 0x000000F0
#define PN_GEN_100TX_LINK 0x00000008
#define PN_GEN_BNC_ENB 0x00000004
#define PN_GEN_100TX_LOOP 0x00000002 /* 1 == normal, 0 == loop */
#define PN_GEN_SPEEDSEL 0x00000001 /* 1 == 100Mbps, 0 == 10Mbps */
#define PN_GEN_MUSTBEONE 0x00000030
/*
* General ENDEC bits.
*/
#define PN_ENDEC_JABBERDIS 0x000000001 /* 1 == disable, 0 == enable */
/*
* MII bits.
*/
#define PN_MII_DATA 0x0000FFFF
#define PN_MII_REGADDR 0x007C0000
#define PN_MII_PHYADDR 0x0F800000
#define PN_MII_OPCODE 0x30000000
#define PN_MII_RESERVED 0x00020000
#define PN_MII_BUSY 0x80000000
#define PN_MII_READ 0x60020000 /* read PHY command */
#define PN_MII_WRITE 0x50020000 /* write PHY command */
/*
* Internal PHY NWAY register bits.
*/
#define PN_NWAY_RESET 0x00000001 /* reset */
#define PN_NWAY_PDOWN 0x00000002 /* power down */
#define PN_NWAY_BYPASS 0x00000004 /* bypass */
#define PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
#define PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
#define PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
#define PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
#define PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
#define PN_NWAY_DUPLEX 0x00000100 /* 1 == full, 0 == half */
#define PN_NWAY_LINKTEST 0x00000200 /* 1 == on, 0 == off */
#define PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
#define PN_NWAY_SPEEDSEL 0x00000800 /* 0 == 10, 1 == 100 */
#define PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
#define PN_NWAY_CAP10HALF 0x00002000
#define PN_NWAY_CAP10FULL 0x00004000
#define PN_NWAY_CAP100FULL 0x00008000
#define PN_NWAY_CAP100HALF 0x00010000
#define PN_NWAY_CAP100T4 0x00020000
#define PN_NWAY_AUTONEGRSTR 0x02000000
#define PN_NWAY_REMFAULT 0x04000000
#define PN_NWAY_LPAR10HALF 0x08000000
#define PN_NWAY_LPAR10FULL 0x10000000
#define PN_NWAY_LPAR100FULL 0x20000000
#define PN_NWAY_LPAR100HALF 0x40000000
#define PN_NWAY_LPAR100T4 0x80000000
/*
* Size of a setup frame.
*/
#define PN_SFRAME_LEN 192
/*
* PNIC TX/RX list structure.
*/
struct pn_desc {
u_int32_t pn_status;
u_int32_t pn_ctl;
u_int32_t pn_ptr1;
u_int32_t pn_ptr2;
};
#define pn_data pn_ptr1
#define pn_next pn_ptr2
#define RX_RXSTAT_FIFOOFLOW 0x00000001
#define PN_RXSTAT_CRCERR 0x00000002
#define PN_RXSTAT_DRIBBLE 0x00000004
#define PN_RXSTAT_WATCHDOG 0x00000010
#define PN_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define PN_RXSTAT_COLLSEEN 0x00000040
#define PN_RXSTAT_GIANT 0x00000080
#define PN_RXSTAT_LASTFRAG 0x00000100
#define PN_RXSTAT_FIRSTFRAG 0x00000200
#define PN_RXSTAT_MULTICAST 0x00000400
#define PN_RXSTAT_RUNT 0x00000800
#define PN_RXSTAT_RXTYPE 0x00003000
#define PN_RXSTAT_RXERR 0x00008000
#define PN_RXSTAT_RXLEN 0x7FFF0000
#define PN_RXSTAT_OWN 0x80000000
#define PN_RXBYTES(x) ((x & PN_RXSTAT_RXLEN) >> 16)
#define PN_RXSTAT (PN_RXSTAT_FIRSTFRAG|PN_RXSTAT_LASTFRAG|PN_RXSTAT_OWN)
#define PN_RXCTL_BUFLEN1 0x00000FFF
#define PN_RXCTL_BUFLEN2 0x00FFF000
#define PN_RXCTL_RLINK 0x01000000
#define PN_RXCTL_RLAST 0x02000000
#define PN_TXSTAT_DEFER 0x00000001
#define PN_TXSTAT_UNDERRUN 0x00000002
#define PN_TXSTAT_LINKFAIL 0x00000003
#define PN_TXSTAT_COLLCNT 0x00000078
#define PN_TXSTAT_SQE 0x00000080
#define PN_TXSTAT_EXCESSCOLL 0x00000100
#define PN_TXSTAT_LATECOLL 0x00000200
#define PN_TXSTAT_NOCARRIER 0x00000400
#define PN_TXSTAT_CARRLOST 0x00000800
#define PN_TXSTAT_JABTIMEO 0x00004000
#define PN_TXSTAT_ERRSUM 0x00008000
#define PN_TXSTAT_OWN 0x80000000
#define PN_TXCTL_BUFLEN1 0x000007FF
#define PN_TXCTL_BUFLEN2 0x003FF800
#define PN_TXCTL_FILTTYPE0 0x00400000
#define PN_TXCTL_PAD 0x00800000
#define PN_TXCTL_TLINK 0x01000000
#define PN_TXCTL_TLAST 0x02000000
#define PN_TXCTL_NOCRC 0x04000000
#define PN_TXCTL_SETUP 0x08000000
#define PN_TXCTL_FILTTYPE1 0x10000000
#define PN_TXCTL_FIRSTFRAG 0x20000000
#define PN_TXCTL_LASTFRAG 0x40000000
#define PN_TXCTL_FINT 0x80000000
#define PN_FILTER_PERFECT 0x00000000
#define PN_FILTER_HASHPERF 0x00400000
#define PN_FILTER_INVERSE 0x10000000
#define PN_FILTER_HASHONLY 0x10400000
#define PN_MAXFRAGS 16
#define PN_RX_LIST_CNT 64
#define PN_TX_LIST_CNT 64
#define PN_MIN_FRAMELEN 60
#define PN_FRAMELEN 1536
/*
* A tx 'super descriptor' is actually 16 regular descriptors
* back to back.
*/
struct pn_txdesc {
struct pn_desc pn_frag[PN_MAXFRAGS];
};
#define PN_TXNEXT(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_next
#define PN_TXSTATUS(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_status
#define PN_TXCTL(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_ctl
#define PN_TXDATA(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_data
#define PN_TXOWN(x) x->pn_ptr->pn_frag[0].pn_status
#define PN_UNSENT 0x12344321
struct pn_list_data {
struct pn_desc pn_rx_list[PN_RX_LIST_CNT];
struct pn_txdesc pn_tx_list[PN_TX_LIST_CNT];
};
struct pn_chain {
struct pn_txdesc *pn_ptr;
struct mbuf *pn_mbuf;
struct pn_chain *pn_nextdesc;
u_int8_t pn_lastdesc;
};
struct pn_chain_onefrag {
struct pn_desc *pn_ptr;
struct mbuf *pn_mbuf;
struct pn_chain_onefrag *pn_nextdesc;
};
struct pn_chain_data {
struct pn_desc pn_sframe;
u_int32_t pn_sbuf[PN_SFRAME_LEN/sizeof(u_int32_t)];
struct pn_chain_onefrag pn_rx_chain[PN_RX_LIST_CNT];
struct pn_chain pn_tx_chain[PN_TX_LIST_CNT];
struct pn_chain_onefrag *pn_rx_head;
struct pn_chain *pn_tx_head;
struct pn_chain *pn_tx_tail;
struct pn_chain *pn_tx_free;
};
struct pn_type {
u_int16_t pn_vid;
u_int16_t pn_did;
char *pn_name;
};
struct pn_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define PN_MII_STARTDELIM 0x01
#define PN_MII_READOP 0x02
#define PN_MII_WRITEOP 0x01
#define PN_MII_TURNAROUND 0x02
#define PN_FLAG_FORCEDELAY 1
#define PN_FLAG_SCHEDDELAY 2
#define PN_FLAG_DELAYTIMEO 3
struct pn_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t pn_bhandle; /* bus space handle */
bus_space_tag_t pn_btag; /* bus space tag */
struct pn_type *pn_info; /* PNIC adapter info */
struct pn_type *pn_pinfo; /* phy info */
u_int8_t pn_unit; /* interface number */
u_int8_t pn_type;
u_int8_t pn_phy_addr; /* PHY address */
u_int8_t pn_tx_pend; /* TX pending */
u_int8_t pn_want_auto;
u_int8_t pn_autoneg;
caddr_t pn_ldata_ptr;
struct pn_list_data *pn_ldata;
struct pn_chain_data pn_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->pn_btag, sc->pn_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->pn_btag, sc->pn_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->pn_btag, sc->pn_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->pn_btag, sc->pn_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->pn_btag, sc->pn_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->pn_btag, sc->pn_bhandle, reg)
#define PN_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* Lite-On PNIC PCI vendor ID
*/
#define PN_VENDORID 0x11AD
/*
* Lite-On PNIC PCI device ID.
*/
#define PN_DEVICEID_PNIC 0x0002
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define PN_PCI_VENDOR_ID 0x00
#define PN_PCI_DEVICE_ID 0x02
#define PN_PCI_COMMAND 0x04
#define PN_PCI_STATUS 0x06
#define PN_PCI_CLASSCODE 0x09
#define PN_PCI_LATENCY_TIMER 0x0D
#define PN_PCI_HEADER_TYPE 0x0E
#define PN_PCI_LOIO 0x10
#define PN_PCI_LOMEM 0x14
#define PN_PCI_BIOSROM 0x30
#define PN_PCI_INTLINE 0x3C
#define PN_PCI_INTPIN 0x3D
#define PN_PCI_MINGNT 0x3E
#define PN_PCI_MINLAT 0x0F
#define PN_PCI_RESETOPT 0x48
#define PN_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define PN_PCI_CAPID 0xDC /* 8 bits */
#define PN_PCI_NEXTPTR 0xDD /* 8 bits */
#define PN_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define PN_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define PN_PSTATE_MASK 0x0003
#define PN_PSTATE_D0 0x0000
#define PN_PSTATE_D1 0x0002
#define PN_PSTATE_D2 0x0002
#define PN_PSTATE_D3 0x0003
#define PN_PME_EN 0x0010
#define PN_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define PN_PHYADDR_MIN 0x00
#define PN_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001

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/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_vrreg.h,v 1.8 1998/12/01 22:08:11 wpaul Exp $
*/
/*
* Rhine register definitions.
*/
#define VR_PAR0 0x00 /* node address 0 to 4 */
#define VR_PAR1 0x04 /* node address 2 to 6 */
#define VR_RXCFG 0x06 /* receiver config register */
#define VR_TXCFG 0x07 /* transmit config register */
#define VR_COMMAND 0x08 /* command register */
#define VR_ISR 0x0C /* interrupt/status register */
#define VR_IMR 0x0E /* interrupt mask register */
#define VR_MAR0 0x10 /* multicast hash 0 */
#define VR_MAR1 0x14 /* multicast hash 1 */
#define VR_RXADDR 0x18 /* rx descriptor list start addr */
#define VR_TXADDR 0x1C /* tx descriptor list start addr */
#define VR_CURRXDESC0 0x20
#define VR_CURRXDESC1 0x24
#define VR_CURRXDESC2 0x28
#define VR_CURRXDESC3 0x2C
#define VR_NEXTRXDESC0 0x30
#define VR_NEXTRXDESC1 0x34
#define VR_NEXTRXDESC2 0x38
#define VR_NEXTRXDESC3 0x3C
#define VR_CURTXDESC0 0x40
#define VR_CURTXDESC1 0x44
#define VR_CURTXDESC2 0x48
#define VR_CURTXDESC3 0x4C
#define VR_NEXTTXDESC0 0x50
#define VR_NEXTTXDESC1 0x54
#define VR_NEXTTXDESC2 0x58
#define VR_NEXTTXDESC3 0x5C
#define VR_CURRXDMA 0x60 /* current RX DMA address */
#define VR_CURTXDMA 0x64 /* current TX DMA address */
#define VR_TALLYCNT 0x68 /* tally counter test register */
#define VR_PHYADDR 0x6C
#define VR_MIISTAT 0x6D
#define VR_BCR0 0x6E
#define VR_BCR1 0x6F
#define VR_MIICMD 0x70
#define VR_MIIADDR 0x71
#define VR_MIIDATA 0x72
#define VR_EECSR 0x74
#define VR_TEST 0x75
#define VR_GPIO 0x76
#define VR_CONFIG 0x78
#define VR_MPA_CNT 0x7C
#define VR_CRC_CNT 0x7E
/*
* RX config bits.
*/
#define VR_RXCFG_RX_ERRPKTS 0x01
#define VR_RXCFG_RX_RUNT 0x02
#define VR_RXCFG_RX_MULTI 0x04
#define VR_RXCFG_RX_BROAD 0x08
#define VR_RXCFG_RX_PROMISC 0x10
#define VR_RXCFG_RX_THRESH 0xE0
#define VR_RXTHRESH_32BYTES 0x00
#define VR_RXTHRESH_64BYTES 0x20
#define VR_RXTHRESH_128BYTES 0x40
#define VR_RXTHRESH_256BYTES 0x60
#define VR_RXTHRESH_512BYTES 0x80
#define VR_RXTHRESH_768BYTES 0xA0
#define VR_RXTHRESH_1024BYTES 0xC0
#define VR_RXTHRESH_STORENFWD 0xE0
/*
* TX config bits.
*/
#define VR_TXCFG_RSVD0 0x01
#define VR_TXCFG_LOOPBKMODE 0x06
#define VR_TXCFG_BACKOFF 0x08
#define VR_TXCFG_RSVD1 0x10
#define VR_TXCFG_TX_THRESH 0xE0
#define VR_TXTHRESH_32BYTES 0x00
#define VR_TXTHRESH_64BYTES 0x20
#define VR_TXTHRESH_128BYTES 0x40
#define VR_TXTHRESH_256BYTES 0x60
#define VR_TXTHRESH_512BYTES 0x80
#define VR_TXTHRESH_768BYTES 0xA0
#define VR_TXTHRESH_1024BYTES 0xC0
#define VR_TXTHRESH_STORENFWD 0xE0
/*
* Command register bits.
*/
#define VR_CMD_INIT 0x0001
#define VR_CMD_START 0x0002
#define VR_CMD_STOP 0x0004
#define VR_CMD_RX_ON 0x0008
#define VR_CMD_TX_ON 0x0010
#define VR_CMD_TX_GO 0x0020
#define VR_CMD_RX_GO 0x0040
#define VR_CMD_RSVD 0x0080
#define VR_CMD_RX_EARLY 0x0100
#define VR_CMD_TX_EARLY 0x0200
#define VR_CMD_FULLDUPLEX 0x0400
#define VR_CMD_TX_NOPOLL 0x0800
#define VR_CMD_RESET 0x8000
/*
* Interrupt status bits.
*/
#define VR_ISR_RX_OK 0x0001 /* packet rx ok */
#define VR_ISR_TX_OK 0x0002 /* packet tx ok */
#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_ISR_BUSERR 0x0040 /* PCI bus error */
#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_ISR_RX_EARLY 0x0100 /* rx early */
#define VR_ISR_LINKSTAT 0x0200 /* MII status change */
#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_ISR_RX_DROPPED 0x0800
#define VR_ISR_RX_NOBUF2 0x1000
#define VR_ISR_TX_ABRT2 0x2000
#define VR_ISR_LINKSTAT2 0x4000
#define VR_ISR_MAGICPACKET 0x8000
/*
* Interrupt mask bits.
*/
#define VR_IMR_RX_OK 0x0001 /* packet rx ok */
#define VR_IMR_TX_OK 0x0002 /* packet tx ok */
#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
#define VR_IMR_BUSERR 0x0040 /* PCI bus error */
#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
#define VR_IMR_RX_EARLY 0x0100 /* rx early */
#define VR_IMR_LINKSTAT 0x0200 /* MII status change */
#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
#define VR_IMR_RX_DROPPED 0x0800
#define VR_IMR_RX_NOBUF2 0x1000
#define VR_IMR_TX_ABRT2 0x2000
#define VR_IMR_LINKSTAT2 0x4000
#define VR_IMR_MAGICPACKET 0x8000
#define VR_INTRS \
(VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
/*
* MII status register.
*/
#define VR_MIISTAT_SPEED 0x01
#define VR_MIISTAT_LINKFAULT 0x02
#define VR_MIISTAT_MGTREADERR 0x04
#define VR_MIISTAT_MIIERR 0x08
#define VR_MIISTAT_PHYOPT 0x10
#define VR_MIISTAT_MDC_SPEED 0x20
#define VR_MIISTAT_RSVD 0x40
#define VR_MIISTAT_GPIO1POLL 0x80
/*
* MII command register bits.
*/
#define VR_MIICMD_CLK 0x01
#define VR_MIICMD_DATAOUT 0x02
#define VR_MIICMD_DATAIN 0x04
#define VR_MIICMD_DIR 0x08
#define VR_MIICMD_DIRECTPGM 0x10
#define VR_MIICMD_WRITE_ENB 0x20
#define VR_MIICMD_READ_ENB 0x40
#define VR_MIICMD_AUTOPOLL 0x80
/*
* EEPROM control bits.
*/
#define VR_EECSR_DATAIN 0x01 /* data out */
#define VR_EECSR_DATAOUT 0x02 /* data in */
#define VR_EECSR_CLK 0x04 /* clock */
#define VR_EECSR_CS 0x08 /* chip select */
#define VR_EECSR_DPM 0x10
#define VR_EECSR_LOAD 0x20
#define VR_EECSR_EMBP 0x40
#define VR_EECSR_EEPR 0x80
#define VR_EECMD_WRITE 0x140
#define VR_EECMD_READ 0x180
#define VR_EECMD_ERASE 0x1c0
/*
* Test register bits.
*/
#define VR_TEST_TEST0 0x01
#define VR_TEST_TEST1 0x02
#define VR_TEST_TEST2 0x04
#define VR_TEST_TSTUD 0x08
#define VR_TEST_TSTOV 0x10
#define VR_TEST_BKOFF 0x20
#define VR_TEST_FCOL 0x40
#define VR_TEST_HBDES 0x80
/*
* Config register bits.
*/
#define VR_CFG_GPIO2OUTENB 0x00000001
#define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */
#define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */
#define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */
#define VR_CFG_MIIOPT 0x00000010
#define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */
#define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */
#define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */
#define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */
#define VR_CFG_MRREADWAIT 0x00000200
#define VR_CFG_MRWRITEWAIT 0x00000400
#define VR_CFG_RX_ARB 0x00000800
#define VR_CFG_TX_ARB 0x00001000
#define VR_CFG_READMULTI 0x00002000
#define VR_CFG_TX_PACE 0x00004000
#define VR_CFG_TX_QDIS 0x00008000
#define VR_CFG_ROMSEL0 0x00010000
#define VR_CFG_ROMSEL1 0x00020000
#define VR_CFG_ROMSEL2 0x00040000
#define VR_CFG_ROMTIMESEL 0x00080000
#define VR_CFG_RSVD0 0x00100000
#define VR_CFG_ROMDLY 0x00200000
#define VR_CFG_ROMOPT 0x00400000
#define VR_CFG_RSVD1 0x00800000
#define VR_CFG_BACKOFFOPT 0x01000000
#define VR_CFG_BACKOFFMOD 0x02000000
#define VR_CFG_CAPEFFECT 0x04000000
#define VR_CFG_BACKOFFRAND 0x08000000
#define VR_CFG_MAGICKPACKET 0x10000000
#define VR_CFG_PCIREADLINE 0x20000000
#define VR_CFG_DIAG 0x40000000
#define VR_CFG_GPIOEN 0x80000000
/*
* Rhine TX/RX list structure.
*/
struct vr_desc {
u_int32_t vr_status;
u_int32_t vr_ctl;
u_int32_t vr_ptr1;
u_int32_t vr_ptr2;
};
#define vr_data vr_ptr1
#define vr_next vr_ptr2
#define VR_RXSTAT_RXERR 0x00000001
#define VR_RXSTAT_CRCERR 0x00000002
#define VR_RXSTAT_FRAMEALIGNERR 0x00000004
#define VR_RXSTAT_FIFOOFLOW 0x00000008
#define VR_RXSTAT_GIANT 0x00000010
#define VR_RXSTAT_RUNT 0x00000020
#define VR_RXSTAT_BUSERR 0x00000040
#define VR_RXSTAT_BUFFERR 0x00000080
#define VR_RXSTAT_LASTFRAG 0x00000100
#define VR_RXSTAT_FIRSTFRAG 0x00000200
#define VR_RXSTAT_RLINK 0x00000400
#define VR_RXSTAT_RX_PHYS 0x00000800
#define VR_RXSTAT_RX_BROAD 0x00001000
#define VR_RXSTAT_RX_MULTI 0x00002000
#define VR_RXSTAT_RX_OK 0x00004000
#define VR_RXSTAT_RXLEN 0x07FF0000
#define VR_RXSTAT_RXLEN_EXT 0x78000000
#define VR_RXSTAT_OWN 0x80000000
#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
#define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN)
#define VR_RXCTL_BUFLEN 0x000007FF
#define VR_RXCTL_BUFLEN_EXT 0x00007800
#define VR_RXCTL_CHAIN 0x00008000
#define VR_RXCTL_RX_INTR 0x00800000
#define VR_TXSTAT_DEFER 0x00000001
#define VR_TXSTAT_UNDERRUN 0x00000002
#define VR_TXSTAT_COLLCNT 0x00000078
#define VR_TXSTAT_SQE 0x00000080
#define VR_TXSTAT_ABRT 0x00000100
#define VR_TXSTAT_LATECOLL 0x00000200
#define VR_TXSTAT_CARRLOST 0x00000400
#define VR_TXSTAT_BUSERR 0x00002000
#define VR_TXSTAT_JABTIMEO 0x00004000
#define VR_TXSTAT_ERRSUM 0x00008000
#define VR_TXSTAT_OWN 0x80000000
#define VR_TXCTL_BUFLEN 0x000007FF
#define VR_TXCTL_BUFLEN_EXT 0x00007800
#define VR_TXCTL_TLINK 0x00008000
#define VR_TXCTL_FIRSTFRAG 0x00200000
#define VR_TXCTL_LASTFRAG 0x00400000
#define VR_TXCTL_FINT 0x00800000
#define VR_MAXFRAGS 16
#define VR_RX_LIST_CNT 64
#define VR_TX_LIST_CNT 64
#define VR_MIN_FRAMELEN 60
#define VR_FRAMELEN 1536
#define VR_TXOWN(x) x->vr_ptr->vr_status
#define VR_UNSENT 0x12341234
struct vr_list_data {
struct vr_desc vr_rx_list[VR_RX_LIST_CNT];
struct vr_desc vr_tx_list[VR_TX_LIST_CNT];
};
struct vr_chain {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain *vr_nextdesc;
};
struct vr_chain_onefrag {
struct vr_desc *vr_ptr;
struct mbuf *vr_mbuf;
struct vr_chain_onefrag *vr_nextdesc;
};
struct vr_chain_data {
struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT];
struct vr_chain vr_tx_chain[VR_TX_LIST_CNT];
struct vr_chain_onefrag *vr_rx_head;
struct vr_chain *vr_tx_head;
struct vr_chain *vr_tx_tail;
struct vr_chain *vr_tx_free;
};
struct vr_type {
u_int16_t vr_vid;
u_int16_t vr_did;
char *vr_name;
};
struct vr_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define VR_MII_STARTDELIM 0x01
#define VR_MII_READOP 0x02
#define VR_MII_WRITEOP 0x01
#define VR_MII_TURNAROUND 0x02
#define VR_FLAG_FORCEDELAY 1
#define VR_FLAG_SCHEDDELAY 2
#define VR_FLAG_DELAYTIMEO 3
struct vr_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t vr_bhandle; /* bus space handle */
bus_space_tag_t vr_btag; /* bus space tag */
struct vr_type *vr_info; /* Rhine adapter info */
struct vr_type *vr_pinfo; /* phy info */
u_int8_t vr_unit; /* interface number */
u_int8_t vr_type;
u_int8_t vr_phy_addr; /* PHY address */
u_int8_t vr_tx_pend; /* TX pending */
u_int8_t vr_want_auto;
u_int8_t vr_autoneg;
caddr_t vr_ldata_ptr;
struct vr_list_data *vr_ldata;
struct vr_chain_data vr_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
#define VR_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* VIA vendor ID
*/
#define VIA_VENDORID 0x1106
/*
* VIA Rhine device IDs.
*/
#define VIA_DEVICEID_RHINE 0x3043
#define VIA_DEVICEID_RHINE_II 0x6100
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define VR_PCI_VENDOR_ID 0x00
#define VR_PCI_DEVICE_ID 0x02
#define VR_PCI_COMMAND 0x04
#define VR_PCI_STATUS 0x06
#define VR_PCI_CLASSCODE 0x09
#define VR_PCI_LATENCY_TIMER 0x0D
#define VR_PCI_HEADER_TYPE 0x0E
#define VR_PCI_LOIO 0x10
#define VR_PCI_LOMEM 0x14
#define VR_PCI_BIOSROM 0x30
#define VR_PCI_INTLINE 0x3C
#define VR_PCI_INTPIN 0x3D
#define VR_PCI_MINGNT 0x3E
#define VR_PCI_MINLAT 0x0F
#define VR_PCI_RESETOPT 0x48
#define VR_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define VR_PCI_CAPID 0xDC /* 8 bits */
#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define VR_PSTATE_MASK 0x0003
#define VR_PSTATE_D0 0x0000
#define VR_PSTATE_D1 0x0002
#define VR_PSTATE_D2 0x0002
#define VR_PSTATE_D3 0x0003
#define VR_PME_EN 0x0010
#define VR_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define VR_PHYADDR_MIN 0x00
#define VR_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001

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/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_wbreg.h,v 1.12 1998/11/29 06:40:50 wpaul Exp $
*/
/*
* Winbond register definitions.
*/
#define WB_BUSCTL 0x00 /* bus control */
#define WB_TXSTART 0x04 /* tx start demand */
#define WB_RXSTART 0x08 /* rx start demand */
#define WB_RXADDR 0x0C /* rx descriptor list start addr */
#define WB_TXADDR 0x10 /* tx descriptor list start addr */
#define WB_ISR 0x14 /* interrupt status register */
#define WB_NETCFG 0x18 /* network config register */
#define WB_IMR 0x1C /* interrupt mask */
#define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */
#define WB_SIO 0x24 /* MII and ROM/EEPROM access */
#define WB_BOOTROMADDR 0x28
#define WB_TIMER 0x2C /* general timer */
#define WB_CURRXCTL 0x30 /* current RX descriptor */
#define WB_CURRXBUF 0x34 /* current RX buffer */
#define WB_MAR0 0x38 /* multicast filter 0 */
#define WB_MAR1 0x3C /* multicast filter 1 */
#define WB_NODE0 0x40 /* station address 0 */
#define WB_NODE1 0x44 /* station address 1 */
#define WB_BOOTROMSIZE 0x48 /* boot ROM size */
#define WB_CURTXCTL 0x4C /* current TX descriptor */
#define WB_CURTXBUF 0x50 /* current TX buffer */
/*
* Bus control bits.
*/
#define WB_BUSCTL_RESET 0x00000001
#define WB_BUSCTL_ARBITRATION 0x00000002
#define WB_BUSCTL_SKIPLEN 0x0000007C
#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
#define WB_BUSCTL_BURSTLEN 0x00003F00
#define WB_BUSCTL_CACHEALIGN 0x0000C000
#define WB_BUSCTL_DES_BIGENDIAN 0x00100000
#define WB_BUSCTL_WAIT 0x00200000
#define WB_SKIPLEN_1LONG 0x00000004
#define WB_SKIPLEN_2LONG 0x00000008
#define WB_SKIPLEN_3LONG 0x00000010
#define WB_SKIPLEN_4LONG 0x00000020
#define WB_SKIPLEN_5LONG 0x00000040
#define WB_CACHEALIGN_8LONG 0x00004000
#define WB_CACHEALIGN_16LONG 0x00008000
#define WB_CACHEALIGN_32LONG 0x0000C000
#define WB_BURSTLEN_USECA 0x00000000
#define WB_BURSTLEN_1LONG 0x00000100
#define WB_BURSTLEN_2LONG 0x00000200
#define WB_BURSTLEN_4LONG 0x00000400
#define WB_BURSTLEN_8LONG 0x00000800
#define WB_BURSTLEN_16LONG 0x00001000
#define WB_BURSTLEN_32LONG 0x00002000
#define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
WB_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define WB_ISR_TX_OK 0x00000001
#define WB_ISR_TX_IDLE 0x00000002
#define WB_ISR_TX_NOBUF 0x00000004
#define WB_ISR_RX_EARLY 0x00000008
#define WB_ISR_RX_ERR 0x00000010
#define WB_ISR_TX_UNDERRUN 0x00000020
#define WB_ISR_RX_OK 0x00000040
#define WB_ISR_RX_NOBUF 0x00000080
#define WB_ISR_RX_IDLE 0x00000100
#define WB_ISR_TX_EARLY 0x00000400
#define WB_ISR_TIMER_EXPIRED 0x00000800
#define WB_ISR_BUS_ERR 0x00002000
#define WB_ISR_ABNORMAL 0x00008000
#define WB_ISR_NORMAL 0x00010000
#define WB_ISR_RX_STATE 0x000E0000
#define WB_ISR_TX_STATE 0x00700000
#define WB_ISR_BUSERRTYPE 0x03800000
/*
* The RX_STATE and TX_STATE fields are not described anywhere in the
* Winbond datasheet, however it appears that the Winbond chip is an
* attempt at a DEC 'tulip' clone, hence the ISR register is identical
* to that of the tulip chip and we can steal the bit definitions from
* the tulip documentation.
*/
#define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define WB_NETCFG_RX_ON 0x00000002
#define WB_NETCFG_RX_ALLPHYS 0x00000008
#define WB_NETCFG_RX_MULTI 0x00000010
#define WB_NETCFG_RX_BROAD 0x00000020
#define WB_NETCFG_RX_RUNT 0x00000040
#define WB_NETCFG_RX_ERR 0x00000080
#define WB_NETCFG_FULLDUPLEX 0x00000200
#define WB_NETCFG_LOOPBACK 0x00000C00
#define WB_NETCFG_TX_ON 0x00002000
#define WB_NETCFG_TX_THRESH 0x001FC000
#define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000
#define WB_NETCFG_100MBPS 0x20000000
#define WB_NETCFG_TX_EARLY_ON 0x40000000
#define WB_NETCFG_RX_EARLY_ON 0x80000000
/*
* The tx threshold can be adjusted in increments of 32 bytes.
*/
#define WB_TXTHRESH(x) ((x >> 5) << 14)
#define WB_TXTHRESH_CHUNK 32
#define WB_TXTHRESH_INIT 72
/*
* Interrupt mask bits.
*/
#define WB_IMR_TX_OK 0x00000001
#define WB_IMR_TX_IDLE 0x00000002
#define WB_IMR_TX_NOBUF 0x00000004
#define WB_IMR_RX_EARLY 0x00000008
#define WB_IMR_RX_ERR 0x00000010
#define WB_IMR_TX_UNDERRUN 0x00000020
#define WB_IMR_RX_OK 0x00000040
#define WB_IMR_RX_NOBUF 0x00000080
#define WB_IMR_RX_IDLE 0x00000100
#define WB_IMR_TX_EARLY 0x00000400
#define WB_IMR_TIMER_EXPIRED 0x00000800
#define WB_IMR_BUS_ERR 0x00002000
#define WB_IMR_ABNORMAL 0x00008000
#define WB_IMR_NORMAL 0x00010000
#define WB_INTRS \
(WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \
WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \
WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define WB_SIO_ROMDATA4 0x00000010
#define WB_SIO_ROMDATA5 0x00000020
#define WB_SIO_ROMDATA6 0x00000040
#define WB_SIO_ROMDATA7 0x00000080
#define WB_SIO_ROMCTL_WRITE 0x00000200
#define WB_SIO_ROMCTL_READ 0x00000400
#define WB_SIO_EESEL 0x00000800
#define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */
#define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */
#define WB_EECMD_WRITE 0x140
#define WB_EECMD_READ 0x180
#define WB_EECMD_ERASE 0x1c0
/*
* Winbond TX/RX descriptor structure.
*/
struct wb_desc {
u_int32_t wb_status;
u_int32_t wb_ctl;
u_int32_t wb_ptr1;
u_int32_t wb_ptr2;
};
#define wb_data wb_ptr1
#define wb_next wb_ptr2
#define WB_RXSTAT_CRCERR 0x00000002
#define WB_RXSTAT_DRIBBLE 0x00000004
#define WB_RXSTAT_MIIERR 0x00000008
#define WB_RXSTAT_LATEEVENT 0x00000040
#define WB_RXSTAT_GIANT 0x00000080
#define WB_RXSTAT_LASTFRAG 0x00000100
#define WB_RXSTAT_FIRSTFRAG 0x00000200
#define WB_RXSTAT_MULTICAST 0x00000400
#define WB_RXSTAT_RUNT 0x00000800
#define WB_RXSTAT_RXTYPE 0x00003000
#define WB_RXSTAT_RXERR 0x00008000
#define WB_RXSTAT_RXLEN 0x3FFF0000
#define WB_RXSTAT_RXCMP 0x40000000
#define WB_RXSTAT_OWN 0x80000000
#define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16)
#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
#define WB_RXCTL_BUFLEN1 0x00000FFF
#define WB_RXCTL_BUFLEN2 0x00FFF000
#define WB_RXCTL_RLINK 0x01000000
#define WB_RXCTL_RLAST 0x02000000
#define WB_TXSTAT_DEFER 0x00000001
#define WB_TXSTAT_UNDERRUN 0x00000002
#define WB_TXSTAT_COLLCNT 0x00000078
#define WB_TXSTAT_SQE 0x00000080
#define WB_TXSTAT_ABORT 0x00000100
#define WB_TXSTAT_LATECOLL 0x00000200
#define WB_TXSTAT_NOCARRIER 0x00000400
#define WB_TXSTAT_CARRLOST 0x00000800
#define WB_TXSTAT_TXERR 0x00001000
#define WB_TXSTAT_OWN 0x80000000
#define WB_TXCTL_BUFLEN1 0x000007FF
#define WB_TXCTL_BUFLEN2 0x003FF800
#define WB_TXCTL_PAD 0x00800000
#define WB_TXCTL_TLINK 0x01000000
#define WB_TXCTL_TLAST 0x02000000
#define WB_TXCTL_NOCRC 0x08000000
#define WB_TXCTL_FIRSTFRAG 0x20000000
#define WB_TXCTL_LASTFRAG 0x40000000
#define WB_TXCTL_FINT 0x80000000
#define WB_MAXFRAGS 16
#define WB_RX_LIST_CNT 64
#define WB_TX_LIST_CNT 64
#define WB_MIN_FRAMELEN 60
/*
* A transmit 'super descriptor' is actually WB_MAXFRAGS regular
* descriptors clumped together. The idea here is to emulate the
* multi-fragment descriptor layout found in devices such as the
* Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
* The advantage to using this scheme is that it avoids buffer copies.
* The disadvantage is that there's a certain amount of overhead due
* to the fact that each 'fragment' is 16 bytes long. In my tests,
* this limits top speed to about 10.5MB/sec. It should be more like
* 11.5MB/sec. However, the upshot is that you can achieve better
* results on slower machines: a Pentium 200 can pump out packets at
* same speed as a PII 400.
*/
struct wb_txdesc {
struct wb_desc wb_frag[WB_MAXFRAGS];
};
#define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
#define WB_UNSENT 0x1234
struct wb_list_data {
struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
};
struct wb_chain {
struct wb_txdesc *wb_ptr;
struct mbuf *wb_mbuf;
struct wb_chain *wb_nextdesc;
u_int8_t wb_lastdesc;
};
struct wb_chain_onefrag {
struct wb_desc *wb_ptr;
struct mbuf *wb_mbuf;
struct wb_chain_onefrag *wb_nextdesc;
u_int8_t wb_rlast;
};
struct wb_chain_data {
u_int8_t wb_pad[WB_MIN_FRAMELEN];
struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];
struct wb_chain_onefrag *wb_rx_head;
struct wb_chain *wb_tx_head;
struct wb_chain *wb_tx_tail;
struct wb_chain *wb_tx_free;
};
struct wb_type {
u_int16_t wb_vid;
u_int16_t wb_did;
char *wb_name;
};
struct wb_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define WB_MII_STARTDELIM 0x01
#define WB_MII_READOP 0x02
#define WB_MII_WRITEOP 0x01
#define WB_MII_TURNAROUND 0x02
#define WB_FLAG_FORCEDELAY 1
#define WB_FLAG_SCHEDDELAY 2
#define WB_FLAG_DELAYTIMEO 3
struct wb_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t wb_bhandle;
bus_space_tag_t wb_btag;
struct wb_type *wb_info; /* 3Com adapter info */
struct wb_type *wb_pinfo; /* phy info */
u_int8_t wb_unit; /* interface number */
u_int8_t wb_type;
u_int8_t wb_phy_addr; /* PHY address */
u_int8_t wb_tx_pend; /* TX pending */
u_int8_t wb_want_auto;
u_int8_t wb_autoneg;
u_int16_t wb_txthresh;
caddr_t wb_ldata_ptr;
struct wb_list_data *wb_ldata;
struct wb_chain_data wb_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
#define WB_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* Winbond PCI vendor ID
*/
#define WB_VENDORID 0x1050
/*
* Winbond device IDs.
*/
#define WB_DEVICEID_840F 0x0840
/*
* Compex vendor ID.
*/
#define CP_VENDORID 0x11F6
/*
* Compex device IDs.
*/
#define CP_DEVICEID_RL100 0x2011
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers. Note: some are only available on
* the 3c905B, in particular those that related to power management.
*/
#define WB_PCI_VENDOR_ID 0x00
#define WB_PCI_DEVICE_ID 0x02
#define WB_PCI_COMMAND 0x04
#define WB_PCI_STATUS 0x06
#define WB_PCI_CLASSCODE 0x09
#define WB_PCI_LATENCY_TIMER 0x0D
#define WB_PCI_HEADER_TYPE 0x0E
#define WB_PCI_LOIO 0x10
#define WB_PCI_LOMEM 0x14
#define WB_PCI_BIOSROM 0x30
#define WB_PCI_INTLINE 0x3C
#define WB_PCI_INTPIN 0x3D
#define WB_PCI_MINGNT 0x3E
#define WB_PCI_MINLAT 0x0F
#define WB_PCI_RESETOPT 0x48
#define WB_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define WB_PCI_CAPID 0xDC /* 8 bits */
#define WB_PCI_NEXTPTR 0xDD /* 8 bits */
#define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define WB_PSTATE_MASK 0x0003
#define WB_PSTATE_D0 0x0000
#define WB_PSTATE_D1 0x0002
#define WB_PSTATE_D2 0x0002
#define WB_PSTATE_D3 0x0003
#define WB_PME_EN 0x0010
#define WB_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define WB_PHYADDR_MIN 0x00
#define WB_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001

6
usr.sbin/sade/devices.c
View File

@ -4,7 +4,7 @@
* This is probably the last program in the `sysinstall' line - the next
* generation being essentially a complete rewrite.
*
* $Id: devices.c,v 1.85 1998/10/18 16:24:20 wpaul Exp $
* $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $
*
* Copyright (c) 1995
* Jordan Hubbard. All rights reserved.
@ -95,10 +95,14 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "tx", "SMC 9432TX ethernet card" },
{ DEVICE_TYPE_NETWORK, "tl", "Texas Instruments ThunderLAN PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vr", "VIA VT3043/VT86C100A Rhine PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vx", "3COM 3c590 / 3c595 ethernet card" },
{ DEVICE_TYPE_NETWORK, "wb", "Winbond W89C840F PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "xl", "3COM 3c90x / 3c90xB PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ze", "IBM/National Semiconductor PCMCIA ethernet card" },
{ DEVICE_TYPE_NETWORK, "zp", "3Com Etherlink III PCMCIA ethernet card" },

6
usr.sbin/sysinstall/devices.c
View File

@ -4,7 +4,7 @@
* This is probably the last program in the `sysinstall' line - the next
* generation being essentially a complete rewrite.
*
* $Id: devices.c,v 1.85 1998/10/18 16:24:20 wpaul Exp $
* $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $
*
* Copyright (c) 1995
* Jordan Hubbard. All rights reserved.
@ -95,10 +95,14 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "tx", "SMC 9432TX ethernet card" },
{ DEVICE_TYPE_NETWORK, "tl", "Texas Instruments ThunderLAN PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vr", "VIA VT3043/VT86C100A Rhine PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "vx", "3COM 3c590 / 3c595 ethernet card" },
{ DEVICE_TYPE_NETWORK, "wb", "Winbond W89C840F PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "xl", "3COM 3c90x / 3c90xB PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ze", "IBM/National Semiconductor PCMCIA ethernet card" },
{ DEVICE_TYPE_NETWORK, "zp", "3Com Etherlink III PCMCIA ethernet card" },